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| author | sandra <sandra@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-08-04 22:16:57 +0000 |
|---|---|---|
| committer | sandra <sandra@138bc75d-0d04-0410-961f-82ee72b054a4> | 2012-08-04 22:16:57 +0000 |
| commit | 1c7d277e91da2159a52051bfc718040063b6dc3b (patch) | |
| tree | da47f76914b6c01896328ee7efd5b97c6d9400d7 | |
| parent | bb8a250735f21bdce77137e7cf7bb2e435ca8a21 (diff) | |
| download | ppe42-gcc-1c7d277e91da2159a52051bfc718040063b6dc3b.tar.gz ppe42-gcc-1c7d277e91da2159a52051bfc718040063b6dc3b.zip | |
2012-08-04 Catherine Moore <clm@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
gcc/
* config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation.
(ir_xlr_alu): Remove clz.
* config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@190146 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips-cpus.def | 2 | ||||
| -rw-r--r-- | gcc/config/mips/xlr.md | 7 |
3 files changed, 14 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c849368db0a..b8f0a86a0f8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2012-08-04 Catherine Moore <clm@codesourcery.com> + Sandra Loosemore <sandra@codesourcery.com> + + * config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation. + (ir_xlr_alu): Remove clz. + * config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY. + 2012-08-04 Richard Earnshaw <rearnsha@arm.com> * arm.c (arm_gen_constant): Use SImode when preparing operands for diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 62b1a19062e..e8dc5a7a036 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -142,7 +142,7 @@ MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY) -MIPS_CPU ("xlr", PROCESSOR_XLR, 64, 0) +MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY) /* MIPS64 Release 2 processors. */ diff --git a/gcc/config/mips/xlr.md b/gcc/config/mips/xlr.md index 14204694d5d..59f863323f2 100644 --- a/gcc/config/mips/xlr.md +++ b/gcc/config/mips/xlr.md @@ -28,10 +28,15 @@ (eq_attr "type" "slt")) "xlr_main_pipe") +(define_insn_reservation "ir_xlr_alu_clz" 2 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "clz")) + "xlr_main_pipe") + ;; Integer arithmetic instructions. (define_insn_reservation "ir_xlr_alu" 1 (and (eq_attr "cpu" "xlr") - (eq_attr "type" "move,arith,shift,clz,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop")) + (eq_attr "type" "move,arith,shift,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop")) "xlr_main_pipe") ;; Integer arithmetic instructions. |
