[Patch ARM] Add "type" attribute to Everything!

gcc/
	* config/arm/types.md: Add "no_insn", "multiple" and "untyped"
	types.
	* config/arm/arm-fixed.md: Add type attribute to all insn
	patterns.
	* config/arm/vfp.md: Add type attribute to all insn patterns.
	* config/arm/arm.md: Add type attribute to all insn patterns.
	* config/arm/thumb2.md: Add type attribute to all insn patterns.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/arm1026ejs.md: Update with new attributes.
	* config/arm/arm1136jfs.md: Update with new attributes.
	* config/arm/arm926ejs.md: Update with new attributes.
	* config/arm/cortex-a15.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4.md: Update with new attributes.
	* config/arm/cortex-r4.md: Update with new attributes.
	* config/arm/fa526.md: Update with new attributes.
	* config/arm/fa606te.md: Update with new attributes.
	* config/arm/fa626te.md: Update with new attributes.
	* config/arm/fa726te.md: Update with new attributes.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@202323 138bc75d-0d04-0410-961f-82ee72b054a4

22 files changed, 752 insertions, 260 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 667e1189171..28b0896f7d2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,269 @@
 2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>
 
+	* config/arm/types.md: Add "no_insn", "multiple" and "untyped"
+	types.
+	* config/arm/arm-fixed.md: Add type attribute to all insn
+	patterns.
+	(add<mode>3): Add type attribute.
+	(add<mode>3): Likewise.
+	(usadd<mode>3): Likewise.
+	(ssadd<mode>3): Likewise.
+	(sub<mode>3): Likewise.
+	(sub<mode>3): Likewise.
+	(ussub<mode>3): Likewise.
+	(sssub<mode>3): Likewise.
+	(ssmulsa3): Likewise.
+	(usmulusa3): Likewise.
+	(arm_usatsihi): Likewise.
+	* config/arm/vfp.md
+	(*movdi_vfp): Add types for all instructions.
+	(*movdi_vfp_cortexa8): Likewise.
+	(*movhf_vfp_neon): Likewise.
+	(*movhf_vfp): Likewise.
+	(*movdf_vfp): Likewise.
+	(*thumb2_movdf_vfp): Likewise.
+	(*thumb2_movdfcc_vfp): Likewise.
+	* config/arm/arm.md: Add type attribute to all insn patterns.
+	(*thumb1_adddi3): Add type attribute.
+	(*arm_adddi3): Likewise.
+	(*adddi_sesidi_di): Likewise.
+	(*adddi_zesidi_di): Likewise.
+	(*thumb1_addsi3): Likewise.
+	(addsi3_compare0): Likewise.
+	(*addsi3_compare0_scratch): Likewise.
+	(*compare_negsi_si): Likewise.
+	(cmpsi2_addneg): Likewise.
+	(*addsi3_carryin_<optab>): Likewise.
+	(*addsi3_carryin_alt2_<optab>): Likewise.
+	(*addsi3_carryin_clobercc_<optab>): Likewise.
+	(*subsi3_carryin): Likewise.
+	(*subsi3_carryin_const): Likewise.
+	(*subsi3_carryin_compare): Likewise.
+	(*subsi3_carryin_compare_const): Likewise.
+	(*arm_subdi3): Likewise.
+	(*thumb_subdi3): Likewise.
+	(*subdi_di_zesidi): Likewise.
+	(*subdi_di_sesidi): Likewise.
+	(*subdi_zesidi_di): Likewise.
+	(*subdi_sesidi_di): Likewise.
+	(*subdi_zesidi_ze): Likewise.
+	(thumb1_subsi3_insn): Likewise.
+	(*arm_subsi3_insn): Likewise.
+	(*anddi3_insn): Likewise.
+	(*anddi_zesidi_di): Likewise.
+	(*anddi_sesdi_di): Likewise.
+	(*ne_zeroextracts): Likewise.
+	(*ne_zeroextracts): Likewise.
+	(*ite_ne_zeroextr): Likewise.
+	(*ite_ne_zeroextr): Likewise.
+	(*anddi_notdi_di): Likewise.
+	(*anddi_notzesidi): Likewise.
+	(*anddi_notsesidi): Likewise.
+	(andsi_notsi_si): Likewise.
+	(thumb1_bicsi3): Likewise.
+	(*iordi3_insn): Likewise.
+	(*iordi_zesidi_di): Likewise.
+	(*iordi_sesidi_di): Likewise.
+	(*thumb1_iorsi3_insn): Likewise.
+	(*xordi3_insn): Likewise.
+	(*xordi_zesidi_di): Likewise.
+	(*xordi_sesidi_di): Likewise.
+	(*arm_xorsi3): Likewise.
+	(*andsi_iorsi3_no): Likewise.
+	(*smax_0): Likewise.
+	(*smax_m1): Likewise.
+	(*arm_smax_insn): Likewise.
+	(*smin_0): Likewise.
+	(*arm_smin_insn): Likewise.
+	(*arm_umaxsi3): Likewise.
+	(*arm_uminsi3): Likewise.
+	(*minmax_arithsi): Likewise.
+	(*minmax_arithsi_): Likewise.
+	(*satsi_<SAT:code>): Likewise.
+	(arm_ashldi3_1bit): Likewise.
+	(arm_ashrdi3_1bit): Likewise.
+	(arm_lshrdi3_1bit): Likewise.
+	(*arm_negdi2): Likewise.
+	(*thumb1_negdi2): Likewise.
+	(*arm_negsi2): Likewise.
+	(*thumb1_negsi2): Likewise.
+	(*negdi_extendsid): Likewise.
+	(*negdi_zero_extend): Likewise.
+	(*arm_abssi2): Likewise.
+	(*thumb1_abssi2): Likewise.
+	(*arm_neg_abssi2): Likewise.
+	(*thumb1_neg_abss): Likewise.
+	(one_cmpldi2): Likewise.
+	(extend<mode>di2): Likewise.
+	(*compareqi_eq0): Likewise.
+	(*arm_extendhisi2addsi): Likewise.
+	(*arm_movdi): Likewise.
+	(*thumb1_movdi_insn): Likewise.
+	(*arm_movt): Likewise.
+	(*thumb1_movsi_insn): Likewise.
+	(pic_add_dot_plus_four): Likewise.
+	(pic_add_dot_plus_eight): Likewise.
+	(tls_load_dot_plus_eight): Likewise.
+	(*thumb1_movhi_insn): Likewise.
+	(*thumb1_movsf_insn): Likewise.
+	(*movdf_soft_insn): Likewise.
+	(*thumb_movdf_insn): Likewise.
+	(cbranchsi4_insn): Likewise.
+	(cbranchsi4_scratch): Likewise.
+	(*negated_cbranchsi4): Likewise.
+	(*tbit_cbranch): Likewise.
+	(*tlobits_cbranch): Likewise.
+	(*tstsi3_cbranch): Likewise.
+	(*cbranchne_decr1): Likewise.
+	(*addsi3_cbranch): Likewise.
+	(*addsi3_cbranch_scratch): Likewise.
+	(*arm_cmpdi_insn): Likewise.
+	(*arm_cmpdi_unsig): Likewise.
+	(*arm_cmpdi_zero): Likewise.
+	(*thumb_cmpdi_zero): Likewise.
+	(*deleted_compare): Likewise.
+	(*mov_scc): Likewise.
+	(*mov_negscc): Likewise.
+	(*mov_notscc): Likewise.
+	(*cstoresi_eq0_thumb1_insn): Likewise.
+	(cstoresi_nltu_thumb1): Likewise.
+	(cstoresi_ltu_thu): Likewise.
+	(thumb1_addsi3_addgeu): Likewise.
+	(*arm_jump): Likewise.
+	(*thumb_jump): Likewise.
+	(*check_arch2): Likewise.
+	(arm_casesi_internal): Likewise.
+	(thumb1_casesi_dispatch): Likewise.
+	(*arm_indirect_jump): Likewise.
+	(*thumb1_indirect_jump): Likewise.
+	(nop): Likewise.
+	(*and_scc): Likewise.
+	(*ior_scc): Likewise.
+	(*compare_scc): Likewise.
+	(*cond_move): Likewise.
+	(*cond_arith): Likewise.
+	(*cond_sub): Likewise.
+	(*cmp_ite0): Likewise.
+	(*cmp_ite1): Likewise.
+	(*cmp_and): Likewise.
+	(*cmp_ior): Likewise.
+	(*ior_scc_scc): Likewise.
+	(*ior_scc_scc_cmp): Likewise.
+	(*and_scc_scc): Likewise.
+	(*and_scc_scc_cmp): Likewise.
+	(*and_scc_scc_nod): Likewise.
+	(*negscc): Likewise.
+	(movcond_addsi): Likewise.
+	(movcond): Likewise.
+	(*ifcompare_plus_move): Likewise.
+	(*if_plus_move): Likewise.
+	(*ifcompare_move_plus): Likewise.
+	(*if_move_plus): Likewise.
+	(*ifcompare_arith_arith): Likewise.
+	(*if_arith_arith): Likewise.
+	(*ifcompare_arith_move): Likewise.
+	(*if_arith_move): Likewise.
+	(*ifcompare_move_arith): Likewise.
+	(*if_move_arith): Likewise.
+	(*ifcompare_move_not): Likewise.
+	(*if_move_not): Likewise.
+	(*ifcompare_not_move): Likewise.
+	(*if_not_move): Likewise.
+	(*ifcompare_shift_move): Likewise.
+	(*if_shift_move): Likewise.
+	(*ifcompare_move_shift): Likewise.
+	(*if_move_shift): Likewise.
+	(*ifcompare_shift_shift): Likewise.
+	(*ifcompare_not_arith): Likewise.
+	(*ifcompare_arith_not): Likewise.
+	(*if_arith_not): Likewise.
+	(*ifcompare_neg_move): Likewise.
+	(*if_neg_move): Likewise.
+	(*ifcompare_move_neg): Likewise.
+	(*if_move_neg): Likewise.
+	(prologue_thumb1_interwork): Likewise.
+	(*cond_move_not): Likewise.
+	(*sign_extract_onebit): Likewise.
+	(*not_signextract_onebit): Likewise.
+	(stack_tie): Likewise.
+	(align_4): Likewise.
+	(align_8): Likewise.
+	(consttable_end): Likewise.
+	(consttable_1): Likewise.
+	(consttable_2): Likewise.
+	(consttable_4): Likewise.
+	(consttable_8): Likewise.
+	(consttable_16): Likewise.
+	(*thumb1_tablejump): Likewise.
+	(prefetch): Likewise.
+	(force_register_use): Likewise.
+	(thumb_eh_return): Likewise.
+	(load_tp_hard): Likewise.
+	(load_tp_soft): Likewise.
+	(tlscall): Likewise.
+	(*arm_movtas_ze): Likewise.
+	(*arm_rev): Likewise.
+	(*arm_revsh): Likewise.
+	(*arm_rev16): Likewise.
+	* config/arm/thumb2.md
+	(*thumb2_smaxsi3): Likewise.
+	(*thumb2_sminsi3): Likewise.
+	(*thumb32_umaxsi3): Likewise.
+	(*thumb2_uminsi3): Likewise.
+	(*thumb2_negdi2): Likewise.
+	(*thumb2_abssi2): Likewise.
+	(*thumb2_neg_abss): Likewise.
+	(*thumb2_movsi_insn): Likewise.
+	(tls_load_dot_plus_four): Likewise.
+	(*thumb2_movhi_insn): Likewise.
+	(*thumb2_mov_scc): Likewise.
+	(*thumb2_mov_negs): Likewise.
+	(*thumb2_mov_negs): Likewise.
+	(*thumb2_mov_nots): Likewise.
+	(*thumb2_mov_nots): Likewise.
+	(*thumb2_movsicc_): Likewise.
+	(*thumb2_movsfcc_soft_insn): Likewise.
+	(*thumb2_indirect_jump): Likewise.
+	(*thumb2_and_scc): Likewise.
+	(*thumb2_ior_scc): Likewise.
+	(*thumb2_ior_scc_strict_it): Likewise.
+	(*thumb2_cond_move): Likewise.
+	(*thumb2_cond_arith): Likewise.
+	(*thumb2_cond_ari): Likewise.
+	(*thumb2_cond_sub): Likewise.
+	(*thumb2_negscc): Likewise.
+	(*thumb2_movcond): Likewise.
+	(thumb2_casesi_internal): Likewise.
+	(thumb2_casesi_internal_pic): Likewise.
+	(*thumb2_alusi3_short): Likewise.
+	(*thumb2_mov<mode>_shortim): Likewise.
+	(*thumb2_addsi_short): Likewise.
+	(*thumb2_subsi_short): Likewise.
+	(thumb2_addsi3_compare0): Likewise.
+	(*thumb2_cbz): Likewise.
+	(*thumb2_cbnz): Likewise.
+	(*thumb2_one_cmplsi2_short): Likewise.
+	(*thumb2_negsi2_short): Likewise.
+	(*orsi_notsi_si): Likewise.
+	* config/arm/arm1020e.md: Update with new attributes.
+	* config/arm/arm1026ejs.md: Update with new attributes.
+	* config/arm/arm1136jfs.md: Update with new attributes.
+	* config/arm/arm926ejs.md: Update with new attributes.
+	* config/arm/cortex-a15.md: Update with new attributes.
+	* config/arm/cortex-a5.md: Update with new attributes.
+	* config/arm/cortex-a53.md: Update with new attributes.
+	* config/arm/cortex-a7.md: Update with new attributes.
+	* config/arm/cortex-a8.md: Update with new attributes.
+	* config/arm/cortex-a9.md: Update with new attributes.
+	* config/arm/cortex-m4.md: Update with new attributes.
+	* config/arm/cortex-r4.md: Update with new attributes.
+	* config/arm/fa526.md: Update with new attributes.
+	* config/arm/fa606te.md: Update with new attributes.
+	* config/arm/fa626te.md: Update with new attributes.
+	* config/arm/fa726te.md: Update with new attributes.
+
+2013-09-06  James Greenhalgh  <james.greenhalgh@arm.com>
+
 	* config/aarch64/aarch64-simd.md
 	(aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use
 	<vwx> iterator to ensure correct register choice.
diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md
index f17fa884e31..3972a850990 100644
--- a/gcc/config/arm/arm-fixed.md
+++ b/gcc/config/arm/arm-fixed.md
@@ -25,7 +25,8 @@
   "TARGET_32BIT"
   "add%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "yes,no")])
+   (set_attr "predicable_short_it" "yes,no")
+   (set_attr "type" "alu_reg")])
 
 (define_insn "add<mode>3"
   [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
@@ -34,7 +35,8 @@
   "TARGET_INT_SIMD"
   "sadd<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")])
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alu_reg")])
 
 (define_insn "usadd<mode>3"
   [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
@@ -43,7 +45,8 @@
   "TARGET_INT_SIMD"
   "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")])
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alu_reg")])
 
 (define_insn "ssadd<mode>3"
   [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
@@ -52,7 +55,8 @@
   "TARGET_INT_SIMD"
   "qadd<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")])
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alu_reg")])
 
 (define_insn "sub<mode>3"
   [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
@@ -61,7 +65,8 @@
   "TARGET_32BIT"
   "sub%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "yes,no")])
+   (set_attr "predicable_short_it" "yes,no")
+   (set_attr "type" "alu_reg")])
 
 (define_insn "sub<mode>3"
   [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
@@ -70,7 +75,8 @@
   "TARGET_INT_SIMD"
   "ssub<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")])
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alu_reg")])
 
 (define_insn "ussub<mode>3"
   [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
@@ -80,7 +86,8 @@
   "TARGET_INT_SIMD"
   "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")])
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alu_reg")])
 
 (define_insn "sssub<mode>3"
   [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
@@ -89,7 +96,8 @@
   "TARGET_INT_SIMD"
   "qsub<qaddsub_suf>%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")])
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alu_reg")])
 
 ;; Fractional multiplies.
 
@@ -246,6 +254,7 @@
   return "";
 }
   [(set_attr "conds" "clob")
+   (set_attr "type" "multiple")
    (set (attr "length")
 	(if_then_else (eq_attr "is_thumb" "yes")
 		      (if_then_else (match_test "arm_restrict_it")
@@ -305,6 +314,7 @@
   return "";
 }
   [(set_attr "conds" "clob")
+   (set_attr "type" "multiple")
    (set (attr "length")
 	(if_then_else (eq_attr "is_thumb" "yes")
 		      (if_then_else (match_test "arm_restrict_it")
@@ -414,5 +424,6 @@
   "TARGET_INT_SIMD"
   "usat%?\\t%0, #16, %1"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alu_imm")]
 )
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4fb12aac35b..5ed8ee7dc62 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -461,7 +461,8 @@
   ]
   "TARGET_THUMB1"
   "add\\t%Q0, %Q0, %Q2\;adc\\t%R0, %R0, %R2"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*arm_adddi3"
@@ -489,7 +490,8 @@
     operands[2] = gen_lowpart (SImode, operands[2]);
   }"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*adddi_sesidi_di"
@@ -518,7 +520,8 @@
     operands[2] = gen_lowpart (SImode, operands[2]);
   }"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*adddi_zesidi_di"
@@ -545,7 +548,8 @@
     operands[2] = gen_lowpart (SImode, operands[2]);
   }"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "addsi3"
@@ -671,7 +675,9 @@
     operands[3] = GEN_INT (offset);
     operands[2] = GEN_INT (INTVAL (operands[2]) - offset);
   }
-  [(set_attr "length" "2,2,2,2,2,2,2,4,4,4")]
+  [(set_attr "length" "2,2,2,2,2,2,2,4,4,4")
+   (set_attr "type" "alus_imm,alus_imm,alus_reg,alus_reg,alus_reg,
+		     alus_reg,alus_reg,multiple,multiple,multiple")]
 )
 
 ;; Reloading and elimination of the frame pointer can
@@ -702,7 +708,7 @@
    sub%.\\t%0, %1, #%n2
    add%.\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "alus_imm,alus_imm,*")]
+   (set_attr "type" "alus_imm,alus_imm,alus_reg")]
 )
 
 (define_insn "*addsi3_compare0_scratch"
@@ -718,8 +724,7 @@
    cmn%?\\t%0, %1"
   [(set_attr "conds" "set")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alus_imm,alus_imm,*")
-   ]
+   (set_attr "type" "alus_imm,alus_imm,alus_reg")]
 )
 
 (define_insn "*compare_negsi_si"
@@ -733,7 +738,8 @@
    (set_attr "predicable" "yes")
    (set_attr "arch" "t2,*")
    (set_attr "length" "2,4")
-   (set_attr "predicable_short_it" "yes,no")]
+   (set_attr "predicable_short_it" "yes,no")
+   (set_attr "type" "alus_reg")]
 )
 
 ;; This is the canonicalization of addsi3_compare0_for_combiner when the
@@ -750,7 +756,8 @@
   "@
    add%.\\t%0, %1, %3
    sub%.\\t%0, %1, #%n3"
-  [(set_attr "conds" "set")]
+  [(set_attr "conds" "set")
+   (set_attr "type" "alus_reg")]
 )
 
 ;; Convert the sequence
@@ -884,7 +891,8 @@
    (set_attr "predicable" "yes")
    (set_attr "arch" "t2,*,*")
    (set_attr "length" "4")
-   (set_attr "predicable_short_it" "yes,no,no")]
+   (set_attr "predicable_short_it" "yes,no,no")
+   (set_attr "type" "adc_reg,adc_reg,adc_imm")]
 )
 
 (define_insn "*addsi3_carryin_alt2_<optab>"
@@ -901,7 +909,8 @@
    (set_attr "predicable" "yes")
    (set_attr "arch" "t2,*,*")
    (set_attr "length" "4")
-   (set_attr "predicable_short_it" "yes,no,no")]
+   (set_attr "predicable_short_it" "yes,no,no")
+   (set_attr "type" "adc_reg,adc_reg,adc_imm")]
 )
 
 (define_insn "*addsi3_carryin_shift_<optab>"
@@ -930,7 +939,8 @@
    (clobber (reg:CC CC_REGNUM))]
    "TARGET_32BIT"
    "adc%.\\t%0, %1, %2"
-   [(set_attr "conds" "set")]
+   [(set_attr "conds" "set")
+    (set_attr "type" "adcs_reg")]
 )
 
 (define_insn "*subsi3_carryin"
@@ -945,7 +955,8 @@
   [(set_attr "conds" "use")
    (set_attr "arch" "*,a")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "adc_reg,adc_imm")]
 )
 
 (define_insn "*subsi3_carryin_const"
@@ -955,7 +966,8 @@
                   (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
   "TARGET_32BIT"
   "sbc\\t%0, %1, #%B2"
-  [(set_attr "conds" "use")]
+  [(set_attr "conds" "use")
+   (set_attr "type" "adc_imm")]
 )
 
 (define_insn "*subsi3_carryin_compare"
@@ -968,7 +980,8 @@
                   (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
   "TARGET_32BIT"
   "sbcs\\t%0, %1, %2"
-  [(set_attr "conds" "set")]
+  [(set_attr "conds" "set")
+   (set_attr "type" "adcs_reg")]
 )
 
 (define_insn "*subsi3_carryin_compare_const"
@@ -981,7 +994,8 @@
                   (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
   "TARGET_32BIT"
   "sbcs\\t%0, %1, #%B2"
-  [(set_attr "conds" "set")]
+  [(set_attr "conds" "set")
+   (set_attr "type" "adcs_imm")]
 )
 
 (define_insn "*subsi3_carryin_shift"
@@ -1088,7 +1102,8 @@
     operands[2] = gen_lowpart (SImode, operands[2]);
    }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb_subdi3"
@@ -1098,7 +1113,8 @@
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_THUMB1"
   "sub\\t%Q0, %Q0, %Q2\;sbc\\t%R0, %R0, %R2"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*subdi_di_zesidi"
@@ -1123,7 +1139,8 @@
     operands[5] = GEN_INT (~0);
    }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*subdi_di_sesidi"
@@ -1149,7 +1166,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*subdi_zesidi_di"
@@ -1175,7 +1193,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*subdi_sesidi_di"
@@ -1204,7 +1223,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*subdi_zesidi_zesidi"
@@ -1227,7 +1247,8 @@
        operands[0] = gen_lowpart (SImode, operands[0]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "subsi3"
@@ -1258,7 +1279,9 @@
   "TARGET_THUMB1"
   "sub\\t%0, %1, %2"
   [(set_attr "length" "2")
-   (set_attr "conds" "set")])
+   (set_attr "conds" "set")
+   (set_attr "type" "alus_reg")]
+)
 
 ; ??? Check Thumb-2 split length
 (define_insn_and_split "*arm_subsi3_insn"
@@ -1288,7 +1311,7 @@
    (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
-   (set_attr "type"  "*,*,*,*,alu_imm,alu_imm,*,*,alu_imm")]
+   (set_attr "type" "alu_reg,alu_reg,alu_reg,alu_reg,alu_imm,alu_imm,alu_reg,alu_reg,multiple")]
 )
 
 (define_peephole2
@@ -2140,7 +2163,7 @@
                                            gen_highpart_mode (SImode, DImode, operands[2]));
 
   }"
-  [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
+  [(set_attr "type" "neon_int_1,neon_int_1,multiple,multiple,multiple,multiple,neon_int_1,neon_int_1")
    (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,
                      avoid_neon_for_64bits,avoid_neon_for_64bits")
    (set_attr "length" "*,*,8,8,8,8,*,*")
@@ -2165,7 +2188,8 @@
     operands[0] = gen_lowpart (SImode, operands[0]);
     operands[1] = gen_lowpart (SImode, operands[1]);
   }"
-  [(set_attr "length" "8")]
+  [(set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*anddi_sesdi_di"
@@ -2175,7 +2199,8 @@
 		(match_operand:DI  1 "s_register_operand" "0,r")))]
   "TARGET_32BIT"
   "#"
-  [(set_attr "length" "8")]
+  [(set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "andsi3"
@@ -2386,7 +2411,8 @@
    (set (attr "length")
 	(if_then_else (eq_attr "is_thumb" "yes")
 		      (const_int 12)
-		      (const_int 8)))]
+		      (const_int 8)))
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*ne_zeroextractsi_shifted"
@@ -2411,7 +2437,8 @@
   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*ite_ne_zeroextractsi"
@@ -2449,7 +2476,8 @@
 			 << INTVAL (operands[3])); 
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*ite_ne_zeroextractsi_shifted"
@@ -2476,7 +2504,8 @@
   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_split
@@ -2816,7 +2845,8 @@
     operands[2] = gen_lowpart (SImode, operands[2]);
   }"
   [(set_attr "length" "8")
-   (set_attr "predicable" "yes")]
+   (set_attr "predicable" "yes")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*anddi_notzesidi_di"
@@ -2844,7 +2874,8 @@
   }"
   [(set_attr "length" "4,8")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*anddi_notsesidi_di"
@@ -2868,7 +2899,8 @@
   }"
   [(set_attr "length" "8")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "andsi_notsi_si"
@@ -2878,7 +2910,8 @@
   "TARGET_32BIT"
   "bic%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_reg")]
 )
 
 (define_insn "thumb1_bicsi3"
@@ -2888,7 +2921,9 @@
   "TARGET_THUMB1"
   "bic\\t%0, %1"
   [(set_attr "length" "2")
-   (set_attr "conds" "set")])
+   (set_attr "conds" "set")
+   (set_attr "type" "logics_reg")]
+)
 
 (define_insn "andsi_not_shiftsi_si"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
@@ -2978,7 +3013,7 @@
                                            gen_highpart_mode (SImode, DImode, operands[2]));
 
   }"
-  [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
+  [(set_attr "type" "neon_int_1,neon_int_1,multiple,multiple,multiple,multiple,neon_int_1,neon_int_1")
    (set_attr "length" "*,*,8,8,8,8,*,*")
    (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
 )
@@ -2994,7 +3029,8 @@
    #"
   [(set_attr "length" "4,8")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_reg,multiple")]
 )
 
 (define_insn "*iordi_sesidi_di"
@@ -3005,7 +3041,8 @@
   "TARGET_32BIT"
   "#"
   [(set_attr "length" "8")
-   (set_attr "predicable" "yes")]
+   (set_attr "predicable" "yes")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "iorsi3"
@@ -3073,7 +3110,8 @@
   "TARGET_THUMB1"
   "orr\\t%0, %2"
   [(set_attr "length" "2")
-   (set_attr "conds" "set")])
+   (set_attr "conds" "set")
+   (set_attr "type" "logics_reg")])
 
 (define_peephole2
   [(match_scratch:SI 3 "r")
@@ -3157,7 +3195,7 @@
 
   }"
   [(set_attr "length" "*,8,8,8,8,*")
-   (set_attr "type" "neon_int_1,*,*,*,*,neon_int_1")
+   (set_attr "type" "neon_int_1,multiple,multiple,multiple,multiple,neon_int_1")
    (set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")]
 )
 
@@ -3172,7 +3210,8 @@
    #"
   [(set_attr "length" "4,8")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_reg")]
 )
 
 (define_insn "*xordi_sesidi_di"
@@ -3183,7 +3222,8 @@
   "TARGET_32BIT"
   "#"
   [(set_attr "length" "8")
-   (set_attr "predicable" "yes")]
+   (set_attr "predicable" "yes")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "xorsi3"
@@ -3236,7 +3276,7 @@
   [(set_attr "length" "4,4,4,16")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no,yes,no,no")
-   (set_attr "type"  "logic_imm,logic_reg,logic_reg,logic_reg")]
+   (set_attr "type"  "logic_imm,logic_reg,logic_reg,multiple")]
 )
 
 (define_insn "*thumb1_xorsi3_insn"
@@ -3305,7 +3345,8 @@
   [(set_attr "length" "8")
    (set_attr "ce_count" "2")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "multiple")]
 )
 
 ; ??? Are these four splitters still beneficial when the Thumb-2 bitfield
@@ -3442,7 +3483,8 @@
   "TARGET_32BIT"
   "bic%?\\t%0, %1, %1, asr #31"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_shift_reg")]
 )
 
 (define_insn "*smax_m1"
@@ -3452,7 +3494,8 @@
   "TARGET_32BIT"
   "orr%?\\t%0, %1, %1, asr #31"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_shift_reg")]
 )
 
 (define_insn_and_split "*arm_smax_insn"
@@ -3473,7 +3516,8 @@
                          (match_dup 2)))]
   ""
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "sminsi3"
@@ -3501,7 +3545,8 @@
   "TARGET_32BIT"
   "and%?\\t%0, %1, %1, asr #31"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_shift_reg")]
 )
 
 (define_insn_and_split "*arm_smin_insn"
@@ -3522,7 +3567,8 @@
                          (match_dup 2)))]
   ""
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple,multiple")]
 )
 
 (define_expand "umaxsi3"
@@ -3554,7 +3600,8 @@
                          (match_dup 2)))]
   ""
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,8,12")]
+   (set_attr "length" "8,8,12")
+   (set_attr "type" "store1")]
 )
 
 (define_expand "uminsi3"
@@ -3586,7 +3633,8 @@
                          (match_dup 2)))]
   ""
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,8,12")]
+   (set_attr "length" "8,8,12")
+   (set_attr "type" "store1")]
 )
 
 (define_insn "*store_minmaxsi"
@@ -3655,7 +3703,8 @@
    (set (attr "length")
 	(if_then_else (eq_attr "is_thumb" "yes")
 		      (const_int 14)
-		      (const_int 12)))]
+		      (const_int 12)))
+   (set_attr "type" "multiple")]
 )
 
 ; Reject the frame pointer in operand[1], since reloading this after
@@ -3703,7 +3752,8 @@
    (set (attr "length")
 	(if_then_else (eq_attr "is_thumb" "yes")
 		      (const_int 14)
-		      (const_int 12)))]
+		      (const_int 12)))
+   (set_attr "type" "multiple")]
 )
 
 (define_code_iterator SAT [smin smax])
@@ -3732,7 +3782,8 @@
     return "usat%?\t%0, %1, %3";
 }
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "alus_imm")]
 )
 
 (define_insn "*satsi_<SAT:code>_shift"
@@ -3838,7 +3889,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "ashlsi3"
@@ -3935,7 +3987,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*rrx"
@@ -4040,7 +4093,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "lshrsi3"
@@ -4593,7 +4647,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb1_negdi2"
@@ -4602,7 +4657,8 @@
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_THUMB1"
   "mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"
-  [(set_attr "length" "6")]
+  [(set_attr "length" "6")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "negsi2"
@@ -4620,7 +4676,8 @@
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,no")
    (set_attr "arch" "t2,*")
-   (set_attr "length" "4")]
+   (set_attr "length" "4")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_insn "*thumb1_negsi2"
@@ -4628,7 +4685,8 @@
 	(neg:SI (match_operand:SI 1 "register_operand" "l")))]
   "TARGET_THUMB1"
   "neg\\t%0, %1"
-  [(set_attr "length" "2")]
+  [(set_attr "length" "2")
+   (set_attr "type" "alu_imm")]
 )
 
 (define_expand "negsf2"
@@ -4686,7 +4744,8 @@
      DONE;
   }
   [(set_attr "length" "8,8,4,4")
-   (set_attr "arch" "a,a,t2,t2")]
+   (set_attr "arch" "a,a,t2,t2")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*negdi_zero_extendsidi"
@@ -4708,7 +4767,8 @@
     operands[0] = gen_lowpart (SImode, operands[0]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]   ;; length in thumb is 4
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]   ;; length in thumb is 4
 )
 
 ;; abssi2 doesn't really clobber the condition codes if a different register
@@ -4793,7 +4853,8 @@
   [(set_attr "conds" "clob,*")
    (set_attr "shift" "1")
    (set_attr "predicable" "no, yes")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb1_abssi2"
@@ -4807,7 +4868,8 @@
    (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
   ""
-  [(set_attr "length" "6")]
+  [(set_attr "length" "6")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*arm_neg_abssi2"
@@ -4863,7 +4925,8 @@
   [(set_attr "conds" "clob,*")
    (set_attr "shift" "1")
    (set_attr "predicable" "no, yes")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb1_neg_abssi2"
@@ -4877,7 +4940,8 @@
    (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))
    (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
   ""
-  [(set_attr "length" "6")]
+  [(set_attr "length" "6")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "abssf2"
@@ -4926,7 +4990,7 @@
   }"
   [(set_attr "length" "*,8,8,*")
    (set_attr "predicable" "no,yes,yes,no")
-   (set_attr "type" "neon_int_1,*,*,neon_int_1")
+   (set_attr "type" "neon_int_1,multiple,multiple,neon_int_1")
    (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")]
 )
 
@@ -5113,7 +5177,8 @@
    (set_attr "ce_count" "2")
    (set_attr "shift" "1")
    (set_attr "predicable" "yes")
-   (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")]
+   (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")
+   (set_attr "type" "multiple,mov_reg,multiple,multiple,multiple")]
 )
 
 ;; Splits for all extensions to DImode
@@ -5418,7 +5483,8 @@
   "tst%?\\t%0, #255"
   [(set_attr "conds" "set")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_imm")]
 )
 
 (define_expand "extendhisi2"
@@ -5615,6 +5681,7 @@
 		 (match_operand:SI 2 "s_register_operand" "r")))]
   "TARGET_INT_SIMD"
   "sxtah%?\\t%0, %2, %1"
+  [(set_attr "type" "alu_shift_reg")]
 )
 
 (define_expand "extendqihi2"
@@ -5935,7 +6002,7 @@
     }
   "
   [(set_attr "length" "8,12,16,8,8")
-   (set_attr "type" "*,*,*,load2,store2")
+   (set_attr "type" "multiple,multiple,multiple,load2,store2")
    (set_attr "arm_pool_range" "*,*,*,1020,*")
    (set_attr "arm_neg_pool_range" "*,*,*,1004,*")
    (set_attr "thumb2_pool_range" "*,*,*,4094,*")
@@ -6075,7 +6142,7 @@
     }
   }"
   [(set_attr "length" "4,4,6,2,2,6,4,4")
-   (set_attr "type" "*,mov_reg,*,load2,store2,load2,store2,mov_reg")
+   (set_attr "type" "multiple,mov_reg,multiple,load2,store2,load2,store2,mov_reg")
    (set_attr "pool_range" "*,*,*,*,*,1018,*,*")]
 )
 
@@ -6173,7 +6240,8 @@
   "movt%?\t%0, #:upper16:%c2"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "length" "4")]
+   (set_attr "length" "4")
+   (set_attr "type" "mov_imm")]
 )
 
 (define_insn "*arm_movsi_insn"
@@ -6245,7 +6313,7 @@
    str\\t%1, %0
    mov\\t%0, %1"
   [(set_attr "length" "2,2,4,4,2,2,2,2,2")
-   (set_attr "type" "*,*,*,*,load1,store1,load1,store1,*")
+   (set_attr "type" "mov_reg,mov_imm,multiple,multiple,load1,store1,load1,store1,mov_reg")
    (set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")
    (set_attr "conds" "set,clob,*,*,nocond,nocond,nocond,nocond,nocond")])
 
@@ -6401,7 +6469,8 @@
 				     INTVAL (operands[2]));
   return \"add\\t%0, %|pc\";
   "
-  [(set_attr "length" "2")]
+  [(set_attr "length" "2")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_insn "pic_add_dot_plus_eight"
@@ -6416,7 +6485,8 @@
 				       INTVAL (operands[2]));
     return \"add%?\\t%0, %|pc, %1\";
   "
-  [(set_attr "predicable" "yes")]
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_insn "tls_load_dot_plus_eight"
@@ -6431,7 +6501,8 @@
 				       INTVAL (operands[2]));
     return \"ldr%?\\t%0, [%|pc, %1]\t\t@ tls_load_dot_plus_eight\";
   "
-  [(set_attr "predicable" "yes")]
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "load1")]
 )
 
 ;; PIC references to local variables can generate pic_add_dot_plus_eight
@@ -6838,7 +6909,7 @@
       return \"ldrh	%0, %1\";
     }"
   [(set_attr "length" "2,4,2,2,2,2")
-   (set_attr "type" "*,load1,store1,*,*,*")
+   (set_attr "type" "alus_imm,load1,store1,mov_reg,mov_reg,mov_imm")
    (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
 
 
@@ -7264,7 +7335,7 @@
    mov\\t%0, %1
    mov\\t%0, %1"
   [(set_attr "length" "2")
-   (set_attr "type" "*,load1,store1,load1,store1,mov_reg,mov_reg")
+   (set_attr "type" "alus_imm,load1,store1,load1,store1,mov_reg,mov_reg")
    (set_attr "pool_range" "*,*,*,1018,*,*,*")
    (set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond,nocond")]
 )
@@ -7352,7 +7423,7 @@
     }
   "
   [(set_attr "length" "8,12,16,8,8")
-   (set_attr "type" "*,*,*,load2,store2")
+   (set_attr "type" "multiple,multiple,multiple,load2,store2")
    (set_attr "arm_pool_range" "*,*,*,1020,*")
    (set_attr "thumb2_pool_range" "*,*,*,1018,*")
    (set_attr "arm_neg_pool_range" "*,*,*,1004,*")
@@ -7396,7 +7467,7 @@
     }
   "
   [(set_attr "length" "4,2,2,6,4,4")
-   (set_attr "type" "*,load2,store2,load2,store2,mov_reg")
+   (set_attr "type" "multiple,load2,store2,load2,store2,mov_reg")
    (set_attr "pool_range" "*,*,*,1018,*,*")]
 )
 
@@ -7704,7 +7775,8 @@
 	        (and (ge (minus (match_dup 3) (pc)) (const_int -2040))
 		     (le (minus (match_dup 3) (pc)) (const_int 2048)))
 		(const_int 6)
-		(const_int 8))))]
+		(const_int 8))))
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "cbranchsi4_scratch"
@@ -7740,7 +7812,8 @@
 	        (and (ge (minus (match_dup 3) (pc)) (const_int -2040))
 		     (le (minus (match_dup 3) (pc)) (const_int 2048)))
 		(const_int 6)
-		(const_int 8))))]
+		(const_int 8))))
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*negated_cbranchsi4"
@@ -7775,7 +7848,8 @@
 	        (and (ge (minus (match_dup 3) (pc)) (const_int -2040))
 		     (le (minus (match_dup 3) (pc)) (const_int 2048)))
 		(const_int 6)
-		(const_int 8))))]
+		(const_int 8))))
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*tbit_cbranch"
@@ -7819,7 +7893,8 @@
 	        (and (ge (minus (match_dup 3) (pc)) (const_int -2040))
 		     (le (minus (match_dup 3) (pc)) (const_int 2048)))
 		(const_int 6)
-		(const_int 8))))]
+		(const_int 8))))
+   (set_attr "type" "multiple")]
 )
   
 (define_insn "*tlobits_cbranch"
@@ -7863,7 +7938,8 @@
 	        (and (ge (minus (match_dup 3) (pc)) (const_int -2040))
 		     (le (minus (match_dup 3) (pc)) (const_int 2048)))
 		(const_int 6)
-		(const_int 8))))]
+		(const_int 8))))
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*tstsi3_cbranch"
@@ -7900,7 +7976,8 @@
 	        (and (ge (minus (match_dup 2) (pc)) (const_int -2040))
 		     (le (minus (match_dup 2) (pc)) (const_int 2048)))
 		(const_int 6)
-		(const_int 8))))]
+		(const_int 8))))
+   (set_attr "type" "multiple")]
 )
   
 (define_insn "*cbranchne_decr1"
@@ -8003,7 +8080,8 @@
 	   (and (ge (minus (match_dup 4) (pc)) (const_int -2038))
 		(le (minus (match_dup 4) (pc)) (const_int 2048)))
 	   (const_int 8)
-	   (const_int 10)))])]
+	   (const_int 10)))])
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*addsi3_cbranch"
@@ -8084,7 +8162,8 @@
 	   (and (ge (minus (match_dup 5) (pc)) (const_int -2038))
 		(le (minus (match_dup 5) (pc)) (const_int 2048)))
 	   (const_int 8)
-	   (const_int 10)))))]
+	   (const_int 10)))))
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*addsi3_cbranch_scratch"
@@ -8152,7 +8231,8 @@
 	   (and (ge (minus (match_dup 4) (pc)) (const_int -2040))
 		(le (minus (match_dup 4) (pc)) (const_int 2048)))
 	   (const_int 6)
-	   (const_int 8))))]
+	   (const_int 8))))
+   (set_attr "type" "multiple")]
 )
 
 
@@ -8255,7 +8335,8 @@
     operands[2] = gen_lowpart (SImode, operands[2]);
   }
   [(set_attr "conds" "set")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*arm_cmpdi_unsigned"
@@ -8283,7 +8364,8 @@
   [(set_attr "conds" "set")
    (set_attr "enabled_for_depr_it" "yes,yes,no")
    (set_attr "arch" "t2,t2,*")
-   (set_attr "length" "6,6,8")]
+   (set_attr "length" "6,6,8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*arm_cmpdi_zero"
@@ -8293,7 +8375,8 @@
    (clobber (match_scratch:SI 1 "=r"))]
   "TARGET_32BIT"
   "orr%.\\t%1, %Q0, %R0"
-  [(set_attr "conds" "set")]
+  [(set_attr "conds" "set")
+   (set_attr "type" "logics_reg")]
 )
 
 (define_insn "*thumb_cmpdi_zero"
@@ -8304,7 +8387,8 @@
   "TARGET_THUMB1"
   "orr\\t%1, %Q0, %R0"
   [(set_attr "conds" "set")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "logics_reg")]
 )
 
 ; This insn allows redundant compares to be removed by cse, nothing should
@@ -8318,7 +8402,8 @@
   "TARGET_32BIT"
   "\\t%@ deleted compare"
   [(set_attr "conds" "set")
-   (set_attr "length" "0")]
+   (set_attr "length" "0")
+   (set_attr "type" "no_insn")]
 )
 
 
@@ -8419,7 +8504,8 @@
                          (const_int 0)))]
   ""
   [(set_attr "conds" "use")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*mov_negscc"
@@ -8437,7 +8523,8 @@
     operands[3] = GEN_INT (~0);
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*mov_notscc"
@@ -8456,7 +8543,8 @@
     operands[4] = GEN_INT (~0);
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "cstoresi4"
@@ -8661,7 +8749,8 @@
   "@
    neg\\t%0, %1\;adc\\t%0, %0, %1
    neg\\t%2, %1\;adc\\t%0, %1, %2"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*cstoresi_ne0_thumb1_insn"
@@ -8681,7 +8770,8 @@
 			(match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r"))))]
   "TARGET_THUMB1"
   "cmp\\t%1, %2\;sbc\\t%0, %0, %0"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "cstoresi_ltu_thumb1"
@@ -8695,7 +8785,8 @@
 	(neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
    (set (match_dup 0) (neg:SI (match_dup 3)))]
   "operands[3] = gen_reg_rtx (SImode);"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "multiple")]
 )
 
 ;; Used as part of the expansion of thumb les sequence.
@@ -8707,7 +8798,8 @@
 			 (match_operand:SI 4 "thumb1_cmp_operand" "lI"))))]
   "TARGET_THUMB1"
   "cmp\\t%3, %4\;adc\\t%0, %1, %2"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "multiple")]
 )
 
 
@@ -8925,7 +9017,8 @@
 		(and (ge (minus (match_dup 0) (pc)) (const_int -2044))
 		     (le (minus (match_dup 0) (pc)) (const_int 2048))))
 	   (const_int 2)
-	   (const_int 4)))]
+	   (const_int 4)))
+   (set_attr "type" "branch")]
 )
 
 (define_insn "*thumb_jump"
@@ -8947,7 +9040,8 @@
 	    (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
 		 (le (minus (match_dup 0) (pc)) (const_int 2048)))
   	    (const_int 2)
-	    (const_int 4)))]
+	    (const_int 4)))
+   (set_attr "type" "branch")]
 )
 
 (define_expand "call"
@@ -9431,7 +9525,8 @@
   "TARGET_ARM"
   "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
   [(set_attr "length" "8")
-   (set_attr "conds" "set")]
+   (set_attr "conds" "set")
+   (set_attr "type" "multiple")]
 )
 
 ;; Call subroutine returning any type.
@@ -9622,7 +9717,8 @@
     return   \"cmp\\t%0, %1\;ldrls\\t%|pc, [%|pc, %0, asl #2]\;b\\t%l3\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "thumb1_casesi_internal_pic"
@@ -9653,7 +9749,8 @@
               (clobber (reg:SI LR_REGNUM))])]
   "TARGET_THUMB1"
   "* return thumb1_output_casesi(operands);"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "multiple")]
 )
 
 (define_expand "indirect_jump"
@@ -9679,7 +9776,8 @@
 	(match_operand:SI 0 "s_register_operand" "r"))]
   "TARGET_ARM"
   "mov%?\\t%|pc, %0\\t%@ indirect register jump"
-  [(set_attr "predicable" "yes")]
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "branch")]
 )
 
 (define_insn "*load_indirect_jump"
@@ -9700,7 +9798,8 @@
   "TARGET_THUMB1"
   "mov\\tpc, %0"
   [(set_attr "conds" "clob")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "branch")]
 )
 
 
@@ -9719,7 +9818,8 @@
   [(set (attr "length")
 	(if_then_else (eq_attr "is_thumb" "yes")
 		      (const_int 2)
-		      (const_int 4)))]
+		      (const_int 4)))
+   (set_attr "type" "mov_reg")]
 )
 
 
@@ -9884,7 +9984,7 @@
     operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
   }
   [(set_attr "conds" "use")
-   (set_attr "type" "mov_reg")
+   (set_attr "type" "multiple")
    (set_attr "length" "8")]
 )
 
@@ -9918,7 +10018,8 @@
     operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "4,8")]
+   (set_attr "length" "4,8")
+   (set_attr "type" "logic_imm,multiple")]
 )
 
 ; A series of splitters for the compare_scc pattern below.  Note that
@@ -10020,7 +10121,9 @@
   else
     rc = reverse_condition (rc);
   operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
-})
+}
+  [(set_attr "type" "multiple")]
+)
 
 ;; Attempt to improve the sequence generated by the compare_scc splitters
 ;; not to use conditional execution.
@@ -10137,7 +10240,7 @@
     return \"\";
   "
   [(set_attr "conds" "use")
-   (set_attr "type" "mov_reg")
+   (set_attr "type" "mov_reg,mov_reg,multiple")
    (set_attr "length" "4,4,8")]
 )
 
@@ -10164,7 +10267,8 @@
     return \"%i5%d4\\t%0, %1, #1\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*cond_sub"
@@ -10182,7 +10286,8 @@
     return \"sub%d4\\t%0, %1, #1\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*cmp_ite0"
@@ -10246,6 +10351,7 @@
   }"
   [(set_attr "conds" "set")
    (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
+   (set_attr "type" "multiple")
    (set_attr_alternative "length"
       [(const_int 6)
        (const_int 8)
@@ -10345,7 +10451,8 @@
            (const_int 10))
        (if_then_else (eq_attr "is_thumb" "no")
            (const_int 8)
-           (const_int 10))])]
+           (const_int 10))])
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*cmp_and"
@@ -10426,7 +10533,8 @@
            (const_int 10))
        (if_then_else (eq_attr "is_thumb" "no")
            (const_int 8)
-           (const_int 10))])]
+           (const_int 10))])
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*cmp_ior"
@@ -10507,7 +10615,8 @@
            (const_int 10))
        (if_then_else (eq_attr "is_thumb" "no")
            (const_int 8)
-           (const_int 10))])]
+           (const_int 10))])
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*ior_scc_scc"
@@ -10536,7 +10645,9 @@
 						  DOM_CC_X_OR_Y),
 		    CC_REGNUM);"
   [(set_attr "conds" "clob")
-   (set_attr "length" "16")])
+   (set_attr "length" "16")
+   (set_attr "type" "multiple")]
+)
 
 ; If the above pattern is followed by a CMP insn, then the compare is 
 ; redundant, since we can rework the conditional instruction that follows.
@@ -10564,7 +10675,9 @@
    (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
   ""
   [(set_attr "conds" "set")
-   (set_attr "length" "16")])
+   (set_attr "length" "16")
+   (set_attr "type" "multiple")]
+)
 
 (define_insn_and_split "*and_scc_scc"
   [(set (match_operand:SI 0 "s_register_operand" "=Ts")
@@ -10594,7 +10707,9 @@
 						  DOM_CC_X_AND_Y),
 		    CC_REGNUM);"
   [(set_attr "conds" "clob")
-   (set_attr "length" "16")])
+   (set_attr "length" "16")
+   (set_attr "type" "multiple")]
+)
 
 ; If the above pattern is followed by a CMP insn, then the compare is 
 ; redundant, since we can rework the conditional instruction that follows.
@@ -10622,7 +10737,9 @@
    (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
   ""
   [(set_attr "conds" "set")
-   (set_attr "length" "16")])
+   (set_attr "length" "16")
+   (set_attr "type" "multiple")]
+)
 
 ;; If there is no dominance in the comparison, then we can still save an
 ;; instruction in the AND case, since we can know that the second compare
@@ -10656,7 +10773,9 @@
    operands[8] = gen_rtx_COMPARE (GET_MODE (operands[7]), operands[4],
 				  operands[5]);"
   [(set_attr "conds" "clob")
-   (set_attr "length" "20")])
+   (set_attr "length" "20")
+   (set_attr "type" "multiple")]
+)
 
 (define_split
   [(set (reg:CC_NOOV CC_REGNUM)
@@ -10767,7 +10886,8 @@
      FAIL;
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "movcond_addsi"
@@ -10805,7 +10925,8 @@
   }
   "
   [(set_attr "conds" "clob")
-   (set_attr "enabled_for_depr_it" "no,yes,yes")]
+   (set_attr "enabled_for_depr_it" "no,yes,yes")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "movcond"
@@ -10868,7 +10989,8 @@
   return \"\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,8,12")]
+   (set_attr "length" "8,8,12")
+   (set_attr "type" "multiple")]
 )
 
 ;; ??? The patterns below need checking for Thumb-2 usefulness.
@@ -10886,7 +11008,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_plus_move"
@@ -10909,10 +11032,10 @@
    (set_attr_alternative "type"
                          [(if_then_else (match_operand 3 "const_int_operand" "")
                                         (const_string "alu_imm" )
-                                        (const_string "*"))
+                                        (const_string "alu_reg"))
                           (const_string "alu_imm")
-                          (const_string "*")
-                          (const_string "*")])]
+                          (const_string "alu_reg")
+                          (const_string "alu_reg")])]
 )
 
 (define_insn "*ifcompare_move_plus"
@@ -10928,7 +11051,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_move_plus"
@@ -10948,13 +11072,7 @@
    sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
   [(set_attr "conds" "use")
    (set_attr "length" "4,4,8,8")
-   (set_attr_alternative "type"
-                         [(if_then_else (match_operand 3 "const_int_operand" "")
-                                        (const_string "alu_imm" )
-                                        (const_string "*"))
-                          (const_string "alu_imm")
-                          (const_string "*")
-                          (const_string "*")])]
+   (set_attr "type" "alu_reg,alu_imm,multiple,multiple")]
 )
 
 (define_insn "*ifcompare_arith_arith"
@@ -10972,7 +11090,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_arith_arith"
@@ -10988,7 +11107,8 @@
   "TARGET_ARM"
   "%I6%d5\\t%0, %1, %2\;%I7%D5\\t%0, %3, %4"
   [(set_attr "conds" "use")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*ifcompare_arith_move"
@@ -11029,7 +11149,8 @@
   return \"\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_arith_move"
@@ -11046,7 +11167,7 @@
    %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1"
   [(set_attr "conds" "use")
    (set_attr "length" "4,8")
-   (set_attr "type" "*,*")]
+   (set_attr "type" "alu_shift_reg,multiple")]
 )
 
 (define_insn "*ifcompare_move_arith"
@@ -11088,7 +11209,8 @@
   return \"%I7%D6\\t%0, %2, %3\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_move_arith"
@@ -11106,7 +11228,7 @@
    %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1"
   [(set_attr "conds" "use")
    (set_attr "length" "4,8")
-   (set_attr "type" "*,*")]
+   (set_attr "type" "alu_shift_reg,multiple")]
 )
 
 (define_insn "*ifcompare_move_not"
@@ -11122,7 +11244,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_move_not"
@@ -11139,7 +11262,8 @@
    mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2"
   [(set_attr "conds" "use")
    (set_attr "type" "mvn_reg")
-   (set_attr "length" "4,8,8")]
+   (set_attr "length" "4,8,8")
+   (set_attr "type" "mvn_reg,multiple,multiple")]
 )
 
 (define_insn "*ifcompare_not_move"
@@ -11155,7 +11279,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_not_move"
@@ -11171,7 +11296,7 @@
    mov%D4\\t%0, %1\;mvn%d4\\t%0, %2
    mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2"
   [(set_attr "conds" "use")
-   (set_attr "type" "mvn_reg")
+   (set_attr "type" "mvn_reg,multiple,multiple")
    (set_attr "length" "4,8,8")]
 )
 
@@ -11189,7 +11314,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_shift_move"
@@ -11209,9 +11335,7 @@
   [(set_attr "conds" "use")
    (set_attr "shift" "2")
    (set_attr "length" "4,8,8")
-   (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
-		      (const_string "mov_shift")
-		      (const_string "mov_shift_reg")))]
+   (set_attr "type" "mov_shift_reg,multiple,multiple")]
 )
 
 (define_insn "*ifcompare_move_shift"
@@ -11228,7 +11352,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_move_shift"
@@ -11248,9 +11373,7 @@
   [(set_attr "conds" "use")
    (set_attr "shift" "2")
    (set_attr "length" "4,8,8")
-   (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
-		      (const_string "mov_shift")
-		      (const_string "mov_shift_reg")))]
+   (set_attr "type" "mov_shift_reg,multiple,multiple")]
 )
 
 (define_insn "*ifcompare_shift_shift"
@@ -11269,7 +11392,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_shift_shift"
@@ -11309,7 +11433,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_not_arith"
@@ -11342,7 +11467,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_arith_not"
@@ -11357,7 +11483,7 @@
   "TARGET_ARM"
   "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3"
   [(set_attr "conds" "use")
-   (set_attr "type" "mvn_reg")
+   (set_attr "type" "multiple")
    (set_attr "length" "8")]
 )
 
@@ -11373,7 +11499,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_neg_move"
@@ -11389,7 +11516,8 @@
    mov%D4\\t%0, %1\;rsb%d4\\t%0, %2, #0
    mvn%D4\\t%0, #%B1\;rsb%d4\\t%0, %2, #0"
   [(set_attr "conds" "use")
-   (set_attr "length" "4,8,8")]
+   (set_attr "length" "4,8,8")
+   (set_attr "type" "logic_shift_imm,multiple,multiple")]
 )
 
 (define_insn "*ifcompare_move_neg"
@@ -11404,7 +11532,8 @@
   "TARGET_ARM"
   "#"
   [(set_attr "conds" "clob")
-   (set_attr "length" "8,12")]
+   (set_attr "length" "8,12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*if_move_neg"
@@ -11420,7 +11549,8 @@
    mov%d4\\t%0, %1\;rsb%D4\\t%0, %2, #0
    mvn%d4\\t%0, #%B1\;rsb%D4\\t%0, %2, #0"
   [(set_attr "conds" "use")
-   (set_attr "length" "4,8,8")]
+   (set_attr "length" "4,8,8")
+   (set_attr "type" "logic_shift_imm,multiple,multiple")]
 )
 
 (define_insn "*arith_adjacentmem"
@@ -11618,7 +11748,8 @@
   [(unspec_volatile [(const_int 0)] VUNSPEC_THUMB1_INTERWORK)]
   "TARGET_THUMB1"
   "* return thumb1_output_interwork ();"
-  [(set_attr "length" "8")]
+  [(set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 ;; Note - although unspec_volatile's USE all hard registers,
@@ -11805,7 +11936,7 @@
    mvn%D4\\t%0, %2
    mov%d4\\t%0, %1\;mvn%D4\\t%0, %2"
   [(set_attr "conds" "use")
-   (set_attr "type" "mvn_reg")
+   (set_attr "type" "mvn_reg,multiple")
    (set_attr "length" "4,8")]
 )
 
@@ -11825,7 +11956,8 @@
     return \"mvnne\\t%0, #0\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*not_signextract_onebit"
@@ -11843,7 +11975,8 @@
     return \"movne\\t%0, #0\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 ;; ??? The above patterns need auditing for Thumb-2
 
@@ -11905,7 +12038,8 @@
 		    UNSPEC_PRLG_STK))]
   ""
   ""
-  [(set_attr "length" "0")]
+  [(set_attr "length" "0")
+   (set_attr "type" "block")]
 )
 
 ;; Pop (as used in epilogue RTL)
@@ -12035,6 +12169,7 @@
   assemble_align (32);
   return \"\";
   "
+  [(set_attr "type" "no_insn")]
 )
 
 (define_insn "align_8"
@@ -12044,6 +12179,7 @@
   assemble_align (64);
   return \"\";
   "
+  [(set_attr "type" "no_insn")]
 )
 
 (define_insn "consttable_end"
@@ -12053,6 +12189,7 @@
   making_const_table = FALSE;
   return \"\";
   "
+  [(set_attr "type" "no_insn")]
 )
 
 (define_insn "consttable_1"
@@ -12064,7 +12201,8 @@
   assemble_zeros (3);
   return \"\";
   "
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "no_insn")]
 )
 
 (define_insn "consttable_2"
@@ -12077,7 +12215,8 @@
   assemble_zeros (2);
   return \"\";
   "
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "no_insn")]
 )
 
 (define_insn "consttable_4"
@@ -12113,7 +12252,8 @@
       }
     return \"\";
   }"
-  [(set_attr "length" "4")]
+  [(set_attr "length" "4")
+   (set_attr "type" "no_insn")]
 )
 
 (define_insn "consttable_8"
@@ -12137,7 +12277,8 @@
       }
     return \"\";
   }"
-  [(set_attr "length" "8")]
+  [(set_attr "length" "8")
+   (set_attr "type" "no_insn")]
 )
 
 (define_insn "consttable_16"
@@ -12161,7 +12302,8 @@
       }
     return \"\";
   }"
-  [(set_attr "length" "16")]
+  [(set_attr "length" "16")
+   (set_attr "type" "no_insn")]
 )
 
 ;; Miscellaneous Thumb patterns
@@ -12189,7 +12331,8 @@
    (use (label_ref (match_operand 1 "" "")))]
   "TARGET_THUMB1"
   "mov\\t%|pc, %0"
-  [(set_attr "length" "2")]
+  [(set_attr "length" "2")
+   (set_attr "type" "no_insn")]
 )
 
 ;; V5 Instructions,
@@ -12231,7 +12374,9 @@
 	     (match_operand:SI 1 "" "")
 	     (match_operand:SI 2 "" ""))]
   "TARGET_32BIT && arm_arch5e"
-  "pld\\t%a0")
+  "pld\\t%a0"
+  [(set_attr "type" "load1")]
+)
 
 ;; General predication pattern
 
@@ -12248,7 +12393,8 @@
   [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_REGISTER_USE)]
   ""
   "%@ %0 needed"
-  [(set_attr "length" "0")]
+  [(set_attr "length" "0")
+   (set_attr "type" "no_insn")]
 )
 
 
@@ -12296,6 +12442,7 @@
     thumb_set_return_address (operands[0], operands[1]);
     DONE;
   }"
+  [(set_attr "type" "mov_reg")]
 )
 
 
@@ -12306,7 +12453,8 @@
 	(unspec:SI [(const_int 0)] UNSPEC_TLS))]
   "TARGET_HARD_TP"
   "mrc%?\\tp15, 0, %0, c13, c0, 3\\t@ load_tp_hard"
-  [(set_attr "predicable" "yes")]
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "mov_reg")]
 )
 
 ;; Doesn't clobber R1-R3.  Must use r0 for the first operand.
@@ -12317,7 +12465,8 @@
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_SOFT_TP"
   "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
-  [(set_attr "conds" "clob")]
+  [(set_attr "conds" "clob")
+   (set_attr "type" "branch")]
 )
 
 ;; tls descriptor call
@@ -12336,7 +12485,8 @@
     return "bl\\t%c0(tlscall)";
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "4")]
+   (set_attr "length" "4")
+   (set_attr "type" "branch")]
 )
 
 ;; For thread pointer builtin
@@ -12362,7 +12512,8 @@
   "movt%?\t%0, %L1"
  [(set_attr "predicable" "yes")
   (set_attr "predicable_short_it" "no")
-  (set_attr "length" "4")]
+  (set_attr "length" "4")
+  (set_attr "type" "mov_imm")]
 )
 
 (define_insn "*arm_rev"
@@ -12374,7 +12525,8 @@
    rev%?\t%0, %1
    rev%?\t%0, %1"
   [(set_attr "arch" "t1,t2,32")
-   (set_attr "length" "2,2,4")]
+   (set_attr "length" "2,2,4")
+   (set_attr "type" "rev")]
 )
 
 (define_expand "arm_legacy_rev"
@@ -12474,7 +12626,8 @@
   revsh%?\t%0, %1
   revsh%?\t%0, %1"
   [(set_attr "arch" "t1,t2,32")
-   (set_attr "length" "2,2,4")]
+   (set_attr "length" "2,2,4")
+   (set_attr "type" "rev")]
 )
 
 (define_insn "*arm_rev16"
@@ -12486,7 +12639,8 @@
    rev16%?\t%0, %1
    rev16%?\t%0, %1"
   [(set_attr "arch" "t1,t2,32")
-   (set_attr "length" "2,2,4")]
+   (set_attr "length" "2,2,4")
+   (set_attr "type" "rev")]
 )
 
 (define_expand "bswaphi2"
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index ce89f1db02a..615c6a5b16d 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -71,7 +71,8 @@
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
                        adr,bfm,rev,\
                        shift_imm,shift_reg,\
-                       mov_imm,mov_reg,mvn_imm,mvn_reg"))
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       multiple,no_insn"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-constant operand
diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md
index 6f4a8fa76e1..f5a0447f5da 100644
--- a/gcc/config/arm/arm1026ejs.md
+++ b/gcc/config/arm/arm1026ejs.md
@@ -71,7 +71,8 @@
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
                        adr,bfm,rev,\
                        shift_imm,shift_reg,\
-                       mov_imm,mov_reg,mvn_imm,mvn_reg"))
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       multiple,no_insn"))
  "a_e,a_m,a_w")
 
 ;; ALU operations with a shift-by-constant operand
diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md
index 7d39f12d08a..f6e0b8da8b6 100644
--- a/gcc/config/arm/arm1136jfs.md
+++ b/gcc/config/arm/arm1136jfs.md
@@ -80,7 +80,8 @@
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
                        adr,bfm,rev,\
                        shift_imm,shift_reg,\
-                       mov_imm,mov_reg,mvn_imm,mvn_reg"))
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       multiple,no_insn"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-constant operand
diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md
index 7c2d52e8073..d2b0e9e3cf8 100644
--- a/gcc/config/arm/arm926ejs.md
+++ b/gcc/config/arm/arm926ejs.md
@@ -66,7 +66,8 @@
                        logic_shift_imm,logics_shift_imm,\
                        shift_imm,shift_reg,extend,\
                        mov_imm,mov_reg,mov_shift,\
-                       mvn_imm,mvn_reg,mvn_shift"))
+                       mvn_imm,mvn_reg,mvn_shift,\
+                       multiple,no_insn"))
  "e,m,w")
 
 ;; ALU operations with a shift-by-register operand
diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md
index 382a3dc73d4..6b155926024 100644
--- a/gcc/config/arm/cortex-a15.md
+++ b/gcc/config/arm/cortex-a15.md
@@ -67,7 +67,8 @@
                         adr,bfm,rev,\
                         shift_imm,shift_reg,\
                         mov_imm,mov_reg,\
-                        mvn_imm,mvn_reg"))
+                        mvn_imm,mvn_reg,\
+                        multiple,no_insn"))
   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
 
 ;; ALU ops with immediate shift
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 19738e6d56f..8930baf8daf 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -63,7 +63,8 @@
                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
                         adr,bfm,rev,\
                         shift_imm,shift_reg,\
-                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
+                        mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                        multiple,no_insn"))
   "cortex_a5_ex1")
 
 (define_insn_reservation "cortex_a5_alu_shift" 2
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index 9331eceb2ed..66d4cb436f5 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -72,7 +72,8 @@
                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
                         adr,bfm,csel,rev,\
                         shift_imm,shift_reg,\
-                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
+                        mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                        multiple,no_insn"))
   "cortex_a53_slot_any")
 
 (define_insn_reservation "cortex_a53_alu_shift" 2
@@ -81,7 +82,7 @@
                         logic_shift_imm,logics_shift_imm,\
                         alu_shift_reg,alus_shift_reg,\
                         logic_shift_reg,logics_shift_reg,\
-                        mov_shift,mov_shift_reg,\
+                        extend,mov_shift,mov_shift_reg,\
                         mvn_shift,mvn_shift_reg"))
   "cortex_a53_slot_any")
 
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index 9373077b754..bd7aecda021 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -109,7 +109,8 @@
                         alu_shift_reg,alus_shift_reg,\
                         logic_shift_reg,logics_shift_reg,\
                         mov_shift,mov_shift_reg,\
-                        mvn_shift,mvn_shift_reg"))
+                        mvn_shift,mvn_shift_reg,\
+                        multiple,no_insn"))
   "cortex_a7_ex1")
 
 ;; Forwarding path for unshifted operands.
diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md
index 22f9ee92bde..ed0b351365c 100644
--- a/gcc/config/arm/cortex-a8.md
+++ b/gcc/config/arm/cortex-a8.md
@@ -89,7 +89,8 @@
                         alu_reg,alus_reg,logic_reg,logics_reg,\
                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
                         adr,bfm,clz,rbit,rev,\
-                        shift_imm,shift_reg"))
+                        shift_imm,shift_reg,\
+                        multiple,no_insn"))
   "cortex_a8_default")
 
 (define_insn_reservation "cortex_a8_alu_shift" 2
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index e5788b6b872..4703bf36b2f 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -86,7 +86,8 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
                         adr,bfm,rev,\
                         shift_imm,shift_reg,\
                         mov_imm,mov_reg,mvn_imm,mvn_reg,\
-                        mov_shift_reg,mov_shift"))
+                        mov_shift_reg,mov_shift,\
+                        multiple,no_insn"))
   "cortex_a9_p0_default|cortex_a9_p1_default")
 
 ;; An instruction using the shifter will go down E1.
diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md
index 0c628f08b5f..8663eb77fa1 100644
--- a/gcc/config/arm/cortex-m4.md
+++ b/gcc/config/arm/cortex-m4.md
@@ -41,7 +41,8 @@
                              alu_shift_reg,alus_shift_reg,\
                              logic_shift_reg,logics_shift_reg,\
                              mov_imm,mov_reg,mov_shift,mov_shift_reg,\
-                             mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")
+                             mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
+                             multiple,no_insn")
 	    (ior (eq_attr "mul32" "yes")
 		 (eq_attr "mul64" "yes"))))
   "cortex_m4_ex")
diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md
index 83745c1b4c7..11a6e6419f5 100644
--- a/gcc/config/arm/cortex-r4.md
+++ b/gcc/config/arm/cortex-r4.md
@@ -101,7 +101,8 @@
   (and (eq_attr "tune_cortexr4" "yes")
        (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
                        logic_shift_reg,logics_shift_reg,\
-                       mov_shift_reg,mvn_shift_reg"))
+                       mov_shift_reg,mvn_shift_reg,\
+                       multiple,no_insn"))
   "cortex_r4_alu_shift_reg")
 
 ;; An ALU instruction followed by an ALU instruction with no early dep.
diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md
index 90abf6cb859..ddd48fe107e 100644
--- a/gcc/config/arm/fa526.md
+++ b/gcc/config/arm/fa526.md
@@ -67,7 +67,8 @@
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
                        adr,bfm,rev,\
                        shift_imm,shift_reg,\
-                       mov_imm,mov_reg,mvn_imm,mvn_reg"))
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       multiple,no_insn"))
  "fa526_core")
 
 (define_insn_reservation "526_alu_shift_op" 2
diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md
index 20f66e6ae19..892ea31fccd 100644
--- a/gcc/config/arm/fa606te.md
+++ b/gcc/config/arm/fa606te.md
@@ -72,7 +72,8 @@
                        alu_shift_reg,alus_shift_reg,\
                        logic_shift_reg,logics_shift_reg,\
                        mov_imm,mov_reg,mov_shift,mov_shift_reg,\
-                       mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
+                       mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
+                       multiple,no_insn"))
  "fa606te_core")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md
index c5b841c3630..8b9253171d4 100644
--- a/gcc/config/arm/fa626te.md
+++ b/gcc/config/arm/fa626te.md
@@ -73,7 +73,8 @@
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
                        adr,bfm,rev,\
                        shift_imm,shift_reg,\
-                       mov_imm,mov_reg,mvn_imm,mvn_reg"))
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       multiple,no_insn"))
  "fa626te_core")
 
 (define_insn_reservation "626te_alu_shift_op" 2
diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md
index 1947d36ec09..28be92de75a 100644
--- a/gcc/config/arm/fa726te.md
+++ b/gcc/config/arm/fa726te.md
@@ -90,7 +90,8 @@
                        alu_reg,alus_reg,logic_reg,logics_reg,\
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
                        adr,bfm,rev,\
-                       shift_imm,shift_reg"))
+                       shift_imm,shift_reg,\
+                       multiple,no_insn"))
   "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
 
 ;; ALU operations with a shift-by-register operand.
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 613d0a10a69..3b5944a014a 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -58,7 +58,8 @@
   ""
   [(set_attr "conds" "clob")
    (set_attr "enabled_for_depr_it" "yes,yes,no")
-   (set_attr "length" "6,6,10")]
+   (set_attr "length" "6,6,10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_sminsi3"
@@ -78,7 +79,8 @@
   ""
   [(set_attr "conds" "clob")
    (set_attr "enabled_for_depr_it" "yes,yes,no")
-   (set_attr "length" "6,6,10")]
+   (set_attr "length" "6,6,10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb32_umaxsi3"
@@ -98,7 +100,8 @@
   ""
   [(set_attr "conds" "clob")
    (set_attr "length" "6,6,10")
-   (set_attr "enabled_for_depr_it" "yes,yes,no")]
+   (set_attr "enabled_for_depr_it" "yes,yes,no")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_uminsi3"
@@ -118,7 +121,8 @@
   ""
   [(set_attr "conds" "clob")
    (set_attr "length" "6,6,10")
-   (set_attr "enabled_for_depr_it" "yes,yes,no")]
+   (set_attr "enabled_for_depr_it" "yes,yes,no")
+   (set_attr "type" "multiple")]
 )
 
 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
@@ -143,7 +147,8 @@
     operands[1] = gen_lowpart (SImode, operands[1]);
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_abssi2"
@@ -200,7 +205,8 @@
    (set_attr "predicable_short_it" "no")
    (set_attr "enabled_for_depr_it" "yes,yes,no")
    (set_attr "ce_count" "2")
-   (set_attr "length" "8,6,10")]
+   (set_attr "length" "8,6,10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_neg_abssi2"
@@ -257,7 +263,8 @@
    (set_attr "enabled_for_depr_it" "yes,yes,no")
    (set_attr "predicable_short_it" "no")
    (set_attr "ce_count" "2")
-   (set_attr "length" "8,6,10")]
+   (set_attr "length" "8,6,10")
+   (set_attr "type" "multiple")]
 )
 
 ;; We have two alternatives here for memory loads (and similarly for stores)
@@ -282,7 +289,7 @@
    ldr%?\\t%0, %1
    str%?\\t%1, %0
    str%?\\t%1, %0"
-  [(set_attr "type" "*,alu_imm,alu_imm,alu_imm,*,load1,load1,store1,store1")
+  [(set_attr "type" "mov_reg,alu_imm,alu_imm,alu_imm,mov_imm,load1,load1,store1,store1")
    (set_attr "length" "2,4,2,4,4,4,4,4,4")
    (set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
@@ -303,7 +310,8 @@
 			     INTVAL (operands[3]));
   return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
   "
-  [(set_attr "length" "4,4,6,6")]
+  [(set_attr "length" "4,4,6,6")
+   (set_attr "type" "multiple")]
 )
 
 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
@@ -319,7 +327,7 @@
    movw%?\\t%0, %L1\\t%@ movhi
    str%(h%)\\t%1, %0\\t%@ movhi
    ldr%(h%)\\t%0, %1\\t%@ movhi"
-  [(set_attr "type" "*,*,store1,load1")
+  [(set_attr "type" "mov_imm,mov_reg,store1,load1")
    (set_attr "predicable" "yes")
    (set_attr "pool_range" "*,*,*,4094")
    (set_attr "neg_pool_range" "*,*,*,250")]
@@ -367,7 +375,8 @@
   ""
   [(set_attr "conds" "use")
    (set_attr "enabled_for_depr_it" "yes,no")
-   (set_attr "length" "8,10")]
+   (set_attr "length" "8,10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_mov_negscc"
@@ -385,7 +394,8 @@
     operands[3] = GEN_INT (~0);
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "10")]
+   (set_attr "length" "10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
@@ -413,7 +423,8 @@
 
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_mov_notscc"
@@ -432,7 +443,8 @@
     operands[4] = GEN_INT (~0);
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "10")]
+   (set_attr "length" "10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
@@ -454,7 +466,8 @@
                                   VOIDmode, operands[2], const0_rtx);
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_movsicc_insn"
@@ -514,7 +527,8 @@
   }
   [(set_attr "length" "4,4,6,6,6,6,10,10,10,10,6")
    (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,yes")
-   (set_attr "conds" "use")]
+   (set_attr "conds" "use")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb2_movsfcc_soft_insn"
@@ -528,7 +542,8 @@
    it\\t%D3\;mov%D3\\t%0, %2
    it\\t%d3\;mov%d3\\t%0, %1"
   [(set_attr "length" "6,6")
-   (set_attr "conds" "use")]
+   (set_attr "conds" "use")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*call_reg_thumb2"
@@ -557,7 +572,8 @@
 	(match_operand:SI 0 "register_operand" "l*r"))]
   "TARGET_THUMB2"
   "bx\\t%0"
-  [(set_attr "conds" "clob")]
+  [(set_attr "conds" "clob")
+   (set_attr "type" "branch")]
 )
 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 ;; addresses will have the thumb bit set correctly.
@@ -585,6 +601,7 @@
     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
   }
   [(set_attr "conds" "use")
+   (set_attr "type" "multiple")
    (set (attr "length") (if_then_else (match_test "arm_restrict_it")
                                       (const_int 8)
                                       (const_int 10)))]
@@ -617,7 +634,8 @@
     operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
   }
   [(set_attr "conds" "use")
-   (set_attr "length" "6,10")]
+   (set_attr "length" "6,10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb2_ior_scc_strict_it"
@@ -630,7 +648,8 @@
    it\\t%d2\;mov%d2\\t%0, #1\;it\\t%d2\;orr%d2\\t%0, %1
    mov\\t%0, #1\;orr\\t%0, %1\;it\\t%D2\;mov%D2\\t%0, %1"
   [(set_attr "conds" "use")
-   (set_attr "length" "8")]
+   (set_attr "length" "8")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb2_cond_move"
@@ -679,7 +698,8 @@
     return \"\";
   "
   [(set_attr "conds" "use")
-   (set_attr "length" "6,6,10")]
+   (set_attr "length" "6,6,10")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb2_cond_arith"
@@ -716,7 +736,8 @@
     return \"%i5%d4\\t%0, %1, #1\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "14")]
+   (set_attr "length" "14")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_cond_arith_strict_it"
@@ -785,7 +806,8 @@
      FAIL;
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "12")]
+   (set_attr "length" "12")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb2_cond_sub"
@@ -816,7 +838,8 @@
     return \"sub%d4\\t%0, %1, #1\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "10,14")]
+   (set_attr "length" "10,14")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*thumb2_negscc"
@@ -884,7 +907,8 @@
     FAIL;
   }
   [(set_attr "conds" "clob")
-   (set_attr "length" "14")]
+   (set_attr "length" "14")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb2_movcond"
@@ -967,7 +991,8 @@
   return \"\";
   "
   [(set_attr "conds" "clob")
-   (set_attr "length" "10,10,14")]
+   (set_attr "length" "10,10,14")
+   (set_attr "type" "multiple")]
 )
 
 ;; Zero and sign extension instructions.
@@ -1030,7 +1055,8 @@
   "TARGET_THUMB2 && !flag_pic"
   "* return thumb2_output_casesi(operands);"
   [(set_attr "conds" "clob")
-   (set_attr "length" "16")]
+   (set_attr "length" "16")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "thumb2_casesi_internal_pic"
@@ -1048,7 +1074,8 @@
   "TARGET_THUMB2 && flag_pic"
   "* return thumb2_output_casesi(operands);"
   [(set_attr "conds" "clob")
-   (set_attr "length" "20")]
+   (set_attr "length" "20")
+   (set_attr "type" "multiple")]
 )
 
 (define_insn "*thumb2_return"
@@ -1085,7 +1112,8 @@
    && GET_CODE(operands[3]) != MINUS"
   "%I3%!\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_insn "*thumb2_shiftsi3_short"
@@ -1113,7 +1141,8 @@
   "TARGET_THUMB2 && reload_completed"
   "mov%!\t%0, %1"
   [(set_attr "predicable" "yes")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "mov_imm")]
 )
 
 (define_insn "*thumb2_addsi_short"
@@ -1137,7 +1166,8 @@
       return \"add%!\\t%0, %1, %2\";
   "
   [(set_attr "predicable" "yes")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_insn "*thumb2_subsi_short"
@@ -1148,7 +1178,8 @@
   "TARGET_THUMB2 && reload_completed"
   "sub%!\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_peephole2
@@ -1200,7 +1231,8 @@
       return \"adds\\t%0, %1, %2\";
   "
   [(set_attr "conds" "set")
-   (set_attr "length" "2,2,4")]
+   (set_attr "length" "2,2,4")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_insn "*thumb2_addsi3_compare0_scratch"
@@ -1284,7 +1316,8 @@
 	         (le (minus (match_dup 1) (pc)) (const_int 128))
 	         (not (match_test "which_alternative")))
 	    (const_int 2)
-	    (const_int 8)))]
+	    (const_int 8)))
+   (set_attr "type" "branch,multiple")]
 )
 
 (define_insn "*thumb2_cbnz"
@@ -1307,7 +1340,8 @@
 	         (le (minus (match_dup 1) (pc)) (const_int 128))
 	         (not (match_test "which_alternative")))
 	    (const_int 2)
-	    (const_int 8)))]
+	    (const_int 8)))
+   (set_attr "type" "branch,multiple")]
 )
 
 (define_insn "*thumb2_one_cmplsi2_short"
@@ -1317,7 +1351,8 @@
   "TARGET_THUMB2 && reload_completed"
   "mvn%!\t%0, %1"
   [(set_attr "predicable" "yes")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "mvn_reg")]
 )
 
 (define_insn "*thumb2_negsi2_short"
@@ -1327,7 +1362,8 @@
   "TARGET_THUMB2 && reload_completed"
   "neg%!\t%0, %1"
   [(set_attr "predicable" "yes")
-   (set_attr "length" "2")]
+   (set_attr "length" "2")
+   (set_attr "type" "alu_reg")]
 )
 
 (define_insn "*orsi_notsi_si"
@@ -1337,7 +1373,8 @@
   "TARGET_THUMB2"
   "orn%?\\t%0, %1, %2"
   [(set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "no")]
+   (set_attr "predicable_short_it" "no")
+   (set_attr "type" "logic_reg")]
 )
 
 (define_insn "*orsi_not_shiftsi_si"
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 14d2bee82ca..ed2522b0cfe 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -105,10 +105,14 @@
 ; mov_shift_reg      simple MOV instruction, shifted operand by a register.
 ; mul                integer multiply.
 ; muls               integer multiply, flag setting.
+; multiple           more than one instruction, candidate for future
+;                    splitting, or better modeling.
 ; mvn_imm            inverting move instruction, immediate.
 ; mvn_reg            inverting move instruction, register.
 ; mvn_shift          inverting move instruction, shifted operand by a constant.
 ; mvn_shift_reg      inverting move instruction, shifted operand by a register.
+; no_insn            an insn which does not represent an instruction in the
+;                    final output, thus having no impact on scheduling.
 ; rbit               reverse bits.
 ; rev                reverse bytes.
 ; sdiv               signed division.
@@ -150,6 +154,8 @@
 ; umlals             unsigned multiply accumulate long, flag setting.
 ; umull              unsigned multiply long.
 ; umulls             unsigned multiply long, flag setting.
+; untyped            insn without type information - default, and error,
+;                    case.
 ;
 ; The classification below is for instructions used by the Wireless MMX
 ; Technology. Each attribute value is used to classify an instruction of the
@@ -301,6 +307,7 @@
   branch,\
   call,\
   clz,\
+  no_insn,\
   csel,\
   extend,\
   f_cvt,\
@@ -360,10 +367,12 @@
   mov_shift_reg,\
   mul,\
   muls,\
+  multiple,\
   mvn_imm,\
   mvn_reg,\
   mvn_shift,\
   mvn_shift_reg,\
+  nop,\
   rbit,\
   rev,\
   sdiv,\
@@ -403,6 +412,7 @@
   umlals,\
   umull,\
   umulls,\
+  untyped,\
   wmmx_tandc,\
   wmmx_tbcst,\
   wmmx_textrc,\
@@ -524,7 +534,7 @@
   neon_vst2_4_regs_vst3_vst4,\
   neon_vst3_vst4_lane,\
   neon_vst3_vst4"
-    (const_string "alu_imm"))
+    (const_string "untyped"))
 
 ; Is this an (integer side) multiply with a 32-bit (or smaller) result?
 (define_attr "mul32" "no,yes"
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index ea4c1f5834f..419a78984b8 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -144,7 +144,7 @@
       gcc_unreachable ();
     }
   "
-  [(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
+  [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
    (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
                               (eq_attr "alternative" "2") (const_int 12)
                               (eq_attr "alternative" "3") (const_int 16)
@@ -192,7 +192,7 @@
       gcc_unreachable ();
     }
   "
-  [(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
+  [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
    (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
                                (eq_attr "alternative" "2") (const_int 12)
                                (eq_attr "alternative" "3") (const_int 16)
@@ -261,7 +261,7 @@
   "
   [(set_attr "conds" "unconditional")
    (set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\
-                     load1,store1,fcpys,*,f_mcr,f_mrc,*")
+                     load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
    (set_attr "length" "4,4,4,4,4,4,4,4,8")]
 )
 
@@ -311,7 +311,7 @@
     }
   "
   [(set_attr "conds" "unconditional")
-   (set_attr "type" "load1,store1,fcpys,*,f_mcr,f_mrc,*")
+   (set_attr "type" "load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
    (set_attr "length" "4,4,4,4,4,4,8")]
 )
 
@@ -429,7 +429,7 @@
     }
   "
   [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
-                     load2,store2,ffarithd,*")
+                     load2,store2,ffarithd,multiple")
    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 			       (eq_attr "alternative" "7")
 				(if_then_else
@@ -474,7 +474,7 @@
     }
   "
   [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
-                     f_stored,load2,store2,ffarithd,*")
+                     f_stored,load2,store2,ffarithd,multiple")
    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 			       (eq_attr "alternative" "7")
 				(if_then_else
@@ -578,7 +578,7 @@
    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
    [(set_attr "conds" "use")
     (set_attr "length" "6,6,10,6,6,10,6,6,10")
-    (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
+    (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
 )