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| author | dj <dj@138bc75d-0d04-0410-961f-82ee72b054a4> | 2006-07-12 22:31:32 +0000 |
|---|---|---|
| committer | dj <dj@138bc75d-0d04-0410-961f-82ee72b054a4> | 2006-07-12 22:31:32 +0000 |
| commit | 03ed61bd8a839c290a43870e8557401fe6ea27d0 (patch) | |
| tree | 7e52ea4b3827946f1440e0a197d644fc3c83dc33 | |
| parent | ec689dc3a21e7be0855ef46eb43928131d8602a2 (diff) | |
| download | ppe42-gcc-03ed61bd8a839c290a43870e8557401fe6ea27d0.tar.gz ppe42-gcc-03ed61bd8a839c290a43870e8557401fe6ea27d0.zip | |
* config/m32c/muldiv.md (umulhisi3_c): Use only registers for
dest.
(umulhisi3_r): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@115400 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/m32c/muldiv.md | 12 |
2 files changed, 12 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0f97b43b517..0ba96f7cb3c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2006-07-12 Naveen.H.S <naveenh@kpitcummins.com> + + * config/m32c/muldiv.md (umulhisi3_c): Use only registers for + dest. + (umulhisi3_r): Likewise. + 2006-07-12 Paolo Carlini <pcarlini@suse.de> PR libstdc++/27878 diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md index 9313088b552..6913ea9a729 100644 --- a/gcc/config/m32c/muldiv.md +++ b/gcc/config/m32c/muldiv.md @@ -107,18 +107,18 @@ ) (define_insn "umulhisi3_c" - [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm") - (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0")) - (match_operand 2 "immediate_operand" "i,i")))] + [(set (match_operand:SI 0 "ra_operand" "=Rsi") + (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0")) + (match_operand 2 "immediate_operand" "i")))] "" "mulu.w\t%u2,%1" [(set_attr "flags" "o")] ) (define_insn "umulhisi3_r" - [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm") - (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0")) - (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))] + [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi") + (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0")) + (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))] "" "mulu.w\t%u2,%1" [(set_attr "flags" "o")] |
