| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Alistair Popple <alistair@popple.id.au>
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P9 MTNIA uses LR as the source register, so set LR as well as GPR0.
This will work on P8 and P9. This is a bit ugly, but it will work
until we have general getspr/putspr calls for target backends.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Tested-by: Rashmica Gupta <rashmica.g@gmail.com>
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Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
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Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
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Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
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Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
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Signed-off-by: Amitay Isaacs <amitay@ozlabs.org>
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When instruction ramming fails we attempt to restore r0 and r1. This is
unlikely to work as instruction ramming isn't likely to magically start
working if a previous attempt failed. Therefore it is only attempted once
before bailing. However a logic bug in the code meant it would try
indefinitely.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
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Dumping XER checkstops P8 hosts. There is a special ramming op-code for XER
which needs to be used instead.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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There is currently no abstraction of thread status between library and
application. It just passes the hardware specific values down. There is
also no interface exported in the library headers to read status.
This makes it difficult to implement more advanced functionality in the
application as there is no way hardware agnostic way to determine if a
thread is in powersave mode or not for example.
Instead introduce a hardware agnostic thread state so that we can implement
more advanced functionality such as automatically stopping threads if
required.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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... and avoid duplicate definitions
Signed-off-by: Amitay Isaacs <amitay@ozlabs.org>
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This uses ramming to pull out most registers. There are more
SPRs to left to add.
Ramming remains set over all register extraction, by keeping
ram_is_setup target attribut. This helps to speed things up
and minimise disturbance to the host.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Pass errors back to the caller, and clean up with ram_destroy on
failure.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Add basic support for a getring operation on POWER9.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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The existing API between libpdbg and pdbg was poorly defined. Other
programs are beginning to utilise libpdbg so a more strictly defined API
would be beneficial. This patch introduces a new header (libpdbg.h) which
includes the definition of a public API for libpdbg and updates pdbg to
only depend on this.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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In preparation for a better defined libpdbg API rename "struct target" to
something less generic so that we can export the name.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
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Signed-off-by: Alistair Popple <alistair@popple.id.au>
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Several minor fixes were required to enable building on both x64 and ARM with
-Wall -Werror, mostly related to unused variables and bad printf string formats.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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This patch adds support for starting and stopping threads on POWER9 as well as
instruction ramming which is required to read/write GPRs, etc.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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The previous implementation of targeting was hardcoded, cumbersome
and difficult to reconfigure for different chip types. This moves to a
method of configuring targets using device-tree which is much easier
to maintain and allows methods to be added to support operations like
getmem on POWER9.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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The processor chip type was not being detected correctly resulting in
attempts to probe unsupported system components.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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Support detecting different chip types so we enable chip type
dependent behaviour.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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Instructions can only be rammed into a thread is all threads on a
chiplet are quiesced or sleeping. This was not properly enforced which
leads to system checkstops when ramming threads if the chip isn't
fully quiesced. This adds a check to ensure all threads are quiesced.
It also changes the startchip/stopchip behaviour to stop all threads
on the given chiplet regards of which threads are selected.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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Adds a command to read a 64-bit word from a given virtual address. The
address is read in the current thread context and may cause an
exception. In the case of exception it will be raised on the host when
thread execution is resumed.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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This includes better support for selecting targets, probing thread
status and a number of other minor bugfixes. Also adds an option to
print version numbers.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
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