Move procedures into separate files.

Procedures will now be in procedures/<chip>/.

The next commit will have the procedures register
themselves so they won't be in a hardcoded list.

Change-Id: I0ff90afe2b51aaff25b5c25bf87070c820323e30
Signed-off-by: Matt Spinler <spinler@us.ibm.com>

3 files changed, 73 insertions, 30 deletions

diff --git a/Makefile.am b/Makefile.am
index 73ea204..57c0e2c 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -6,9 +6,10 @@ sbin_PROGRAMS = \
 openpower_proc_control_SOURCES = \
 	proc_control.cpp \
 	cfam_access.cpp \
-	p9_procedures.cpp \
 	filedescriptor.cpp \
-	targeting.cpp
+	targeting.cpp \
+	procedures/p9/start_host.cpp \
+	procedures/p9/vcs_workaround.cpp
 
 openpower_proc_control_LDFLAGS = $(PHOSPHOR_LOGGING_LIBS) -lstdc++fs
 openpower_proc_control_CXXFLAGS = $(PHOSPHOR_LOGGING_CFLAGS)
diff --git a/p9_procedures.cpp b/procedures/p9/start_host.cpp
index 188fec0..f781e68 100644
--- a/p9_procedures.cpp
+++ b/procedures/p9/start_host.cpp
@@ -28,6 +28,11 @@ using namespace openpower::cfam::access;
 using namespace openpower::cfam::p9;
 using namespace openpower::targeting;
 
+
+/**
+ * @brief Starts the self boot engine on P9 position 0 to kick off a boot.
+ * @return void
+ */
 void startHost()
 {
     Targeting targets;
@@ -36,7 +41,6 @@ void startHost()
     log<level::INFO>("Running P9 procedure startHost",
                      entry("NUM_PROCS=%d", targets.size()));
 
-
     //Ensure asynchronous clock mode is set
     writeReg(master, P9_LL_MODE_REG, 0x00000001);
 
@@ -68,32 +72,6 @@ void startHost()
 }
 
 
-void vcsWorkaround()
-{
-    Targeting targets;
-    const auto& master = *(targets.begin());
-
-    log<level::INFO>("Running P9 procedure vcsWorkaround",
-                     entry("NUM_PROCS=%d", targets.size()));
-
-    //Set asynchronous clock mode
-    writeReg(master, P9_LL_MODE_REG, 0x00000001);
-
-    for (const auto& t : targets)
-    {
-        //Unfence PLL controls
-        writeRegWithMask(t, P9_ROOT_CTRL0,
-                         0x00000000, 0x00010000);
-
-        //Assert Perv chiplet endpoint reset
-        writeRegWithMask(t, P9_PERV_CTRL0,
-                         0x40000000, 0x40000000);
-
-        //Enable Nest PLL
-        writeRegWithMask(t, P9_PERV_CTRL0,
-                         0x00000001, 0x00000001);
-    }
-}
-
 }
 }
+
diff --git a/procedures/p9/vcs_workaround.cpp b/procedures/p9/vcs_workaround.cpp
new file mode 100644
index 0000000..64b41c1
--- /dev/null
+++ b/procedures/p9/vcs_workaround.cpp
@@ -0,0 +1,64 @@
+/**
+ * Copyright © 2017 IBM Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <phosphor-logging/log.hpp>
+#include "cfam_access.hpp"
+#include "p9_cfam.hpp"
+#include "targeting.hpp"
+
+namespace openpower
+{
+namespace p9
+{
+
+using namespace phosphor::logging;
+using namespace openpower::cfam::access;
+using namespace openpower::cfam::p9;
+using namespace openpower::targeting;
+
+
+/**
+ * @brief Performs the 'VCS Workaround' on all P9s in the system.
+ * @return void
+ */
+void vcsWorkaround()
+{
+    Targeting targets;
+    const auto& master = *(targets.begin());
+
+    log<level::INFO>("Running P9 procedure vcsWorkaround",
+                     entry("NUM_PROCS=%d", targets.size()));
+
+    //Set asynchronous clock mode
+    writeReg(master, P9_LL_MODE_REG, 0x00000001);
+
+    for (const auto& t : targets)
+    {
+        //Unfence PLL controls
+        writeRegWithMask(t, P9_ROOT_CTRL0,
+                         0x00000000, 0x00010000);
+
+        //Assert Perv chiplet endpoint reset
+        writeRegWithMask(t, P9_PERV_CTRL0,
+                         0x40000000, 0x40000000);
+
+        //Enable Nest PLL
+        writeRegWithMask(t, P9_PERV_CTRL0,
+                         0x00000001, 0x00000001);
+    }
+}
+
+}
+}