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author | Raptor Engineering Development Team <support@raptorengineering.com> | 2021-10-29 13:36:31 -0500 |
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committer | Raptor Engineering Development Team <support@raptorengineering.com> | 2021-10-29 13:37:29 -0500 |
commit | 2b48243d7c404f3841f9ebe45aed9c3bee09ebe2 (patch) | |
tree | 33c50b6affd1a0890b7dfd82ef6b875dc8a5b6b4 | |
parent | 9ddbe70ea5e85466c1e24da927b135e62810c93f (diff) | |
download | blackbird-system-fpga-master.tar.gz blackbird-system-fpga-master.zip |
This enables support for the standby-coupled VDDRA 1.2V
power plane on Blackbird planar revision 1.02 and above.
NOTE: When building the FPGA image for Blackbird planar
revision 1.01 or below, PLATFORM_HAS_S2RAM_POWER_PLANES
must be set to 0 to avoid incorrect firmware operation.
-rw-r--r-- | main.v | 63 |
1 files changed, 59 insertions, 4 deletions
@@ -1,9 +1,15 @@ // Copyright © 2017, International Business Machines Corp. -// Copyright © 2017 - 2019 Raptor Engineering, LLC +// Copyright © 2017 - 2021 Raptor Engineering, LLC // All Rights Reserved // // See LICENSE file for licensing details +// Blackbird planar version 1.02 or higher +`define PLATFORM_HAS_S2RAM_POWER_PLANES 1 + +// Blackbird planar version 1.01 or lower +//`define PLATFORM_HAS_S2RAM_POWER_PLANES 0 + module system_fpga_top ( // FPGA clock @@ -230,7 +236,7 @@ module system_fpga_top .D_IN_0(i2c_sda_in) ); - parameter fpga_version = 8'h02; + parameter fpga_version = 8'h03; parameter vendor_id1 = 8'h52; parameter vendor_id2 = 8'h43; parameter vendor_id3 = 8'h53; @@ -251,6 +257,9 @@ module system_fpga_top reg reg_debug_force_enable = 1'b0; reg atx_en_lockout = 1'b0; reg invert_sata_hdd_act_req = 1'b0; + reg s2ram_active = 1'b0; + reg s2ram_active_req = 1'b0; + reg s2ram_active_req_prev = 1'b0; parameter railarray_0 = {RAIL_SIZE{1'b0}}; parameter railarray_1 = {RAIL_SIZE{1'b1}}; // synchronizing signals reg [RAIL_SIZE - 1:0] pg_s1 = {RAIL_SIZE{1'b0}}; @@ -295,6 +304,9 @@ module system_fpga_top parameter i2c_led_config_reg_addr = 8'b00010001; parameter i2c_seq_fail_stat_reg_addr1 = 8'b00011000; parameter i2c_seq_fail_stat_reg_addr2 = 8'b00011001; + parameter i2c_planar_config_reg_addr = 8'b00101100; + parameter i2c_planar_status_reg_addr = 8'b00101110; + parameter i2c_feature_bits_reg_addr = 8'b00101111; parameter i2c_system_override_reg_addr = 8'b00110011; reg [15:0] i2c_pg_reg = 0; reg i2c_clr_err = 1'b0; @@ -515,6 +527,11 @@ module system_fpga_top i2c_led_config_reg_addr: begin invert_sata_hdd_act_req <= i2c_data_from_master[0]; end + i2c_planar_config_reg_addr: begin + if (`PLATFORM_HAS_S2RAM_POWER_PLANES != 0) begin + s2ram_active_req <= i2c_data_from_master[0]; + end + end i2c_system_override_reg_addr: begin atx_force_enable <= i2c_data_from_master[0]; mfr_force_enable <= i2c_data_from_master[1]; @@ -562,6 +579,23 @@ module system_fpga_top i2c_led_config_reg_addr: begin i2c_data_to_master <= {7'b0, invert_sata_hdd_act_req}; end + i2c_planar_config_reg_addr: begin + i2c_data_to_master <= {7'b0, s2ram_active_req}; + end + i2c_planar_status_reg_addr: begin + i2c_data_to_master <= {7'b0, s2ram_active}; + end + i2c_feature_bits_reg_addr: begin + // [7:1] RESERVED + // [0] If 1, platform has suspend to RAM functionality at the power plane level + i2c_data_to_master[7:1] <= 7'b0; + + if (`PLATFORM_HAS_S2RAM_POWER_PLANES == 0) begin + i2c_data_to_master[0] <= 1'b0; + end else begin + i2c_data_to_master[0] <= 1'b1; + end + end i2c_vendor_id_reg_addr1: begin i2c_data_to_master <= vendor_id1; end @@ -763,7 +797,28 @@ module system_fpga_top wait_err_detail = en_buf ^ pg_buf; end end - + + // Handle suspend to RAM power overrides + always @(posedge clk_in) begin + // DDR suspend power shared with VTT PG signal + // Try to reflect actual platform state, assuming the FPGA gets reset if V5_0_DUAL (and thereby VDDRAB) drops out + if (s2ram_active_req) begin + if (en_buf[8]) begin + s2ram_active <= s2ram_active_req & pg_buf[8]; + end else begin + if (!s2ram_active_req_prev) begin + // S2RAM enable attempted when DDR regulators offline + // Force inactive + s2ram_active <= 1'b0; + end + end + end else begin + s2ram_active <= 1'b0; + end + + s2ram_active_req_prev <= s2ram_active_req; + end + // Assign Ports to Enables always @(posedge clk_in) begin atx_en = ~(en_buf[0] | atx_debug_force_enable); @@ -774,7 +829,7 @@ module system_fpga_top vdda_en = en_buf[5] | reg_debug_force_enable; vcsa_en = en_buf[6] | reg_debug_force_enable; vppab_en = en_buf[7] | reg_debug_force_enable; - vddrab_en = en_buf[8] | reg_debug_force_enable; + vddrab_en = en_buf[8] | s2ram_active | reg_debug_force_enable; vttab_en = en_buf[8] | reg_debug_force_enable; end |