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* Add PVR_TYPE_P9PReza Arbab2019-02-101-0/+1
| | | | | | | Enable a new PVR to get us running on another p9 variant. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* capp/phb: Introduce 'struct capp' to hold capp related info in 'struct phb'Vaibhav Jain2019-01-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously struct proc_chip member 'capp_phb3_attached_mask' was used for Power-8 to keep track of PHB attached to the single CAPP on the chip. CAPP on that chip supported a flexible PHB assignment scheme. However since then new chips only support a static assignment i.e a CAPP can only be attached to a specific PEC. Hence instead of using 'proc_chip.capp_phb4_attached_mask' to manage CAPP <-> PEC assignments which needs a global lock (capi_lock) to be updated, we introduce a new struct named 'capp' a pointer to which resides inside struct 'phb4'. Since updates to struct 'phb4' already happen in context of phb_lock; this eliminates the need to use mutex 'capi_lock' while updating 'capp_phb4_attached_mask'. This struct is also used to hold CAPP specific variables such as pointer to the 'struct phb' to which the CAPP is attached, 'capp_xscom_offset' which is the xscom offset to be added to CAPP registers in case there are more than 1 on the chip, 'capp_index' which is the index of the CAPP on the chip, and attached_pe' which is the process endpoint index to which CAPP is attached. Finally member 'chip_id' holds the chip-id thats used for performing xscom read/writes. Also new helpers named capp_xscom_read()/write() are introduced to make access to CAPP xscom registers easier. Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* NX: Add NX coprocessor init opal callHaren Myneni2018-06-181-0/+2
| | | | | | | | | | | | | | | | | | The read offset (4:11) in Receive FIFO control register is incremented by FIFO size whenever CRB read by NX. But the index in RxFIFO has to match with the corresponding entry in FIFO maintained by VAS in kernel. VAS entry is reset to 0 when opening the receive window during driver initialization. So when NX842 is reloaded or in kexec boot, possibility of mismatch between RxFIFO control register and VAS entries in kernel. It could cause CRB failure / timeout from NX. This patch adds nx_coproc_init opal call for kernel to initialize readOffset (4:11) and Queued (15:23) in RxFIFO control register. Fixes: 3b3c5962f432 ("NX: Add P9 NX support for 842 compression engine") CC: stable # v5.8+ Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Add SBE driver supportVasant Hegde2018-04-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SBE (Self Boot Engine) on P9 has two different jobs: - Boot the chip up to the point the core is functional - Provide various services like timer, scom, stash MPIPL, etc., at runtime OPAL can communicate to SBE via a set of data and control registers provided by the PSU block in P9 chip. - Four 8 byte registers for Host to send command packets to SBE - Four 8 byte registers for SBE to send response packets to Host - Two doorbell registers (1 on each side) to alert either party when data is placed in above mentioned data register Protocol constraints: Only one command is accepted in the command buffer until the response for the command is enqueued in the response buffer by SBE. Usage: We will use SBE for various purposes like timer, MPIPL, etc. This patch implements the SBE MBOX spec for OPAL to communicate with SBE. Design consideration: - Each chip has SBE. We need to track SBE messages per chip. Hence added per chip sbe structure and list of messages to that chip - SBE accepts only one command at a time. Hence serialized MBOX commands. - OPAL gets interrupted once SBE sets doorbell register - OPAL has to clear doorbell register after reading response - Every command class has timeout option. Timed out messages are discarded - SBE MBOX commands can be classified into four types : - Those that must be sent to the master only (ex: sending MDST/MDDT info) - Those that must be sent to slaves only (ex: continue MPIPL) - Those that must be sent to all chips (ex: close insecure window) - Those that can be sent to any chip (ex: timer) Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal: Get chip location codeMahesh Salgaonkar2017-12-131-0/+15
| | | | | | | | and store it under proc_chip for quick reference during HMI handling code. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Initialize VAS registersSukadev Bhattiprolu2017-08-011-0/+3
| | | | | | | | | | Initialize the VAS registers on each of instance that we discover. Initializing VAS involves writing either pre-defined values or allocated addresses to appropriate SCOM addresses. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: update phys_map_get API usage] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Define helpers to extract P9 node/chip idsSukadev Bhattiprolu2017-08-011-0/+4
| | | | | | | | VAS needs the node and chip ids to compute the "paste address" of a window. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Find the IMC DTBMadhavan Srinivasan2017-06-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IMC (In Memory Collection) catalog is a repository of information about the Performance Monitoring Units (PMUs) and their events under the IMC infrastructure. The information include : - The PMU names - Event names - Event description - Event offsets - Event scale - Event unit The catalog is provided as a flattened device tree (dtb). Processors with different PVR values may have different PMU or event names. Hence, for each processor, there can be multiple device tree binaries (dtbs) containing the IMC information. Each of the dtb is compressed and forms a sub-partition inside the PNOR partition "IMA_CATALOG". Here is a link to the commit adding this partition to PNOR : https://github.com/open-power/pnor/commit/c940142c6dc64dd176096dc648f433c889919e84 So, each compressed dtb forms a sub-partition inside the IMC pnor partition and can be accessed/loaded through a sub-partition id which is nothing but the PVR id. Based on the current processor's PVR, the appropriate sub-partion will be loaded. Note however, that the catalog information is in the form of a dtb and the dtb is compressed too. So, the sub-partition loaded must be decompressed first before we can actually use it. It is important to mention here that while a PNOR image built for one processor is specific to only that processor and isn't portable, a single system generation (Processor version) may have multiple revisions and these revisions may have some changes in their IMC PMUs and events, and hence, the need for multiple IMC DTBs. The sub-partition that we obtain from the IMC pnor partition is a compressed device tree binary. We uncompress it using the libxz's functions. After uncompressing it, we link the device tree binary to the system's device tree. The kernel can now access the device tree and get the IMC PMUs and their events' information. Not all the IMC PMUs listed in the device tree may be available. This is indicated by imc availability vector (which is a part of the IMC control block structure). We need to check this vector and make sure to remove the IMC device nodes which are unavailable. Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt, fix failure path for resource load] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Enable capi mode for PHB4Christophe Lombard2017-06-191-0/+1
| | | | | | | | | | | | | | | | Enable the Coherently attached processor interface. The PHB is used as a CAPI interface. CAPI Adapters can be connected to either PEC0 or PEC2. Single port CAPI adapter can be connected to either PEC0 or PEC2, but Dual-Port Adapter can be only connected to PEC2 CAPP0 attached to PHB0(PEC0 - single port) CAPP1 attached to PHB3(PEC2 - single or dual port) As we did for PHB3, a new specific file 'phb4-capp.h' is created to contain the CAPP register definitions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* nx: Add POWER9 DARN supportMichael Neuling2017-04-271-0/+1
| | | | | | | | | | | | | | This sets up the per chip RNG MMIO BAR and points the per core DARN BAR at it. This is needed on P9 to enabled the DARN instruction (otherwise it'll cause a xstop). This includes a minor rework of some #defines to abstract MMIO definitions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Grab P9 DD1.0 revision levelBenjamin Herrenschmidt2017-02-021-0/+1
| | | | | | | To differentiate between 1.00, 1.01, 1.02 etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Declare proc_chip_quirks as extern, squash sparse warningStewart Smith2016-10-171-1/+3
| | | | | | | | | include/chip.h:134:3: warning: symbol 'proc_chip_quirks' was not declared. Should it be static? In fact it shouldn't be static, it should just exist *once* and that place is chip.c Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* include: Fix u8 type in chip.hClaudio Carvalho2016-09-141-3/+3
| | | | | | | | | | u8 is defined in ccan/short_types/short_types.h, but chip.h doesn't include it. This just replaces u8 by uint8_t in chip.h. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* chip: Add a quirk for when core direct control XSCOMs are missingBenjamin Herrenschmidt2016-08-221-0/+1
| | | | | | | | Those will be needed by fast reboot. For now, mark qemu and mambo as not having them. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc: Move LPC instance variables to a private structureBenjamin Herrenschmidt2016-08-111-6/+2
| | | | | | | | Take them out of struct proc_chip and into a private struct lpcm that's local to lpc.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* lpc: Add basic P9 LPC read/write opsBenjamin Herrenschmidt2016-07-081-0/+1
| | | | | | | | | | We still need to review interrupts handling etc... Also update the example device-tree for SIMICS Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* XIVE: Base XIVE support for OPAL XICS emulation callsBenjamin Herrenschmidt2016-07-081-0/+4
| | | | | | | | | | | | | This provides basic initialization of the XIVE along with some OPAL calls to emulate an old-style XICS which will initially be used by Linux for backward compatibility. The current implementation is limited to one priority and doesn't expose much to Linux for future exploitation mode yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: add (C) header, fix whitespace, missing breaks] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Timebase quirk for slow simulators like AWAN and SIMICSBenjamin Herrenschmidt2016-07-061-0/+1
| | | | | | | | | | | This will internally pretend the timebase is running 1000 times slower, which reduces some otherwise really terrible delays in some simulators. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: move cfam_chipid cleanup into own patch] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* chip: Add more P9 accessors for converting to/from PIRBenjamin Herrenschmidt2016-07-061-1/+9
| | | | | | | | | To access a local CPU number within a chip essentially, will be used by XIVE Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Allow adding idle states to power-mgt node in mamboShreyas B. Prabhu2016-06-201-2/+1
| | | | | | | | | | | | | | | | | | | This patch removes the check which prevents adding any idle state to "power-mgt" node in mambo. Power8 exposes 3 idle states- nap, fast-sleep and deep-winkle. While fast-sleep depends on SCOMs and deep-winkle depends on SCOMs/SLW, nap has no such dependencies and it can be enabled in mambo. Current code checks for "fast-sleep" in hostboot provided "ibm,enabled-idle-states" dt node for adding fast-sleep and checks for presence of SLW for adding winkle to "power-mgt". Hence with this change only nap will be added to "power-mgt" node in mambo on Power8. On Power9, this patch enables all idle states which don't need SLW. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add base POWER9 supportMichael Neuling2016-05-101-0/+20
| | | | | | | | | | | Add PVR detection, chip id and other misc bits for POWER9. POWER9 changes the location of the HILE and attn enable bits in the HID0 register, so add these definitions also. Signed-off-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: Fix Numbus typo, hdata_to_dt build fixes] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: Load CAPP ucode to both CAPP units on NaplesPhilippe Bergheaud2016-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Venice and Murano have only one capp unit, that can be mapped to phb0, phb1 or phb2. Naples has two capp units, that are statically mapped, capp unit 0 on phb0 and capp unit 1 on phb1. The capp ucode must be loaded once onto each capp unit. This patch replaces the boolean chip->capp_ucode_loaded by a bitmap, and sets the bit corresponding to the phb index to indicate that ucode has been loaded. The macro CAPP_UCODE_LOADED(chip, phb) returns the value of the phb index bit. The xscom register addresses of capp unit 0 are identical to the register addresses of the single capp unit of Venice and Murano. The addresses of the Naples capp unit 1 are equal to the addresses of capp unit 0 + 0x180. This patch introduces the macro PHB3_CAPP_REG_OFFSET(p), that returns the following xscom register address offsets: 0x0 for the Venice capp unit 0x0 for the Murano capp unit 0x0 for Naples capp unit 0 0x180 for Naples capp unit 1 The offset is added to the register address at each xscom_write, in order to operate on the right capp unit. Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Enable Simics UART consoleRyan Grimm2016-03-071-0/+1
| | | | | | | | | | | | | The UART is a simulated ns16550 with memory mapped registers. A /simics dt node is detected and a SIMICS_QUIRK is added to chip quirks similar to MAMBO_CALLOUTS. It can contain an ns16550 dt node with a property console-bar. The LPC UART code is reused and this will work without an LPC bus in the model. Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Skip OCCs for chip that has occ_functional set to falseStewart Smith2015-11-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some simulation environments, we simulate a system close to an ibm-fsp system but with a crucial difference: we don't simulate OCCs. This means that for a P8 (well, a simulated one) that looks like it's part of a ibm-fsp system, we'd wait around for about a minute to be asked to start OCCs and for the OCCs to start. Obviously, this would never happen and we'd hit the OCC initialization timeout (correctly) logging an error. However, in this simulation environment, it isn't an error as the required information to work out it isn't an error is (at least now) provided in hdat under 'OCC Functional State'. Previously, the ibm,occ-functional-state property was just passed through the device tree to the host through the XSCOM node and skiboot ignored it. This patch takes note of occ-functional-state and skips waiting for OCCs on any chips that have been marked as having non functional OCC. In such simulation environments this means we: a) don't log an error that isn't really an error b) boot 1 minute quicker as we don't hit the timeout. Tested-by: Gajendra B Bandhu1 <gbandhu1@in.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fsi-master: Refactor the driverBenjamin Herrenschmidt2015-07-061-0/+4
| | | | | | | | | Move the various base addresses etc... in a per-instance struct mfsi which simplifies the code and will make it easier to add subsequent error handling improvements. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ: Poll OCC throttle status and queue OCC events to hostShilpasri G Bhat2015-07-061-0/+1
| | | | | | | | | | | | | | | | | Add a new class of message definition OPAL_MSG_OCC to opal_message_type to notify the following OCC events to host: 1) OCC Reset 2) OCC Load 3) OCC Throttle Status Change Add an opal poller to periodically read throttle status updated by OCC for each chip and notify any change in throttle status to host. The throttle status indicates the reason why OCC may have limited the max Pstate of the chip. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Preeti U Murthy <preeti@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Support for Naples LPC serial interruptsBenjamin Herrenschmidt2015-06-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This adds support for the HW SerIRQ deserializer of the P8 LPC bridge which is properly wired up on Naples. It also adds support for detecting and reporting LPC error interrupts on all P8s. On most platforms (Rhesus is the exception here due to the way it lets Linux handle the UART interrupts directly), we modify the device-tree to properly represent the LPC controller as a cascaded interrupt-controller and the "interrupts" property of LPC devices to contain the actual LPC interrupt number for the device. We add a mechanism for drivers to register specific LPC interrupts, and a "workaround" for pre-Naples P8 which platforms can use to call all of them for when the external FPGA based deserializer is used. There's also a callback on LPC resets which isn't used yet, we need a bit more work on the general LPC error handling, but it can be done a separate patches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ: Send self-interrupt to chip with active PSIJoel Stanley2015-05-131-0/+3
| | | | | | | | | | | | | | | | | We were previously asking the OCC of the current chip to generate the self interrupt. If Hostboot does not configure all the PSI Host Bridges, so if the current chip happens to have an unconfigured PSI HB, the chip will never see the interrupt. Instead grab a chip id from the list of configured PSIs, and ask the OCC on that chip to generate the self-interrupt. This adds a pointer to the chip's PSI in struct proc_chip so we can use the current chip's PSI if it is active without having to look through all of them. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add Naples chip supportBenjamin Herrenschmidt2015-04-091-0/+1
| | | | | | | | | | This adds the PVR and CFAM ID for the Naples chip. Otherwise treated as a Venice. This doesn't add the definitions for the new PHB revision yet Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Rework microcode flash download and CAPP uploadMichael Neuling2015-02-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | This reworks the CAPP microcode flash download and CAPP upload. We now use load_resource() to download microcode from flash rather than assuming we are on an FSP. This means we can download the microcode on PNOR based systems. Also, currently the code associates the microcode upload with the PHB. This means we store one copy of the microcode for every PHB in the system. This patch changes this so that we only save one copy of the microcode for the whole system. We mark if the microcode as been uploaded in the CAPP unit based on the chip, rather than the PHB. We add a check in case the system has two different chip ECs in the one system but such a Frankenmachine should never be built! We keep the microcode around in case we need it for a recovery event. It also harmonises the CAPP printks to look the same. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Replace is_mambo_chip with a better chip quirk mechanismBenjamin Herrenschmidt2015-02-181-3/+15
| | | | | | | And add some basic qemu quirks Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add tweaks to work in Mambo simulatorBenjamin Herrenschmidt2014-12-011-0/+3
| | | | | | | | | | | Mambo doesn't implement various things such as PBA SCOMs, LPC, ChipTOD, etc... It also provides a special console hook. This adds detection of Mambo via the /mambo node, and enables us to boot all the way to Linux. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* i2c: Use new timer facility and improve interrupts handlingBenjamin Herrenschmidt2014-11-121-0/+5
| | | | | | | | | | We only poll the masters for the chip that got the interrupt and we improve the running of the timers as well. We user the new TIMER_POLL facility to replace the use of the OPAL poller, which simplifies the code further. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Initial commit of Open Source releaseBenjamin Herrenschmidt2014-07-021-0/+151
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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