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* Expose PNOR Flash partitions to host MTD driver via devicetreeTimothy Pearson2019-04-241-0/+1
| | | | Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
* Write boot progress to LPC port 80hStewart Smith2019-04-241-1/+1
| | | | | | | | | | | | | | | | | This is an adaptation of what we currently do for op_display() on FSP machines, inventing an encoding for what we can write into the single byte at LPC port 80h. Port 80h is often used on x86 systems to indicate boot progress/status and dates back a decent amount of time. Since a byte isn't exactly very expressive for everything that can go on (and wrong) during boot, it's all about compromise. Some systems (such as Zaius/Barreleye G2) have a physical dual 7 segment display that display these codes. So far, this has only been driven by hostboot (see hostboot commit 90ec2e65314c). Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head.S: set POWER9 radix HID bit at entryNicholas Piggin2019-04-171-1/+0
| | | | | | | | | | | When running in virtual memory mode, the radix MMU hid bit should not be changed, so set this in the initial boot SPR setup. As a side effect, fast reboot also has HID0:RADIX bit set by the shared spr init, so no need for an explicit call. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* chiptod: Remove unused prototype from headerJordan Niethe2019-04-171-1/+0
| | | | | | | | | There is prototype for chiptod_reset_tb() in include/chiptod.h. However no definition is ever provided, nor is it ever used. Remove the prototype. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/npu2: Dump (more) npu2 registers on link error and HMIsFrederic Barrat2019-04-092-0/+11
| | | | | | | | | | | | | | | | | | We were already logging some NPU registers during an HMI. This patch cleans up a bit how it is done and separates what is global from what is specific to nvlink or opencapi. Since we can now receive an error interrupt when an opencapi link goes down unexpectedly, we also dump the NPU state but we limit it to the registers of the brick which hit the error. The list of registers to dump was worked out with the hw team to allow for proper debugging. For each register, we print the name as found in the NPU workbook, the scom address and the register value. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/npu2: Report errors to the OS if an OpenCAPI brick is fencedFrederic Barrat2019-04-091-0/+1
| | | | | | | | | | | | | | Now that the NPU may report interrupts due to the link going down unexpectedly, report those errors to the OS when queried by the 'next_error' PHB callback. The hardware doesn't support recovery of the link when it goes down unexpectedly. So we report the PHB as dead, so that the OS can log the proper message, notify the drivers and take the devices down. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/npu2: Setup an error interrupt on some opencapi FIRsFrederic Barrat2019-04-091-1/+4
| | | | | | | | | | | | | | | | | | | | Many errors reported in the NPU FIR2 register, mostly catching unexpected errors on the opencapi link are defined as 'brick fatal' in the workbook, yet the default action is set to system checkstop. It's possible to see those errors during AFU development, where the AFU may send unexpected packets on the link, therefore triggering those errors. Checkstopping the system in this case is clearly extreme, as the error could be contained to the brick and proper analysis of a checkstop is not trivial outside of a bringup environment. This patch changes the default action of those errors so that the NPU will raise an interrupt instead. Follow-up patches will log proper information so that the error can be debugged and linux can catch the event. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/npu2: Use NVLink irq setup for OpenCAPIFrederic Barrat2019-04-091-1/+0
| | | | | | | | | | | | | | Start using the irq setup code from NVLink for OpenCAPI, since the 2 versions are so close. There are only 2 differences: - the NPU may trigger more interrupts for OpenCAPI, 35 vs. 23, though none are configured to be triggered for now. - we need to enable the 4 translation faults interrupts for OpenCAPI. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/npu2: Fix OpenCAPI PE assignmentAndrew Donnellan2019-04-091-3/+18
| | | | | | | | | | | | | | | | | | | | When we support mixing NVLink and OpenCAPI devices on the same NPU, we're going to have to share the same range of 16 PE numbers between NVLink and OpenCAPI PHBs. For OpenCAPI devices, PE assignment is only significant for determining which System Interrupt Log register is used for a particular brick - unlike NVLink, it doesn't play any role in determining how links are fenced. Split the PE range into a lower half which is used for NVLink, and an upper half that is used for OpenCAPI, with a fixed PE number assigned per brick. As the PE assignment for OpenCAPI devices is fixed, set the PE once during device init and then ignore calls to the set_pe() operation. Suggested-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal-api: Reserve 2 OPAL API calls for future OpenCAPI LPC useAndrew Donnellan2019-04-091-2/+4
| | | | | | | | | | | | OpenCAPI Lowest Point of Coherency (LPC) memory is going to require some extra OPAL calls to set up NPU BARs. These calls will most likely be called OPAL_NPU_LPC_ALLOC and OPAL_NPU_LPC_RELEASE, we're not quite ready to upstream that code yet though. Reserve 171 and 172 for this purpose. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Force noinline for pci_add_(one_)device_node(s)()Stewart Smith2019-03-291-0/+1
| | | | | | We call all of these things recursively, so don't use excess stack. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/i2c: split i2c_request_send()Oliver O'Halloran2019-03-281-1/+2
| | | | | | | | | | | | | | | Split the i2c_request_send() method into two methods: i2c_request_send() which allocates and populates and i2c_request structure, and i2c_request_sync() which take a request structure and blocks until it completes. This allows code that allocates a i2c_request structure elsewhere to make use of the existing busy-wait and request retry logic. Fix the return types to use int64_t while we're here since these are returning OPAL_API error codes. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/i2c: Add request state trackingOliver O'Halloran2019-03-281-2/+12
| | | | | | | | | Allow the submitter to track the state of an I2C request by adding a state field to the request. This avoids the need to use a stub completion callback in some cases. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/phb4: Drop FRESET_DEASSERT_DELAY stateOliver O'Halloran2019-03-281-1/+0
| | | | | | | | | | | The delay between the ASSERT_DELAY and DEASSERT_DELAY states is set to one timebase tick. This state seems to have been a hold over from PHB3 where it was used to add a 1s delay between de-asserting PERST and polling the link for the CAPI FPGA. There's no requirement for that here since the link polling on PHB4 is a bit smarter so we should be fine. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/phb4: Skip FRESET PERST when coming from CRESETOliver O'Halloran2019-03-281-0/+1
| | | | | | | | | | | | | | | | PERST is asserted at the beginning of the CRESET process to prevent the downstream device from interacting with the host while the PHB logic is being reset and re-initialised. There is at least a 100ms wait during the CRESET processing so it's not necessary to wait this time again in the FRESET handler. This patch extends the delay after re-setting the PHB logic to extend to the 250ms PERST wait period that we typically use and sets the skip_perst flag so that we don't wait this time again in the FRESET handler. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* include/imc: Trace IMC Macro definitionsAnju T Sudhakar2019-03-282-0/+31
| | | | | | | | | | Add macros needed for Trace mode enablement of IMC(In-Memory Collection Counters). These macros are used to identify the trace node in the device-tree and to make appropriate scom calls to enable trace-mode in the hardware. Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/stack: Rename backtrace functions, get rid of wrappersAndrew Donnellan2019-03-281-27/+5
| | | | | | | | | Rename ___backtrace() to backtrace_create() and ___print_backtrace() to backtrace_print(). Get rid of __backtrace() and __print_backtrace() wrappers. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/stack: Convert stack check code to not use backtrace wrapperAndrew Donnellan2019-03-281-1/+1
| | | | | | | | We're about to get rid of __backtrace() and __print_backtrace(), convert the stack check code to not use them. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/stack: Define a backtrace metadata structAndrew Donnellan2019-03-281-12/+28
| | | | | | | | | | | | | | | | Every time we take a backtrace, we have to store the number of entries, the OPAL API token, r1 caller and PIR values. Rather than defining these and passing them around all over the place, let's throw them in a struct. Define a struct, struct bt_metadata, to store these details, and convert ___backtrace() and ___print_backtrace() to use it. We change the wrapper functions __backtrace() and __print_backtrace() to call ___backtrace()/___print_backtrace() with struct bt_metadata, but don't change their parameter profiles for now - we'll do that later. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/stack: Remove r1 argument from ___backtrace()Andrew Donnellan2019-03-281-4/+1
| | | | | | | | | ___backtrace() is always called with r1 = __builtin_frame_address(0), and it's unlikely we're going to need it to do something else any time soon, so simplify the API by removing the parameter. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* xive: Add calls to save/restore the queues and VPs HW stateCédric Le Goater2019-03-281-3/+4
| | | | | | | | | | | | | | | | | To be able to support migration of guests using the XIVE native exploitation mode, (where the queue is effectively owned by the guest), KVM needs to be able to save and restore the HW-modified fields of the queue, such as the current queue producer pointer and generation bit, and to retrieve the modified thread context registers of the VP from the NVT structure : the VP interrupt pending bits. However, there is no need to set back the NVT structure on P9. P10 should be the same. Based on previous work from BenH. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2/hw-procedures: Fix parallel zcal for opencapiFrederic Barrat2019-03-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | For opencapi, we currently do impedance calibration when initializing the PHY for the device, which could run in parallel if we were rich and had multiple opencapi devices. But if 2 devices are on the same obus, the 2 calibration sequences could overlap, which likely yields bad results and is useless anyway since it only needs to be done once per obus. This patch splits the opencapi PHY reset in 2 parts: - a 'init' part called serially at boot. That's when zcal is done. If we have 2 devices on the same socket, the zcal won't be redone, since we're called serially and we'll see it has already be done for the obus - a 'reset' part called during fundamental reset as a prereq for link training. It does the PHY setup for a set of lanes and the dccal. The PHY team confirmed there's no dependency between zcal and the other reset steps and it can be moved earlier. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2-opencapi: Fix adapter reset when using 2 adaptersFrederic Barrat2019-03-131-0/+4
| | | | | | | | | | | | | | | | If two opencapi adapters are on the same obus, we may try to train the two links in parallel at boot time, when all the PCI links are being trained. Both links use the same i2c controller to handle the reset signal, so some care is needed to make sure resetting one doesn't interfere with the reset of the other. We need to keep track of the current state of the i2c controller (and use locking). This went mostly unnoticed as you need to have 2 opencapi cards on the same socket and links tended to train anyway because of the retries. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2-opencapi: Setup perf counters to detect CRC errorsFrederic Barrat2019-03-131-0/+17
| | | | | | | | | | | | | | | | | | | It's possible to set up performance counters for the PLL to detect various conditions for the links in nvlink or opencapi mode. Since those counters are currently unused, let's configure them when an obus is in opencapi mode to detect CRC errors on the link. Each link has two counters: - CRC error detected by the host - CRC error detected by the DLx (NAK received by the host) We also dump the counters shortly after the link trains, but they can be read multiple times through cronus, pdbg or linux. The counters are configured to be reset after each read. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2-opencapi: Rework ODL register accessFrederic Barrat2019-03-131-19/+11
| | | | | | | | | | | | | ODL registers used to control the opencapi link state have an address built on a base address and an offset for each brick which can be computed instead of hard-coded individually for each brick. Rework how we access the ODL registers, to avoid repeating switch statements all over the place. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal/hmi: set a flag to inform OS that TOD/TB has failed.Mahesh Salgaonkar2019-03-051-0/+1
| | | | | | | | | | Set a flag to indicate OS about TOD/TB failure as part of new opal_handle_hmi2 handler. This flag then can be used by OS to make sure functions depending on TB value (e.g. udelay()) are aware of TB not ticking. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Allow ATSD for LPAR other than 0Alexey Kardashevskiy2019-02-251-0/+2
| | | | | | | | | | | | | | | | | Each XTS MMIO ATSD# register is accompanied by another register - XTS MMIO ATSD0 LPARID# - which controls LPID filtering for ATSD transactions. When a host system passes a GPU through to a guest, we need to enable some ATSD for an LPAR. At the moment the host assigns one ATSD to a NVLink bridge and this maps it to an LPAR when GPU is assigned to the LPAR. The link number is used for an ATSD index. ATSD6&7 stay mapped to the host (LPAR=0) all the time which seems to be acceptable price for the simplicity. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Add XTS_BDF_MAP wildcard refcountAlexey Kardashevskiy2019-02-251-0/+2
| | | | | | | | | | | | | | | | | | Currently PID wildcard is programmed into the NPU once and never cleared up. This works for the bare metal as MSR does not change while the host OS is running. However with the device virtualization, we need to keep track of wildcard entries use and clear them up before switching a GPU from a host to a guest or vice versa. This adds refcount to a NPU2, one counter per wildcard entry. The index is a short lparid (4 bits long) which is allocated in opal_npu_map_lpar() and should be smaller than NPU2_XTS_BDF_MAP_SIZE (defined as 16). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Retry link training at PCIe GEN1 if presence detected but training ↵Timothy Pearson2019-02-261-1/+2
| | | | | | | | | | | | | repeatedly failed Certain older PCIe 1.0 devices will not train unless the training process starts at GEN1 speeds. As a last resort when a device will not train, fall back to GEN1 speed for the last training attempt. This is verified to fix devices based on the Conexant CX23888 on the Talos II platform. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> [stewart: cut P9NDD1.0 support, fixup dt_max_link_speed] Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* imc/catalog: Decompress catalog asynchronouslySantosh Sivaraj2019-02-251-0/+1
| | | | | | | | | | | | | | | In-Memory Collection(IMC) counters catalog is compressed blob which is loaded from the flash; decompression starts once the data is loaded from nvram by the main thread. This can be optimized by using the libxz API function which creates a job to do the decompression by not blocking the main thread. Refactor decompress() to use the libxz asynchronous wrapper functions. This also cleans up the error handling path in imc_init(). CC: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Santosh Sivaraj <santosh@fossix.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* flash: Add support for async decompressionSantosh Sivaraj2019-02-251-0/+34
| | | | | | | | | | | | | | | | | Implement a standard API for decompressing images using the existing method found in the IMC code. This patch also standardizes error codes and does the decompression asynchronously. The IMC decompress() function is refactored to decompress blobs/images as a separate CPU job. 'xz_decompress_start()' starts the decompression in a newly created CPU job; while 'wait_xz_decompress()' waits for the job to complete. The IMC code will be first user for the new APIs; whose implementation is provided as reference in the next patch. Signed-off-by: Santosh Sivaraj <santosh@fossix.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* config: Get rid of FAST_REBOOT_CLEARS_MEMORYAndrew Donnellan2019-02-251-3/+0
| | | | | | | | | | FAST_REBOOT_CLEARS_MEMORY is a relic of the initial attempts at fast reboot, which went away in 0279d8951ead ("Fast reboot for P8"). Remove it from config.h as it's misleading. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* config: Get rid of DEBUG_MALLOCAndrew Donnellan2019-02-251-3/+0
| | | | | | | | | | | | Since the initial release of skiboot, we've #defined DEBUG_MALLOC to 1. Also since the initial release of skiboot, DEBUG_MALLOC has been referenced absolutely nowhere. Get rid of it. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* astbmc: Try IPMI HIOMAP for P8 (again)Andrew Jeffery2019-02-251-1/+2
| | | | | | | | | | | | | | | The HIOMAP protocol was developed after the release of P8 in preparation for P9. As a consequence P9 always uses it, but it has rarely been enabled for P8. P8DTU has recently added IPMI HIOMAP support to its BMC firmware, so enable its use in skiboot with P8 machines. Doing so requires some rework to ensure fallback works correctly as in the past the fallback was to mbox, which will only work for P9. Tested on Garrison, Palmetto without HIOMAP, Palmetto with HIOMAP, and Witherspoon. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* hw/bt: Add backend interface to disable ipmi message retry optionVasant Hegde2019-02-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | During boot OPAL makes IPMI_GET_BT_CAPS call to BMC to get BT interface capabilities which includes IPMI message max resend count, message timeout, etc,. Most of the time OPAL gets response from BMC within specified timeout. In some corner cases (like mboxd daemon reset in BMC, BMC reboot, etc) OPAL may not get response within timeout period. In such scenarios, OPAL resends message until max resend count reaches. OPAL uses synchronous IPMI message (ipmi_queue_msg_sync()) for few operations like flash read, write, etc. Thread will wait in OPAL until it gets response from BMC. In some corner cases like BMC reboot, thread may wait in OPAL for long time (more than 20 seconds) and results in kernel hardlockup. This patch introduces new interface to disable message resend option. We will disable message resend option for synchrous message. This will greatly reduces kernel hardlock up issues. This is short term fix. Long term solution is to convert all synchronous messages to asynhrounous one. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal: Deprecate reading the PHB statusAlexey Kardashevskiy2019-02-182-4/+2
| | | | | | | | | | | | | | | | | The OPAL_PCI_EEH_FREEZE_STATUS call takes a bunch of parameters, one of them is @phb_status. It is defined as __be64* and always NULL in the current Linux upstream but if anyone ever decides to read that status, then the PHB3's handler will assume it is struct OpalIoPhb3ErrorData* (which is a lot bigger than 8 bytes) and zero it causing the stack corruption; p7ioc-phb has the same issue. This removes @phb_status from all eeh_freeze_status() hooks and moves the error message from PHB4 to the affected OPAL handlers. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-By: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* phb4: Eliminate peltv_cacheOliver O'Halloran2019-02-181-2/+1
| | | | | | | | | | The PELT-V is also an in-memory table and there is no reason to have two copies of it. Removing the cache shaves another 128KB off the size of each struct phb4. Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* phb4: Eliminate p->rte_cacheOliver O'Halloran2019-02-181-2/+1
| | | | | | | | | | | | | | | | | In ancient times we added a caches to struct phb3 for some of the IODA tables which can only be accessed in-directly via XSCOM. A cache for the Requester Translation Table (RTT) was also added even though this is an in-memory table. This was carried over to PHB4 when Ben did the initial copy and paste, but it's still largely pointless. There's no real need to have a second copy of the table. This patch removes the "cache" and changes all the users to reference the RTT directly if we need to. This reduces the size of the struct phb4 by 128KB. Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: implement support for MCE interrupts in powersaveNicholas Piggin2019-02-132-2/+4
| | | | | | | | | | | | | | The ISA specifies that MCE interrupts in power saving modes will enter at 0x200 with powersave bits in SRR1 set. This is not currently supported properly, the MCE will just happen like a normal interrupt, but GPRs could be lost, which would lead to crashes (e.g., r1, r2, r13 etc). So check the power save bits similarly to the sreset vector, and handle this properly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: allow recoverable sreset exceptionsNicholas Piggin2019-02-131-2/+2
| | | | | | | | This requires implementing the MSR[RI] bit. Then just allow all non-fatal sreset exceptions to recover. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: implement an exception handler for non-powersave sresetsNicholas Piggin2019-02-132-0/+9
| | | | | | | | Detect non-powersave sresets and send them to the normal exception handler which prints registers and stack. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* asm/head: sreset handler remove FIXUP_ENDIANNicholas Piggin2019-02-131-0/+12
| | | | | | | | | | | | Remove FIXUP_ENDIAN from the normal sreset handler (not the fast reboot handler), to prevent it from trashing registers and CFAR. This mean sreset can be used to report a reliable register dump, and even be recoverable. A watchdog could be implemented to catch and diagnose stuck CPUs during boot using sreset. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/fast-reboot: fast reboot specific sreset patchNicholas Piggin2019-02-131-0/+3
| | | | | | | | | | | | Provide an sreset handler specifically for fast reboots, which allows FIXUP_ENDIAN to be removed from the normal sreset handler in the next patch. The save_1 == 0 condition is no longer required to signal a fast reboot. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/exceptions: save current MSR in exception frameNicholas Piggin2019-02-121-0/+1
| | | | | | | | | Save and print the MSR of the interrupt context. This can be derived from the interrupt type, SRR1, and other system register settings. But it can be useful to quickly verify what's happening. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/cpu: do not inline cpu_relaxNicholas Piggin2019-02-121-11/+1
| | | | | | | | | The added nops now push it up in size, and -Os uninlines it for every compilation unit that calls it more than once, so it's much better to just uninline. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/init: rename setup_reset_vectorNicholas Piggin2019-02-121-1/+1
| | | | | | | Use the word copy, to match copy_exception_vectors. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Add PVR_TYPE_P9PReza Arbab2019-02-102-0/+2
| | | | | | | Enable a new PVR to get us running on another p9 variant. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Revert "astbmc: Try IPMI HIOMAP for P8"Joel Stanley2019-02-101-2/+1
| | | | | | | | | | | | | | | | | | | This reverts commit bd9839684d482417e8c60449592f4308e9a91dac as it broke booting on P8 systems, including Garrison (AMI BMC), Firestone (AMI BMC) and QEMU (BMC simulator). Issue https://github.com/open-power/skiboot/issues/217 tracks the failure. The P8 IPMI HIOMAP feature can be re-enabled once this issue is resolved. Reported-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Reported-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Acked-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Tested-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Remove POWER9N DD1 supportNicholas Piggin2019-01-252-10/+0
| | | | | | | | This is not a shipping product and is no longer supported by Linux or other firmware components. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* astbmc: Try IPMI HIOMAP for P8Andrew Jeffery2019-01-181-1/+2
| | | | | | | | | | | | The HIOMAP protocol was developed after the release of P8 in preparation for P9. As a consequence P9 always uses it, but it has rarely been enabled for P8. P8DTU has recently added IPMI HIOMAP support to its BMC firmware, so enable its use in skiboot with P8 machines. Doing so requires some rework to ensure fallback works correctly as in the past the fallback was to mbox, which will only work for P9. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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