diff options
Diffstat (limited to 'board/amcc/ocotea')
| -rw-r--r-- | board/amcc/ocotea/Makefile | 47 | ||||
| -rw-r--r-- | board/amcc/ocotea/config.mk | 44 | ||||
| -rw-r--r-- | board/amcc/ocotea/flash.c | 150 | ||||
| -rw-r--r-- | board/amcc/ocotea/init.S | 97 | ||||
| -rw-r--r-- | board/amcc/ocotea/ocotea.c | 527 | ||||
| -rw-r--r-- | board/amcc/ocotea/ocotea.h | 140 | ||||
| -rw-r--r-- | board/amcc/ocotea/u-boot.lds | 155 |
7 files changed, 1160 insertions, 0 deletions
diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile new file mode 100644 index 0000000000..af223d2c55 --- /dev/null +++ b/board/amcc/ocotea/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk new file mode 100644 index 0000000000..5543a4eabd --- /dev/null +++ b/board/amcc/ocotea/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IBM 440GX Reference Platform (Ocotea) board +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c new file mode 100644 index 0000000000..5614e20780 --- /dev/null +++ b/board/amcc/ocotea/flash.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +#undef DEBUG + +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +#define BOOT_SMALL_FLASH_VAL 4 +#define FLASH_ONBD_N_VAL 2 +#define FLASH_SRAM_SEL_VAL 1 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ + {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ + {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ + {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ + {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ + {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ + {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ + {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned char switch_status; + unsigned short index = 0; + int i; + + /* read FPGA base register FPGA_REG0 */ + switch_status = *fpga_base; + + /* check the bitmap of switch status */ + if (switch_status & BOOT_SMALL_FLASH) { + index += BOOT_SMALL_FLASH_VAL; + } + if (switch_status & FLASH_ONBD_N) { + index += FLASH_ONBD_N_VAL; + } + if (switch_status & FLASH_SRAM_SEL) { + index += FLASH_SRAM_SEL_VAL; + } + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = + flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf + ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S new file mode 100644 index 0000000000..e33427a108 --- /dev/null +++ b/board/amcc/ocotea/init.S @@ -0,0 +1,97 @@ +/* +* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c new file mode 100644 index 0000000000..5f436eaeee --- /dev/null +++ b/board/amcc/ocotea/ocotea.c @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2004 PaulReynolds@lhsolutions.com + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include "ocotea.h" +#include <asm/processor.h> +#include <spd_sdram.h> +#include <440gx_enet.h> + +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +long int fixed_sdram (void); +void fpga_init (void); + +int board_early_init_f (void) +{ + unsigned long mfr; + unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; + unsigned char switch_status; + unsigned long cs0_base; + unsigned long cs0_size; + unsigned long cs0_twt; + unsigned long cs2_base; + unsigned long cs2_size; + unsigned long cs2_twt; + + /*-------------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------------*/ + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | + EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | + EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); + + /*-------------------------------------------------------------------------+ + | FPGA. Initialize bank 7 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /* read FPGA base register FPGA_REG0 */ + switch_status = *fpga_base; + + if (switch_status & 0x40) { + cs0_base = 0xFFE00000; + cs0_size = EBC_BXCR_BS_2MB; + cs0_twt = 8; + cs2_base = 0xFF800000; + cs2_size = EBC_BXCR_BS_4MB; + cs2_twt = 10; + } else { + cs0_base = 0xFFC00000; + cs0_size = EBC_BXCR_BS_4MB; + cs0_twt = 10; + cs2_base = 0xFF800000; + cs2_size = EBC_BXCR_BS_2MB; + cs2_twt = 8; + } + + /*-------------------------------------------------------------------------+ + | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)| + cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| + EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------------+ + | 4 MB FLASH. Initialize bank 2 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)| + cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------------+ + | FPGA. Initialize bank 7 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); /* */ + mtdcr (uicb0tr, 0x00000000); /* */ + mtdcr (uicb0vr, 0x00000001); /* */ + mfsdr (sdr_mfr, mfr); + mfr &= ~SDR0_MFR_ECS_MASK; +/* mtsdr(sdr_mfr, mfr); */ + fpga_init(); + + return 0; +} + + +int checkboard (void) +{ + sys_info_t sysinfo; + unsigned char *s = getenv ("serial#"); + + get_sys_info (&sysinfo); + + printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board"); + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); + return (0); +} + + +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 128 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay (400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + for (;;) { + mfsdram (mem_mcsts, reg); + if (reg & 0x80000000) + break; + } + + return (128 * 1024 * 1024); /* 128 MB */ +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The ocotea board is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* The ocotea board is always configured as host. */ + return(1); +} +#endif /* defined(CONFIG_PCI) */ + + +void fpga_init(void) +{ + unsigned long group; + unsigned long sdr0_pfc0; + unsigned long sdr0_pfc1; + unsigned long sdr0_cust0; + unsigned long pvr; + + mfsdr (sdr_pfc0, sdr0_pfc0); + mfsdr (sdr_pfc1, sdr0_pfc1); + group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); + pvr = get_pvr (); + + sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; + if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { + sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; + out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | + FPGA_REG2_EXT_INTFACE_ENABLE); + mtsdr (sdr_pfc0, sdr0_pfc0); + mtsdr (sdr_pfc1, sdr0_pfc1); + } else { + sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; + switch (group) + { + case 0: + case 1: + case 2: + /* CPU trace A */ + out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | + FPGA_REG2_EXT_INTFACE_ENABLE); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; + mtsdr (sdr_pfc0, sdr0_pfc0); + mtsdr (sdr_pfc1, sdr0_pfc1); + break; + case 3: + case 4: + case 5: + case 6: + /* CPU trace B - Over EBMI */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; + mtsdr (sdr_pfc0, sdr0_pfc0); + mtsdr (sdr_pfc1, sdr0_pfc1); + out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | + FPGA_REG2_EXT_INTFACE_DISABLE); + break; + } + } + + /* Initialize the ethernet specific functions in the fpga */ + mfsdr(sdr_pfc1, sdr0_pfc1); + mfsdr(sdr_cust0, sdr0_cust0); + if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && + ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || + (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) + { + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | + FPGA_REG3_ENET_GROUP7); + } + else + { + if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | + FPGA_REG3_ENET_GROUP7); + } + else + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | + FPGA_REG3_ENET_GROUP8); + } + } + } + else + { + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | + FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); + } + else + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | + FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); + } + } + out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | + FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | + FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); + + /* reset the gigabyte phy if necessary */ + if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) + { + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) + { + out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); + udelay(10000); + out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); + } + else + { + out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); + udelay(10000); + out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); + } + } + + /* Turn off the LED's */ + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | + FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | + FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); + + return; +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} +#endif diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h new file mode 100644 index 0000000000..41bd4500d6 --- /dev/null +++ b/board/amcc/ocotea/ocotea.h @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Board specific FPGA stuff ... */ +#define FPGA_REG0 (CFG_FPGA_BASE + 0x00) +#define FPGA_REG0_SSCG_MASK 0x80 +#define FPGA_REG0_SSCG_DISABLE 0x00 +#define FPGA_REG0_SSCG_ENABLE 0x80 +#define FPGA_REG0_BOOT_MASK 0x40 +#define FPGA_REG0_BOOT_LARGE_FLASH 0x00 +#define FPGA_REG0_BOOT_SMALL_FLASH 0x40 +#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ARBITER_MASK 0x04 +#define FPGA_REG0_ARBITER_EXT 0x00 +#define FPGA_REG0_ARBITER_INT 0x04 +#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 +#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 +#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 +#define FPGA_REG0_FLASH 0x01 +#define FPGA_REG1 (CFG_FPGA_BASE + 0x01) +#define FPGA_REG1_9772_FSELFBX_MASK 0x80 +#define FPGA_REG1_9772_FSELFBX_6 0x00 +#define FPGA_REG1_9772_FSELFBX_10 0x80 +#define FPGA_REG1_9531_SX_MASK 0x60 +#define FPGA_REG1_9531_SX_33MHZ 0x00 +#define FPGA_REG1_9531_SX_100MHZ 0x20 +#define FPGA_REG1_9531_SX_66MHZ 0x40 +#define FPGA_REG1_9531_SX_133MHZ 0x60 +#define FPGA_REG1_9772_FSELBX_MASK 0x18 +#define FPGA_REG1_9772_FSELBX_4 0x00 +#define FPGA_REG1_9772_FSELBX_6 0x08 +#define FPGA_REG1_9772_FSELBX_8 0x10 +#define FPGA_REG1_9772_FSELBX_10 0x18 +#define FPGA_REG1_SOURCE_MASK 0x07 +#define FPGA_REG1_SOURCE_TC 0x00 +#define FPGA_REG1_SOURCE_66MHZ 0x01 +#define FPGA_REG1_SOURCE_50MHZ 0x02 +#define FPGA_REG1_SOURCE_33MHZ 0x03 +#define FPGA_REG1_SOURCE_25MHZ 0x04 +#define FPGA_REG1_SOURCE_SSDIV1 0x05 +#define FPGA_REG1_SOURCE_SSDIV2 0x06 +#define FPGA_REG1_SOURCE_SSDIV4 0x07 +#define FPGA_REG2 (CFG_FPGA_BASE + 0x02) +#define FPGA_REG2_TC0 0x80 +#define FPGA_REG2_TC1 0x40 +#define FPGA_REG2_TC2 0x20 +#define FPGA_REG2_TC3 0x10 +#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ +#define FPGA_REG2_EXT_INTFACE_MASK 0x04 +#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 +#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 +#define FPGA_REG2_DEFAULT_UART1_N 0x01 +#define FPGA_REG3 (CFG_FPGA_BASE + 0x03) +#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ +#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ +#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ +#define FPGA_REG3_ENET_GROUP0 0x00 +#define FPGA_REG3_ENET_GROUP1 0x10 +#define FPGA_REG3_ENET_GROUP2 0x20 +#define FPGA_REG3_ENET_GROUP3 0x30 +#define FPGA_REG3_ENET_GROUP4 0x40 +#define FPGA_REG3_ENET_GROUP5 0x50 +#define FPGA_REG3_ENET_GROUP6 0x60 +#define FPGA_REG3_ENET_GROUP7 0x70 +#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ +#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ +#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ +#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ +#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ +#define FPGA_REG3_STAT_MASK 0x0F +#define FPGA_REG3_STAT_LED8_ENAB 0x08 +#define FPGA_REG3_STAT_LED4_ENAB 0x04 +#define FPGA_REG3_STAT_LED2_ENAB 0x02 +#define FPGA_REG3_STAT_LED1_ENAB 0x01 +#define FPGA_REG3_STAT_LED8_DISAB 0x00 +#define FPGA_REG3_STAT_LED4_DISAB 0x00 +#define FPGA_REG3_STAT_LED2_DISAB 0x00 +#define FPGA_REG3_STAT_LED1_DISAB 0x00 +#define FPGA_REG4 (CFG_FPGA_BASE + 0x04) +#define FPGA_REG4_GPHY_MODE10 0x80 +#define FPGA_REG4_GPHY_MODE100 0x40 +#define FPGA_REG4_GPHY_MODE1000 0x20 +#define FPGA_REG4_GPHY_FRC_DPLX 0x10 +#define FPGA_REG4_GPHY_ANEG_DIS 0x08 +#define FPGA_REG4_CONNECT_PHYS 0x04 + + +#define SDR0_CUST0_ENET3_MASK 0x00000080 +#define SDR0_CUST0_ENET3_COPPER 0x00000000 +#define SDR0_CUST0_ENET3_FIBER 0x00000080 +#define SDR0_CUST0_RGMII3_MASK 0x00000070 +#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) +#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) +#define SDR0_CUST0_RGMII3_DISAB 0x00000000 +#define SDR0_CUST0_RGMII3_RTBI 0x00000040 +#define SDR0_CUST0_RGMII3_RGMII 0x00000050 +#define SDR0_CUST0_RGMII3_TBI 0x00000060 +#define SDR0_CUST0_RGMII3_GMII 0x00000070 +#define SDR0_CUST0_ENET2_MASK 0x00000008 +#define SDR0_CUST0_ENET2_COPPER 0x00000000 +#define SDR0_CUST0_ENET2_FIBER 0x00000008 +#define SDR0_CUST0_RGMII2_MASK 0x00000007 +#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) +#define SDR0_CUST0_RGMII2_DISAB 0x00000000 +#define SDR0_CUST0_RGMII2_RTBI 0x00000004 +#define SDR0_CUST0_RGMII2_RGMII 0x00000005 +#define SDR0_CUST0_RGMII2_TBI 0x00000006 +#define SDR0_CUST0_RGMII2_GMII 0x00000007 diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds new file mode 100644 index 0000000000..a9852461e1 --- /dev/null +++ b/board/amcc/ocotea/u-boot.lds @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/ocotea/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} |
