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-rw-r--r--arch/arm/include/asm/arch-am33xx/mmc_host_def.h140
-rw-r--r--arch/arm/include/asm/arch-am33xx/spl.h1
-rw-r--r--arch/arm/include/asm/arch-am33xx/sys_proto.h2
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9x5.h6
-rw-r--r--arch/arm/include/asm/arch-davinci/gpio.h7
-rw-r--r--arch/arm/include/asm/arch-mx35/spl.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h12
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h8
-rw-r--r--arch/arm/include/asm/arch-mx6/iomux.h5
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-ddr.h85
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-pins.h31
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6dl-ddr.h71
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6dl_pins.h193
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6q-ddr.h69
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6q_pins.h1671
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6x_pins.h1671
-rw-r--r--arch/arm/include/asm/arch-mx6/mxc_hdmi.h1083
-rw-r--r--arch/arm/include/asm/arch-mxs/dma.h19
-rw-r--r--arch/arm/include/asm/arch-mxs/imx-regs.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/iomux.h5
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-ssp.h26
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-timrot.h101
-rw-r--r--arch/arm/include/asm/arch-omap3/dss.h31
-rw-r--r--arch/arm/include/asm/arch-omap3/mmc_host_def.h139
-rw-r--r--arch/arm/include/asm/arch-omap3/spl.h2
-rw-r--r--arch/arm/include/asm/arch-omap4/clocks.h562
-rw-r--r--arch/arm/include/asm/arch-omap4/mmc_host_def.h140
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h34
-rw-r--r--arch/arm/include/asm/arch-omap4/spl.h2
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/clocks.h539
-rw-r--r--arch/arm/include/asm/arch-omap5/mmc_host_def.h140
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_dra7xx.h344
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_omap5.h8
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h125
-rw-r--r--arch/arm/include/asm/arch-omap5/spl.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h10
-rw-r--r--arch/arm/include/asm/arch-tegra/mmc.h2
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra_i2c.h6
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra_mmc.h48
-rw-r--r--arch/arm/include/asm/arch-tegra/usb.h (renamed from arch/arm/include/asm/arch-tegra20/usb.h)22
-rw-r--r--arch/arm/include/asm/arch-tegra114/gp_padctrl.h34
-rw-r--r--arch/arm/include/asm/arch-tegra114/pinmux.h246
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra.h1
-rw-r--r--arch/arm/include/asm/arch-tegra30/gp_padctrl.h6
-rw-r--r--arch/arm/include/asm/arch-tegra30/pinmux.h67
-rw-r--r--arch/arm/include/asm/arch-tegra30/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h85
-rw-r--r--arch/arm/include/asm/arch-zynq/sys_proto.h30
-rw-r--r--arch/arm/include/asm/armv7.h1
-rw-r--r--arch/arm/include/asm/emif.h20
-rw-r--r--arch/arm/include/asm/omap_common.h523
-rw-r--r--arch/arm/include/asm/omap_mmc.h168
53 files changed, 4357 insertions, 4194 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 1f597c0eec..33c9c83892 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -16,148 +16,12 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x48060100
#define OMAP_HSMMC2_BASE 0x481D8100
-typedef struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-} hsmmc_t;
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 644ff353fe..e961ce0578 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -29,6 +29,7 @@
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
+#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 588d8de82f..97ab60d1b2 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -35,5 +35,7 @@ void ddr_pll_config(unsigned int ddrpll_M);
void sdelay(unsigned long);
void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size);
void omap_nand_switch_ecc(int);
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h
index de0f1b1923..b7d1932f42 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h
@@ -140,12 +140,6 @@
/*
* Cpu Name
*/
-#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15"
-#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25"
-#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35"
-#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25"
-#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35"
-#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type"
#define ATMEL_CPU_NAME get_cpu_name()
/*
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/include/asm/arch-davinci/gpio.h
index 5206b12211..06390c85e1 100644
--- a/arch/arm/include/asm/arch-davinci/gpio.h
+++ b/arch/arm/include/asm/arch-davinci/gpio.h
@@ -65,15 +65,16 @@ struct davinci_gpio_bank {
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
+#define gpio_status() gpio_info()
+#define GPIO_NAME_SIZE 20
#if defined(CONFIG_SOC_DM644X)
/* GPIO0 to GPIO53, omit the V3.3 volts one */
#define MAX_NUM_GPIOS 70
+#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#define MAX_NUM_GPIOS 128
#else
#define MAX_NUM_GPIOS 144
#endif
-
-#define gpio_status() gpio_info()
-#define GPIO_NAME_SIZE 20
#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
#define GPIO_BIT(gp) ((gp) & 0x1F)
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
index 91d11ae847..3ca4c94680 100644
--- a/arch/arm/include/asm/arch-mx35/spl.h
+++ b/arch/arm/include/asm/arch-mx35/spl.h
@@ -27,7 +27,7 @@
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index d670f30c02..76764571a7 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,6 +20,17 @@
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define CCM_CCGR0 0x020C4068
+#define CCM_CCGR1 0x020C406c
+#define CCM_CCGR2 0x020C4070
+#define CCM_CCGR3 0x020C4074
+#define CCM_CCGR4 0x020C4078
+#define CCM_CCGR5 0x020C407c
+#define CCM_CCGR6 0x020C4080
+
+#define PMU_MISC2 0x020C8170
+
+#ifndef __ASSEMBLY__
struct mxc_ccm_reg {
u32 ccr; /* 0x0000 */
u32 ccdr;
@@ -105,6 +116,7 @@ struct mxc_ccm_reg {
u32 analog_pfd_528_clr;
u32 analog_pfd_528_tog;
};
+#endif
/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN (1 << 27)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3eb0081ca8..eaa7439486 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -601,5 +601,13 @@ struct iomuxc_base_regs {
u32 daisy[104]; /* 0x7b0..94c */
};
+struct wdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Miscellaneous Control */
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index d23abd764a..d67f600068 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -16,6 +16,11 @@
#ifndef __ASM_ARCH_IOMUX_H__
#define __ASM_ARCH_IOMUX_H__
+
+#define MX6_IOMUXC_GPR4 0x020e0010
+#define MX6_IOMUXC_GPR6 0x020e0018
+#define MX6_IOMUXC_GPR7 0x020e001c
+
/*
* IOMUXC_GPR13 bit fields
*/
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
new file mode 100644
index 0000000000..1fdc1d48b3
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6_DDR_H__
+#define __ASM_ARCH_MX6_DDR_H__
+
+#ifdef CONFIG_MX6Q
+#include "mx6q-ddr.h"
+#else
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#include "mx6dl-ddr.h"
+#else
+#error "Please select cpu"
+#endif /* CONFIG_MX6DL or CONFIG_MX6S */
+#endif /* CONFIG_MX6Q */
+
+#define MX6_MMDC_P0_MDCTL 0x021b0000
+#define MX6_MMDC_P0_MDPDC 0x021b0004
+#define MX6_MMDC_P0_MDOTC 0x021b0008
+#define MX6_MMDC_P0_MDCFG0 0x021b000c
+#define MX6_MMDC_P0_MDCFG1 0x021b0010
+#define MX6_MMDC_P0_MDCFG2 0x021b0014
+#define MX6_MMDC_P0_MDMISC 0x021b0018
+#define MX6_MMDC_P0_MDSCR 0x021b001c
+#define MX6_MMDC_P0_MDREF 0x021b0020
+#define MX6_MMDC_P0_MDRWD 0x021b002c
+#define MX6_MMDC_P0_MDOR 0x021b0030
+#define MX6_MMDC_P0_MDASP 0x021b0040
+#define MX6_MMDC_P0_MAPSR 0x021b0404
+#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
+#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
+#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
+#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
+#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
+#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
+#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
+#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
+#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
+#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
+#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
+#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
+#define MX6_MMDC_P0_MPMUR0 0x021b08b8
+
+#define MX6_MMDC_P1_MDCTL 0x021b4000
+#define MX6_MMDC_P1_MDPDC 0x021b4004
+#define MX6_MMDC_P1_MDOTC 0x021b4008
+#define MX6_MMDC_P1_MDCFG0 0x021b400c
+#define MX6_MMDC_P1_MDCFG1 0x021b4010
+#define MX6_MMDC_P1_MDCFG2 0x021b4014
+#define MX6_MMDC_P1_MDMISC 0x021b4018
+#define MX6_MMDC_P1_MDSCR 0x021b401c
+#define MX6_MMDC_P1_MDREF 0x021b4020
+#define MX6_MMDC_P1_MDRWD 0x021b402c
+#define MX6_MMDC_P1_MDOR 0x021b4030
+#define MX6_MMDC_P1_MDASP 0x021b4040
+#define MX6_MMDC_P1_MAPSR 0x021b4404
+#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
+#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
+#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
+#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
+#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
+#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
+#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
+#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
+#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
+#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
+#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
+#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
+#define MX6_MMDC_P1_MPMUR0 0x021b48b8
+
+#endif /*__ASM_ARCH_MX6_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
new file mode 100644
index 0000000000..63f485666a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6_PINS_H__
+#define __ASM_ARCH_MX6_PINS_H__
+
+#ifdef CONFIG_MX6Q
+#include "mx6q_pins.h"
+#else
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#include "mx6dl_pins.h"
+#else
+#error "Please select cpu"
+#endif /* CONFIG_MX6DL or CONFIG_MX6S */
+#endif /* CONFIG_MX6Q */
+
+#endif /*__ASM_ARCH_MX6_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
new file mode 100644
index 0000000000..325da3314a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6DLS_DDR_H__
+#define __ASM_ARCH_MX6DLS_DDR_H__
+
+#ifndef CONFIG_MX6DL
+#ifndef CONFIG_MX6S
+#error "wrong CPU"
+#endif
+#endif
+
+#define MX6_IOM_DRAM_DQM0 0x020e0470
+#define MX6_IOM_DRAM_DQM1 0x020e0474
+#define MX6_IOM_DRAM_DQM2 0x020e0478
+#define MX6_IOM_DRAM_DQM3 0x020e047c
+#define MX6_IOM_DRAM_DQM4 0x020e0480
+#define MX6_IOM_DRAM_DQM5 0x020e0484
+#define MX6_IOM_DRAM_DQM6 0x020e0488
+#define MX6_IOM_DRAM_DQM7 0x020e048c
+
+#define MX6_IOM_DRAM_CAS 0x020e0464
+#define MX6_IOM_DRAM_RAS 0x020e0490
+#define MX6_IOM_DRAM_RESET 0x020e0494
+#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
+#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
+#define MX6_IOM_DRAM_SDBA2 0x020e04a0
+#define MX6_IOM_DRAM_SDCKE0 0x020e04a4
+#define MX6_IOM_DRAM_SDCKE1 0x020e04a8
+#define MX6_IOM_DRAM_SDODT0 0x020e04b4
+#define MX6_IOM_DRAM_SDODT1 0x020e04b8
+
+#define MX6_IOM_DRAM_SDQS0 0x020e04bc
+#define MX6_IOM_DRAM_SDQS1 0x020e04c0
+#define MX6_IOM_DRAM_SDQS2 0x020e04c4
+#define MX6_IOM_DRAM_SDQS3 0x020e04c8
+#define MX6_IOM_DRAM_SDQS4 0x020e04cc
+#define MX6_IOM_DRAM_SDQS5 0x020e04d0
+#define MX6_IOM_DRAM_SDQS6 0x020e04d4
+#define MX6_IOM_DRAM_SDQS7 0x020e04d8
+
+#define MX6_IOM_GRP_B0DS 0x020e0764
+#define MX6_IOM_GRP_B1DS 0x020e0770
+#define MX6_IOM_GRP_B2DS 0x020e0778
+#define MX6_IOM_GRP_B3DS 0x020e077c
+#define MX6_IOM_GRP_B4DS 0x020e0780
+#define MX6_IOM_GRP_B5DS 0x020e0784
+#define MX6_IOM_GRP_B6DS 0x020e078c
+#define MX6_IOM_GRP_B7DS 0x020e0748
+#define MX6_IOM_GRP_ADDDS 0x020e074c
+#define MX6_IOM_DDRMODE_CTL 0x020e0750
+#define MX6_IOM_GRP_DDRPKE 0x020e0754
+#define MX6_IOM_GRP_DDRMODE 0x020e0760
+#define MX6_IOM_GRP_CTLDS 0x020e076c
+#define MX6_IOM_GRP_DDR_TYPE 0x020e0774
+
+#endif /*__ASM_ARCH_MX6S_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 79e2c4f5a4..9494e4126a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -50,100 +50,103 @@
#define NO_MUX_I 0
#define NO_PAD_I 0
enum {
- MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
- MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
- MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
- MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
- MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
- MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
- MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
- MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
- MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
- MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
- MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
- MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
- MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
- MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
- MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
- MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
- MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
- MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
- MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
- MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
- MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
- MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
- MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
- MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
- MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+ MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+ MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+ MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+ MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+ MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+ MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+ MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
+ MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
+ MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+ MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
+ MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
+ MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
+ MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
+ MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+ MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+ MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
new file mode 100644
index 0000000000..e51727c389
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6Q_DDR_H__
+#define __ASM_ARCH_MX6Q_DDR_H__
+
+#ifndef CONFIG_MX6Q
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0 0x020e05ac
+#define MX6_IOM_DRAM_DQM1 0x020e05b4
+#define MX6_IOM_DRAM_DQM2 0x020e0528
+#define MX6_IOM_DRAM_DQM3 0x020e0520
+#define MX6_IOM_DRAM_DQM4 0x020e0514
+#define MX6_IOM_DRAM_DQM5 0x020e0510
+#define MX6_IOM_DRAM_DQM6 0x020e05bc
+#define MX6_IOM_DRAM_DQM7 0x020e05c4
+
+#define MX6_IOM_DRAM_CAS 0x020e056c
+#define MX6_IOM_DRAM_RAS 0x020e0578
+#define MX6_IOM_DRAM_RESET 0x020e057c
+#define MX6_IOM_DRAM_SDCLK_0 0x020e0588
+#define MX6_IOM_DRAM_SDCLK_1 0x020e0594
+#define MX6_IOM_DRAM_SDBA2 0x020e058c
+#define MX6_IOM_DRAM_SDCKE0 0x020e0590
+#define MX6_IOM_DRAM_SDCKE1 0x020e0598
+#define MX6_IOM_DRAM_SDODT0 0x020e059c
+#define MX6_IOM_DRAM_SDODT1 0x020e05a0
+
+#define MX6_IOM_DRAM_SDQS0 0x020e05a8
+#define MX6_IOM_DRAM_SDQS1 0x020e05b0
+#define MX6_IOM_DRAM_SDQS2 0x020e0524
+#define MX6_IOM_DRAM_SDQS3 0x020e051c
+#define MX6_IOM_DRAM_SDQS4 0x020e0518
+#define MX6_IOM_DRAM_SDQS5 0x020e050c
+#define MX6_IOM_DRAM_SDQS6 0x020e05b8
+#define MX6_IOM_DRAM_SDQS7 0x020e05c0
+
+#define MX6_IOM_GRP_B0DS 0x020e0784
+#define MX6_IOM_GRP_B1DS 0x020e0788
+#define MX6_IOM_GRP_B2DS 0x020e0794
+#define MX6_IOM_GRP_B3DS 0x020e079c
+#define MX6_IOM_GRP_B4DS 0x020e07a0
+#define MX6_IOM_GRP_B5DS 0x020e07a4
+#define MX6_IOM_GRP_B6DS 0x020e07a8
+#define MX6_IOM_GRP_B7DS 0x020e0748
+#define MX6_IOM_GRP_ADDDS 0x020e074c
+#define MX6_IOM_DDRMODE_CTL 0x020e0750
+#define MX6_IOM_GRP_DDRPKE 0x020e0758
+#define MX6_IOM_GRP_DDRMODE 0x020e0774
+#define MX6_IOM_GRP_CTLDS 0x020e078c
+#define MX6_IOM_GRP_DDR_TYPE 0x020e0798
+
+#endif /*__ASM_ARCH_MX6Q_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
new file mode 100644
index 0000000000..1c1c00855f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -0,0 +1,1671 @@
+/*
+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__
+#define __ASM_ARCH_MX6_MX6Q_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS (1 << 16)
+#define PAD_CTL_PUS_100K_DOWN (0 << 14)
+#define PAD_CTL_PUS_47K_UP (1 << 14)
+#define PAD_CTL_PUS_100K_UP (2 << 14)
+#define PAD_CTL_PUS_22K_UP (3 << 14)
+
+#define PAD_CTL_PUE (1 << 13)
+#define PAD_CTL_PKE (1 << 12)
+#define PAD_CTL_ODE (1 << 11)
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
+enum {
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
+ MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0),
+ MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0),
+ MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0),
+ MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0),
+ MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0),
+ MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0),
+ MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0),
+ MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0),
+ MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
+ MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
+ MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
+ MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
+ MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
+ MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
+ MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0),
+ MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0),
+ MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0),
+ MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0),
+ MX6_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0),
+ MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0),
+ MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0),
+ MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0),
+ MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0),
+ MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0),
+ MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0),
+ MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0),
+ MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0),
+ MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0),
+ MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0),
+ MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0),
+ MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0),
+ MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0),
+ MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0),
+ MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
+ MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0),
+ MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0),
+ MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0),
+ MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0),
+ MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0),
+ MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0),
+ MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0),
+ MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0),
+ MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0),
+ MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0),
+ MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0),
+ MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0),
+ MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
+ MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
+ MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0),
+ MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
+ MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
+ MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0),
+ MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
+ MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
+ MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
+ MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
+ MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0),
+ MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0),
+ MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0),
+ MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0),
+ MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0),
+ MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0),
+ MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0),
+ MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0),
+ MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0),
+ MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0),
+ MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0),
+ MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0),
+ MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0),
+ MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0),
+ MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0),
+ MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0),
+ MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0),
+ MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0),
+ MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0),
+ MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0),
+ MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0),
+ MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0),
+ MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0),
+ MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0),
+ MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0),
+ MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0),
+ MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0),
+ MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
+ MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
+ MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
+ MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
+ MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
+ MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
+ MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
+ MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
+ MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
+ MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
+ MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
+ MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
+ MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
+ MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
+ MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
+ MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
+ MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0),
+ MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
+ MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
+ MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0),
+ MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
+ MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
+ MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
+ MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
+ MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
+ MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
+ MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
+ MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
+ MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
+ MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
+ MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0),
+ MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0),
+ MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0),
+ MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0),
+ MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0),
+ MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
+ MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0),
+ MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0),
+ MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0),
+ MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0),
+ MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0),
+ MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0),
+ MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0),
+ MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0),
+ MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0),
+ MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0),
+ MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0),
+ MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0),
+ MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0),
+ MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
+ MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
+ MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0),
+ MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
+ MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
+ MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0),
+ MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0),
+ MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
+ MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
+ MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0),
+ MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
+ MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
+ MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0),
+ MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0),
+ MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0),
+ MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0),
+ MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0),
+ MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0),
+ MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0),
+ MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0),
+ MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0),
+ MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0),
+ MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0),
+ MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0),
+ MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0),
+ MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0),
+ MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0),
+ MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
+ MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
+ MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0),
+ MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
+ MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
+ MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0),
+ MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0),
+ MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0),
+ MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
+ MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
+ MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
+ MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0),
+ MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0),
+ MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0),
+ MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0),
+ MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0),
+ MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0),
+ MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0),
+ MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0),
+ MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0),
+ MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
+ MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
+ MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0),
+ MX6_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0),
+ MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
+ MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0),
+ MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
+ MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
+ MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
+ MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
+ MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0),
+ MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0),
+ MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0),
+ MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0),
+ MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0),
+ MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0),
+ MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0),
+ MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0),
+ MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0),
+ MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0),
+ MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0),
+ MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0),
+ MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0),
+ MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0),
+ MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0),
+ MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0),
+ MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0),
+ MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0),
+ MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0),
+ MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0),
+ MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0),
+ MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0),
+ MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0),
+ MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0),
+ MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
+ MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
+ MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
+ MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
+ MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
+ MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
+ MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
+ MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
+ MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0),
+ MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0),
+ MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0),
+ MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0),
+ MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
+ MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
+ MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
+ MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
+ MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
+ MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0),
+ MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0),
+ MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
+ MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0),
+ MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0),
+ MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
+ MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
+ MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0),
+ MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0),
+ MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
+ MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
+ MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
+ MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0),
+ MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0),
+ MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
+ MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0),
+ MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
+ MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0),
+ MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0),
+ MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0),
+ MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0),
+ MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0),
+ MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0),
+ MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0),
+ MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0),
+ MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0),
+ MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0),
+ MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0),
+ MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
+};
+
+#endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
deleted file mode 100644
index 3ade8dc433..0000000000
--- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h
+++ /dev/null
@@ -1,1671 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Auto Generate file, please don't edit it
- *
- */
-
-#ifndef __ASM_ARCH_MX6_MX6X_PINS_H__
-#define __ASM_ARCH_MX6_MX6X_PINS_H__
-
-#include <asm/imx-common/iomux-v3.h>
-
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-
-enum {
- MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
- MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0),
- MX6Q_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0),
- MX6Q_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0),
- MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0),
- MX6Q_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0),
- MX6Q_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0),
- MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0),
- MX6Q_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0),
- MX6Q_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
- MX6Q_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
- MX6Q_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
- MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
- MX6Q_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
- MX6Q_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
- MX6Q_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0),
- MX6Q_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0),
- MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0),
- MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0),
- MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0),
- MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0),
- MX6Q_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0),
- MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0),
- MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0),
- MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0),
- MX6Q_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0),
- MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0),
- MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0),
- MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0),
- MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0),
- MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0),
- MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0),
- MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0),
- MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0),
- MX6Q_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
- MX6Q_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0),
- MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0),
- MX6Q_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0),
- MX6Q_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0),
- MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0),
- MX6Q_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0),
- MX6Q_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0),
- MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0),
- MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0),
- MX6Q_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0),
- MX6Q_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0),
- MX6Q_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0),
- MX6Q_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0),
- MX6Q_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
- MX6Q_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
- MX6Q_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0),
- MX6Q_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
- MX6Q_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
- MX6Q_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
- MX6Q_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
- MX6Q_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0),
- MX6Q_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0),
- MX6Q_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0),
- MX6Q_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0),
- MX6Q_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0),
- MX6Q_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0),
- MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0),
- MX6Q_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0),
- MX6Q_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0),
- MX6Q_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0),
- MX6Q_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0),
- MX6Q_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0),
- MX6Q_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0),
- MX6Q_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0),
- MX6Q_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0),
- MX6Q_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0),
- MX6Q_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0),
- MX6Q_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0),
- MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0),
- MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0),
- MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0),
- MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0),
- MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0),
- MX6Q_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0),
- MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0),
- MX6Q_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0),
- MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0),
- MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
- MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
- MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
- MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
- MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
- MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
- MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
- MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
- MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
- MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
- MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
- MX6Q_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
- MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
- MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
- MX6Q_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0),
- MX6Q_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0),
- MX6Q_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
- MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
- MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
- MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
- MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
- MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
- MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
- MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
- MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
- MX6Q_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
- MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0),
- MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0),
- MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0),
- MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
- MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0),
- MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0),
- MX6Q_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0),
- MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0),
- MX6Q_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0),
- MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0),
- MX6Q_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0),
- MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0),
- MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0),
- MX6Q_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0),
- MX6Q_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0),
- MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0),
- MX6Q_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0),
- MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
- MX6Q_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
- MX6Q_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0),
- MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
- MX6Q_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
- MX6Q_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0),
- MX6Q_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0),
- MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
- MX6Q_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
- MX6Q_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0),
- MX6Q_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
- MX6Q_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
- MX6Q_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0),
- MX6Q_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0),
- MX6Q_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0),
- MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0),
- MX6Q_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0),
- MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0),
- MX6Q_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0),
- MX6Q_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0),
- MX6Q_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0),
- MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0),
- MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0),
- MX6Q_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0),
- MX6Q_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0),
- MX6Q_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0),
- MX6Q_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0),
- MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
- MX6Q_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
- MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0),
- MX6Q_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
- MX6Q_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
- MX6Q_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0),
- MX6Q_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0),
- MX6Q_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0),
- MX6Q_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
- MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
- MX6Q_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
- MX6Q_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0),
- MX6Q_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0),
- MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0),
- MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0),
- MX6Q_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0),
- MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0),
- MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0),
- MX6Q_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0),
- MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0),
- MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
- MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
- MX6Q_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0),
- MX6Q_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0),
- MX6Q_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
- MX6Q_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0),
- MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
- MX6Q_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
- MX6Q_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
- MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
- MX6Q_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0),
- MX6Q_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0),
- MX6Q_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0),
- MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0),
- MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0),
- MX6Q_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0),
- MX6Q_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0),
- MX6Q_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0),
- MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0),
- MX6Q_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0),
- MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0),
- MX6Q_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0),
- MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0),
- MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0),
- MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0),
- MX6Q_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0),
- MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0),
- MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0),
- MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0),
- MX6Q_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0),
- MX6Q_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0),
- MX6Q_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0),
- MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0),
- MX6Q_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0),
- MX6Q_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
- MX6Q_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
- MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
- MX6Q_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
- MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
- MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
- MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
- MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
- MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0),
- MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0),
- MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0),
- MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0),
- MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
- MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
- MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
- MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
- MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
- MX6Q_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0),
- MX6Q_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0),
- MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
- MX6Q_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0),
- MX6Q_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0),
- MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
- MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
- MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0),
- MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0),
- MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
- MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
- MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
- MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0),
- MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0),
- MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
- MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0),
- MX6Q_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
- MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0),
- MX6Q_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0),
- MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0),
- MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0),
- MX6Q_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0),
- MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0),
- MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0),
- MX6Q_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0),
- MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0),
- MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0),
- MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0),
- MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
-};
-
-#endif /* __ASM_ARCH_MX6_MX6X_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
index 02a413f2bc..9dccb3fef5 100644
--- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
+++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
@@ -24,542 +24,553 @@
/*
* Hdmi controller registers
*/
-
-/* Identification Registers */
-#define HDMI_DESIGN_ID 0x0000
-#define HDMI_REVISION_ID 0x0001
-#define HDMI_PRODUCT_ID0 0x0002
-#define HDMI_PRODUCT_ID1 0x0003
-#define HDMI_CONFIG0_ID 0x0004
-#define HDMI_CONFIG1_ID 0x0005
-#define HDMI_CONFIG2_ID 0x0006
-#define HDMI_CONFIG3_ID 0x0007
-
-/* Interrupt Registers */
-#define HDMI_IH_FC_STAT0 0x0100
-#define HDMI_IH_FC_STAT1 0x0101
-#define HDMI_IH_FC_STAT2 0x0102
-#define HDMI_IH_AS_STAT0 0x0103
-#define HDMI_IH_PHY_STAT0 0x0104
-#define HDMI_IH_I2CM_STAT0 0x0105
-#define HDMI_IH_CEC_STAT0 0x0106
-#define HDMI_IH_VP_STAT0 0x0107
-#define HDMI_IH_I2CMPHY_STAT0 0x0108
-#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
-
-#define HDMI_IH_MUTE_FC_STAT0 0x0180
-#define HDMI_IH_MUTE_FC_STAT1 0x0181
-#define HDMI_IH_MUTE_FC_STAT2 0x0182
-#define HDMI_IH_MUTE_AS_STAT0 0x0183
-#define HDMI_IH_MUTE_PHY_STAT0 0x0184
-#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
-#define HDMI_IH_MUTE_CEC_STAT0 0x0186
-#define HDMI_IH_MUTE_VP_STAT0 0x0187
-#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
-#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
-#define HDMI_IH_MUTE 0x01FF
-
-/* Video Sample Registers */
-#define HDMI_TX_INVID0 0x0200
-#define HDMI_TX_INSTUFFING 0x0201
-#define HDMI_TX_GYDATA0 0x0202
-#define HDMI_TX_GYDATA1 0x0203
-#define HDMI_TX_RCRDATA0 0x0204
-#define HDMI_TX_RCRDATA1 0x0205
-#define HDMI_TX_BCBDATA0 0x0206
-#define HDMI_TX_BCBDATA1 0x0207
-
-/* Video Packetizer Registers */
-#define HDMI_VP_STATUS 0x0800
-#define HDMI_VP_PR_CD 0x0801
-#define HDMI_VP_STUFF 0x0802
-#define HDMI_VP_REMAP 0x0803
-#define HDMI_VP_CONF 0x0804
-#define HDMI_VP_STAT 0x0805
-#define HDMI_VP_INT 0x0806
-#define HDMI_VP_MASK 0x0807
-#define HDMI_VP_POL 0x0808
-
-/* Frame Composer Registers */
-#define HDMI_FC_INVIDCONF 0x1000
-#define HDMI_FC_INHACTV0 0x1001
-#define HDMI_FC_INHACTV1 0x1002
-#define HDMI_FC_INHBLANK0 0x1003
-#define HDMI_FC_INHBLANK1 0x1004
-#define HDMI_FC_INVACTV0 0x1005
-#define HDMI_FC_INVACTV1 0x1006
-#define HDMI_FC_INVBLANK 0x1007
-#define HDMI_FC_HSYNCINDELAY0 0x1008
-#define HDMI_FC_HSYNCINDELAY1 0x1009
-#define HDMI_FC_HSYNCINWIDTH0 0x100A
-#define HDMI_FC_HSYNCINWIDTH1 0x100B
-#define HDMI_FC_VSYNCINDELAY 0x100C
-#define HDMI_FC_VSYNCINWIDTH 0x100D
-#define HDMI_FC_INFREQ0 0x100E
-#define HDMI_FC_INFREQ1 0x100F
-#define HDMI_FC_INFREQ2 0x1010
-#define HDMI_FC_CTRLDUR 0x1011
-#define HDMI_FC_EXCTRLDUR 0x1012
-#define HDMI_FC_EXCTRLSPAC 0x1013
-#define HDMI_FC_CH0PREAM 0x1014
-#define HDMI_FC_CH1PREAM 0x1015
-#define HDMI_FC_CH2PREAM 0x1016
-#define HDMI_FC_AVICONF3 0x1017
-#define HDMI_FC_GCP 0x1018
-#define HDMI_FC_AVICONF0 0x1019
-#define HDMI_FC_AVICONF1 0x101A
-#define HDMI_FC_AVICONF2 0x101B
-#define HDMI_FC_AVIVID 0x101C
-#define HDMI_FC_AVIETB0 0x101D
-#define HDMI_FC_AVIETB1 0x101E
-#define HDMI_FC_AVISBB0 0x101F
-#define HDMI_FC_AVISBB1 0x1020
-#define HDMI_FC_AVIELB0 0x1021
-#define HDMI_FC_AVIELB1 0x1022
-#define HDMI_FC_AVISRB0 0x1023
-#define HDMI_FC_AVISRB1 0x1024
-#define HDMI_FC_AUDICONF0 0x1025
-#define HDMI_FC_AUDICONF1 0x1026
-#define HDMI_FC_AUDICONF2 0x1027
-#define HDMI_FC_AUDICONF3 0x1028
-#define HDMI_FC_VSDIEEEID0 0x1029
-#define HDMI_FC_VSDSIZE 0x102A
-#define HDMI_FC_VSDIEEEID1 0x1030
-#define HDMI_FC_VSDIEEEID2 0x1031
-#define HDMI_FC_VSDPAYLOAD0 0x1032
-#define HDMI_FC_VSDPAYLOAD1 0x1033
-#define HDMI_FC_VSDPAYLOAD2 0x1034
-#define HDMI_FC_VSDPAYLOAD3 0x1035
-#define HDMI_FC_VSDPAYLOAD4 0x1036
-#define HDMI_FC_VSDPAYLOAD5 0x1037
-#define HDMI_FC_VSDPAYLOAD6 0x1038
-#define HDMI_FC_VSDPAYLOAD7 0x1039
-#define HDMI_FC_VSDPAYLOAD8 0x103A
-#define HDMI_FC_VSDPAYLOAD9 0x103B
-#define HDMI_FC_VSDPAYLOAD10 0x103C
-#define HDMI_FC_VSDPAYLOAD11 0x103D
-#define HDMI_FC_VSDPAYLOAD12 0x103E
-#define HDMI_FC_VSDPAYLOAD13 0x103F
-#define HDMI_FC_VSDPAYLOAD14 0x1040
-#define HDMI_FC_VSDPAYLOAD15 0x1041
-#define HDMI_FC_VSDPAYLOAD16 0x1042
-#define HDMI_FC_VSDPAYLOAD17 0x1043
-#define HDMI_FC_VSDPAYLOAD18 0x1044
-#define HDMI_FC_VSDPAYLOAD19 0x1045
-#define HDMI_FC_VSDPAYLOAD20 0x1046
-#define HDMI_FC_VSDPAYLOAD21 0x1047
-#define HDMI_FC_VSDPAYLOAD22 0x1048
-#define HDMI_FC_VSDPAYLOAD23 0x1049
-#define HDMI_FC_SPDVENDORNAME0 0x104A
-#define HDMI_FC_SPDVENDORNAME1 0x104B
-#define HDMI_FC_SPDVENDORNAME2 0x104C
-#define HDMI_FC_SPDVENDORNAME3 0x104D
-#define HDMI_FC_SPDVENDORNAME4 0x104E
-#define HDMI_FC_SPDVENDORNAME5 0x104F
-#define HDMI_FC_SPDVENDORNAME6 0x1050
-#define HDMI_FC_SPDVENDORNAME7 0x1051
-#define HDMI_FC_SDPPRODUCTNAME0 0x1052
-#define HDMI_FC_SDPPRODUCTNAME1 0x1053
-#define HDMI_FC_SDPPRODUCTNAME2 0x1054
-#define HDMI_FC_SDPPRODUCTNAME3 0x1055
-#define HDMI_FC_SDPPRODUCTNAME4 0x1056
-#define HDMI_FC_SDPPRODUCTNAME5 0x1057
-#define HDMI_FC_SDPPRODUCTNAME6 0x1058
-#define HDMI_FC_SDPPRODUCTNAME7 0x1059
-#define HDMI_FC_SDPPRODUCTNAME8 0x105A
-#define HDMI_FC_SDPPRODUCTNAME9 0x105B
-#define HDMI_FC_SDPPRODUCTNAME10 0x105C
-#define HDMI_FC_SDPPRODUCTNAME11 0x105D
-#define HDMI_FC_SDPPRODUCTNAME12 0x105E
-#define HDMI_FC_SDPPRODUCTNAME13 0x105F
-#define HDMI_FC_SDPPRODUCTNAME14 0x1060
-#define HDMI_FC_SPDPRODUCTNAME15 0x1061
-#define HDMI_FC_SPDDEVICEINF 0x1062
-#define HDMI_FC_AUDSCONF 0x1063
-#define HDMI_FC_AUDSSTAT 0x1064
-#define HDMI_FC_DATACH0FILL 0x1070
-#define HDMI_FC_DATACH1FILL 0x1071
-#define HDMI_FC_DATACH2FILL 0x1072
-#define HDMI_FC_CTRLQHIGH 0x1073
-#define HDMI_FC_CTRLQLOW 0x1074
-#define HDMI_FC_ACP0 0x1075
-#define HDMI_FC_ACP28 0x1076
-#define HDMI_FC_ACP27 0x1077
-#define HDMI_FC_ACP26 0x1078
-#define HDMI_FC_ACP25 0x1079
-#define HDMI_FC_ACP24 0x107A
-#define HDMI_FC_ACP23 0x107B
-#define HDMI_FC_ACP22 0x107C
-#define HDMI_FC_ACP21 0x107D
-#define HDMI_FC_ACP20 0x107E
-#define HDMI_FC_ACP19 0x107F
-#define HDMI_FC_ACP18 0x1080
-#define HDMI_FC_ACP17 0x1081
-#define HDMI_FC_ACP16 0x1082
-#define HDMI_FC_ACP15 0x1083
-#define HDMI_FC_ACP14 0x1084
-#define HDMI_FC_ACP13 0x1085
-#define HDMI_FC_ACP12 0x1086
-#define HDMI_FC_ACP11 0x1087
-#define HDMI_FC_ACP10 0x1088
-#define HDMI_FC_ACP9 0x1089
-#define HDMI_FC_ACP8 0x108A
-#define HDMI_FC_ACP7 0x108B
-#define HDMI_FC_ACP6 0x108C
-#define HDMI_FC_ACP5 0x108D
-#define HDMI_FC_ACP4 0x108E
-#define HDMI_FC_ACP3 0x108F
-#define HDMI_FC_ACP2 0x1090
-#define HDMI_FC_ACP1 0x1091
-#define HDMI_FC_ISCR1_0 0x1092
-#define HDMI_FC_ISCR1_16 0x1093
-#define HDMI_FC_ISCR1_15 0x1094
-#define HDMI_FC_ISCR1_14 0x1095
-#define HDMI_FC_ISCR1_13 0x1096
-#define HDMI_FC_ISCR1_12 0x1097
-#define HDMI_FC_ISCR1_11 0x1098
-#define HDMI_FC_ISCR1_10 0x1099
-#define HDMI_FC_ISCR1_9 0x109A
-#define HDMI_FC_ISCR1_8 0x109B
-#define HDMI_FC_ISCR1_7 0x109C
-#define HDMI_FC_ISCR1_6 0x109D
-#define HDMI_FC_ISCR1_5 0x109E
-#define HDMI_FC_ISCR1_4 0x109F
-#define HDMI_FC_ISCR1_3 0x10A0
-#define HDMI_FC_ISCR1_2 0x10A1
-#define HDMI_FC_ISCR1_1 0x10A2
-#define HDMI_FC_ISCR2_15 0x10A3
-#define HDMI_FC_ISCR2_14 0x10A4
-#define HDMI_FC_ISCR2_13 0x10A5
-#define HDMI_FC_ISCR2_12 0x10A6
-#define HDMI_FC_ISCR2_11 0x10A7
-#define HDMI_FC_ISCR2_10 0x10A8
-#define HDMI_FC_ISCR2_9 0x10A9
-#define HDMI_FC_ISCR2_8 0x10AA
-#define HDMI_FC_ISCR2_7 0x10AB
-#define HDMI_FC_ISCR2_6 0x10AC
-#define HDMI_FC_ISCR2_5 0x10AD
-#define HDMI_FC_ISCR2_4 0x10AE
-#define HDMI_FC_ISCR2_3 0x10AF
-#define HDMI_FC_ISCR2_2 0x10B0
-#define HDMI_FC_ISCR2_1 0x10B1
-#define HDMI_FC_ISCR2_0 0x10B2
-#define HDMI_FC_DATAUTO0 0x10B3
-#define HDMI_FC_DATAUTO1 0x10B4
-#define HDMI_FC_DATAUTO2 0x10B5
-#define HDMI_FC_DATMAN 0x10B6
-#define HDMI_FC_DATAUTO3 0x10B7
-#define HDMI_FC_RDRB0 0x10B8
-#define HDMI_FC_RDRB1 0x10B9
-#define HDMI_FC_RDRB2 0x10BA
-#define HDMI_FC_RDRB3 0x10BB
-#define HDMI_FC_RDRB4 0x10BC
-#define HDMI_FC_RDRB5 0x10BD
-#define HDMI_FC_RDRB6 0x10BE
-#define HDMI_FC_RDRB7 0x10BF
-#define HDMI_FC_STAT0 0x10D0
-#define HDMI_FC_INT0 0x10D1
-#define HDMI_FC_MASK0 0x10D2
-#define HDMI_FC_POL0 0x10D3
-#define HDMI_FC_STAT1 0x10D4
-#define HDMI_FC_INT1 0x10D5
-#define HDMI_FC_MASK1 0x10D6
-#define HDMI_FC_POL1 0x10D7
-#define HDMI_FC_STAT2 0x10D8
-#define HDMI_FC_INT2 0x10D9
-#define HDMI_FC_MASK2 0x10DA
-#define HDMI_FC_POL2 0x10DB
-#define HDMI_FC_PRCONF 0x10E0
-
-#define HDMI_FC_GMD_STAT 0x1100
-#define HDMI_FC_GMD_EN 0x1101
-#define HDMI_FC_GMD_UP 0x1102
-#define HDMI_FC_GMD_CONF 0x1103
-#define HDMI_FC_GMD_HB 0x1104
-#define HDMI_FC_GMD_PB0 0x1105
-#define HDMI_FC_GMD_PB1 0x1106
-#define HDMI_FC_GMD_PB2 0x1107
-#define HDMI_FC_GMD_PB3 0x1108
-#define HDMI_FC_GMD_PB4 0x1109
-#define HDMI_FC_GMD_PB5 0x110A
-#define HDMI_FC_GMD_PB6 0x110B
-#define HDMI_FC_GMD_PB7 0x110C
-#define HDMI_FC_GMD_PB8 0x110D
-#define HDMI_FC_GMD_PB9 0x110E
-#define HDMI_FC_GMD_PB10 0x110F
-#define HDMI_FC_GMD_PB11 0x1110
-#define HDMI_FC_GMD_PB12 0x1111
-#define HDMI_FC_GMD_PB13 0x1112
-#define HDMI_FC_GMD_PB14 0x1113
-#define HDMI_FC_GMD_PB15 0x1114
-#define HDMI_FC_GMD_PB16 0x1115
-#define HDMI_FC_GMD_PB17 0x1116
-#define HDMI_FC_GMD_PB18 0x1117
-#define HDMI_FC_GMD_PB19 0x1118
-#define HDMI_FC_GMD_PB20 0x1119
-#define HDMI_FC_GMD_PB21 0x111A
-#define HDMI_FC_GMD_PB22 0x111B
-#define HDMI_FC_GMD_PB23 0x111C
-#define HDMI_FC_GMD_PB24 0x111D
-#define HDMI_FC_GMD_PB25 0x111E
-#define HDMI_FC_GMD_PB26 0x111F
-#define HDMI_FC_GMD_PB27 0x1120
-
-#define HDMI_FC_DBGFORCE 0x1200
-#define HDMI_FC_DBGAUD0CH0 0x1201
-#define HDMI_FC_DBGAUD1CH0 0x1202
-#define HDMI_FC_DBGAUD2CH0 0x1203
-#define HDMI_FC_DBGAUD0CH1 0x1204
-#define HDMI_FC_DBGAUD1CH1 0x1205
-#define HDMI_FC_DBGAUD2CH1 0x1206
-#define HDMI_FC_DBGAUD0CH2 0x1207
-#define HDMI_FC_DBGAUD1CH2 0x1208
-#define HDMI_FC_DBGAUD2CH2 0x1209
-#define HDMI_FC_DBGAUD0CH3 0x120A
-#define HDMI_FC_DBGAUD1CH3 0x120B
-#define HDMI_FC_DBGAUD2CH3 0x120C
-#define HDMI_FC_DBGAUD0CH4 0x120D
-#define HDMI_FC_DBGAUD1CH4 0x120E
-#define HDMI_FC_DBGAUD2CH4 0x120F
-#define HDMI_FC_DBGAUD0CH5 0x1210
-#define HDMI_FC_DBGAUD1CH5 0x1211
-#define HDMI_FC_DBGAUD2CH5 0x1212
-#define HDMI_FC_DBGAUD0CH6 0x1213
-#define HDMI_FC_DBGAUD1CH6 0x1214
-#define HDMI_FC_DBGAUD2CH6 0x1215
-#define HDMI_FC_DBGAUD0CH7 0x1216
-#define HDMI_FC_DBGAUD1CH7 0x1217
-#define HDMI_FC_DBGAUD2CH7 0x1218
-#define HDMI_FC_DBGTMDS0 0x1219
-#define HDMI_FC_DBGTMDS1 0x121A
-#define HDMI_FC_DBGTMDS2 0x121B
-
-/* HDMI Source PHY Registers */
-#define HDMI_PHY_CONF0 0x3000
-#define HDMI_PHY_TST0 0x3001
-#define HDMI_PHY_TST1 0x3002
-#define HDMI_PHY_TST2 0x3003
-#define HDMI_PHY_STAT0 0x3004
-#define HDMI_PHY_INT0 0x3005
-#define HDMI_PHY_MASK0 0x3006
-#define HDMI_PHY_POL0 0x3007
-
-/* HDMI Master PHY Registers */
-#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
-#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
-#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
-#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
-#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
-#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
-#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
-#define HDMI_PHY_I2CM_INT_ADDR 0x3027
-#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
-#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
-#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
-#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
-#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
-#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
-#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
-#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
-#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
-#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
-#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
-
-/* Audio Sampler Registers */
-#define HDMI_AUD_CONF0 0x3100
-#define HDMI_AUD_CONF1 0x3101
-#define HDMI_AUD_INT 0x3102
-#define HDMI_AUD_CONF2 0x3103
-#define HDMI_AUD_N1 0x3200
-#define HDMI_AUD_N2 0x3201
-#define HDMI_AUD_N3 0x3202
-#define HDMI_AUD_CTS1 0x3203
-#define HDMI_AUD_CTS2 0x3204
-#define HDMI_AUD_CTS3 0x3205
-#define HDMI_AUD_INPUTCLKFS 0x3206
-#define HDMI_AUD_SPDIFINT 0x3302
-#define HDMI_AUD_CONF0_HBR 0x3400
-#define HDMI_AUD_HBR_STATUS 0x3401
-#define HDMI_AUD_HBR_INT 0x3402
-#define HDMI_AUD_HBR_POL 0x3403
-#define HDMI_AUD_HBR_MASK 0x3404
-
-/* Generic Parallel Audio Interface Registers */
-/* Not used as GPAUD interface is not enabled in hw */
-#define HDMI_GP_CONF0 0x3500
-#define HDMI_GP_CONF1 0x3501
-#define HDMI_GP_CONF2 0x3502
-#define HDMI_GP_STAT 0x3503
-#define HDMI_GP_INT 0x3504
-#define HDMI_GP_MASK 0x3505
-#define HDMI_GP_POL 0x3506
-
-/* Audio DMA Registers */
-#define HDMI_AHB_DMA_CONF0 0x3600
-#define HDMI_AHB_DMA_START 0x3601
-#define HDMI_AHB_DMA_STOP 0x3602
-#define HDMI_AHB_DMA_THRSLD 0x3603
-#define HDMI_AHB_DMA_STRADDR0 0x3604
-#define HDMI_AHB_DMA_STRADDR1 0x3605
-#define HDMI_AHB_DMA_STRADDR2 0x3606
-#define HDMI_AHB_DMA_STRADDR3 0x3607
-#define HDMI_AHB_DMA_STPADDR0 0x3608
-#define HDMI_AHB_DMA_STPADDR1 0x3609
-#define HDMI_AHB_DMA_STPADDR2 0x360a
-#define HDMI_AHB_DMA_STPADDR3 0x360b
-#define HDMI_AHB_DMA_BSTADDR0 0x360c
-#define HDMI_AHB_DMA_BSTADDR1 0x360d
-#define HDMI_AHB_DMA_BSTADDR2 0x360e
-#define HDMI_AHB_DMA_BSTADDR3 0x360f
-#define HDMI_AHB_DMA_MBLENGTH0 0x3610
-#define HDMI_AHB_DMA_MBLENGTH1 0x3611
-#define HDMI_AHB_DMA_STAT 0x3612
-#define HDMI_AHB_DMA_INT 0x3613
-#define HDMI_AHB_DMA_MASK 0x3614
-#define HDMI_AHB_DMA_POL 0x3615
-#define HDMI_AHB_DMA_CONF1 0x3616
-#define HDMI_AHB_DMA_BUFFSTAT 0x3617
-#define HDMI_AHB_DMA_BUFFINT 0x3618
-#define HDMI_AHB_DMA_BUFFMASK 0x3619
-#define HDMI_AHB_DMA_BUFFPOL 0x361a
-
-/* Main Controller Registers */
-#define HDMI_MC_SFRDIV 0x4000
-#define HDMI_MC_CLKDIS 0x4001
-#define HDMI_MC_SWRSTZ 0x4002
-#define HDMI_MC_OPCTRL 0x4003
-#define HDMI_MC_FLOWCTRL 0x4004
-#define HDMI_MC_PHYRSTZ 0x4005
-#define HDMI_MC_LOCKONCLOCK 0x4006
-#define HDMI_MC_HEACPHY_RST 0x4007
-
-/* Color Space Converter Registers */
-#define HDMI_CSC_CFG 0x4100
-#define HDMI_CSC_SCALE 0x4101
-#define HDMI_CSC_COEF_A1_MSB 0x4102
-#define HDMI_CSC_COEF_A1_LSB 0x4103
-#define HDMI_CSC_COEF_A2_MSB 0x4104
-#define HDMI_CSC_COEF_A2_LSB 0x4105
-#define HDMI_CSC_COEF_A3_MSB 0x4106
-#define HDMI_CSC_COEF_A3_LSB 0x4107
-#define HDMI_CSC_COEF_A4_MSB 0x4108
-#define HDMI_CSC_COEF_A4_LSB 0x4109
-#define HDMI_CSC_COEF_B1_MSB 0x410A
-#define HDMI_CSC_COEF_B1_LSB 0x410B
-#define HDMI_CSC_COEF_B2_MSB 0x410C
-#define HDMI_CSC_COEF_B2_LSB 0x410D
-#define HDMI_CSC_COEF_B3_MSB 0x410E
-#define HDMI_CSC_COEF_B3_LSB 0x410F
-#define HDMI_CSC_COEF_B4_MSB 0x4110
-#define HDMI_CSC_COEF_B4_LSB 0x4111
-#define HDMI_CSC_COEF_C1_MSB 0x4112
-#define HDMI_CSC_COEF_C1_LSB 0x4113
-#define HDMI_CSC_COEF_C2_MSB 0x4114
-#define HDMI_CSC_COEF_C2_LSB 0x4115
-#define HDMI_CSC_COEF_C3_MSB 0x4116
-#define HDMI_CSC_COEF_C3_LSB 0x4117
-#define HDMI_CSC_COEF_C4_MSB 0x4118
-#define HDMI_CSC_COEF_C4_LSB 0x4119
-
-/* HDCP Encryption Engine Registers */
-#define HDMI_A_HDCPCFG0 0x5000
-#define HDMI_A_HDCPCFG1 0x5001
-#define HDMI_A_HDCPOBS0 0x5002
-#define HDMI_A_HDCPOBS1 0x5003
-#define HDMI_A_HDCPOBS2 0x5004
-#define HDMI_A_HDCPOBS3 0x5005
-#define HDMI_A_APIINTCLR 0x5006
-#define HDMI_A_APIINTSTAT 0x5007
-#define HDMI_A_APIINTMSK 0x5008
-#define HDMI_A_VIDPOLCFG 0x5009
-#define HDMI_A_OESSWCFG 0x500A
-#define HDMI_A_TIMER1SETUP0 0x500B
-#define HDMI_A_TIMER1SETUP1 0x500C
-#define HDMI_A_TIMER2SETUP0 0x500D
-#define HDMI_A_TIMER2SETUP1 0x500E
-#define HDMI_A_100MSCFG 0x500F
-#define HDMI_A_2SCFG0 0x5010
-#define HDMI_A_2SCFG1 0x5011
-#define HDMI_A_5SCFG0 0x5012
-#define HDMI_A_5SCFG1 0x5013
-#define HDMI_A_SRMVERLSB 0x5014
-#define HDMI_A_SRMVERMSB 0x5015
-#define HDMI_A_SRMCTRL 0x5016
-#define HDMI_A_SFRSETUP 0x5017
-#define HDMI_A_I2CHSETUP 0x5018
-#define HDMI_A_INTSETUP 0x5019
-#define HDMI_A_PRESETUP 0x501A
-#define HDMI_A_SRM_BASE 0x5020
-
-/* CEC Engine Registers */
-#define HDMI_CEC_CTRL 0x7D00
-#define HDMI_CEC_STAT 0x7D01
-#define HDMI_CEC_MASK 0x7D02
-#define HDMI_CEC_POLARITY 0x7D03
-#define HDMI_CEC_INT 0x7D04
-#define HDMI_CEC_ADDR_L 0x7D05
-#define HDMI_CEC_ADDR_H 0x7D06
-#define HDMI_CEC_TX_CNT 0x7D07
-#define HDMI_CEC_RX_CNT 0x7D08
-#define HDMI_CEC_TX_DATA0 0x7D10
-#define HDMI_CEC_TX_DATA1 0x7D11
-#define HDMI_CEC_TX_DATA2 0x7D12
-#define HDMI_CEC_TX_DATA3 0x7D13
-#define HDMI_CEC_TX_DATA4 0x7D14
-#define HDMI_CEC_TX_DATA5 0x7D15
-#define HDMI_CEC_TX_DATA6 0x7D16
-#define HDMI_CEC_TX_DATA7 0x7D17
-#define HDMI_CEC_TX_DATA8 0x7D18
-#define HDMI_CEC_TX_DATA9 0x7D19
-#define HDMI_CEC_TX_DATA10 0x7D1a
-#define HDMI_CEC_TX_DATA11 0x7D1b
-#define HDMI_CEC_TX_DATA12 0x7D1c
-#define HDMI_CEC_TX_DATA13 0x7D1d
-#define HDMI_CEC_TX_DATA14 0x7D1e
-#define HDMI_CEC_TX_DATA15 0x7D1f
-#define HDMI_CEC_RX_DATA0 0x7D20
-#define HDMI_CEC_RX_DATA1 0x7D21
-#define HDMI_CEC_RX_DATA2 0x7D22
-#define HDMI_CEC_RX_DATA3 0x7D23
-#define HDMI_CEC_RX_DATA4 0x7D24
-#define HDMI_CEC_RX_DATA5 0x7D25
-#define HDMI_CEC_RX_DATA6 0x7D26
-#define HDMI_CEC_RX_DATA7 0x7D27
-#define HDMI_CEC_RX_DATA8 0x7D28
-#define HDMI_CEC_RX_DATA9 0x7D29
-#define HDMI_CEC_RX_DATA10 0x7D2a
-#define HDMI_CEC_RX_DATA11 0x7D2b
-#define HDMI_CEC_RX_DATA12 0x7D2c
-#define HDMI_CEC_RX_DATA13 0x7D2d
-#define HDMI_CEC_RX_DATA14 0x7D2e
-#define HDMI_CEC_RX_DATA15 0x7D2f
-#define HDMI_CEC_LOCK 0x7D30
-#define HDMI_CEC_WKUPCTRL 0x7D31
-
-/* I2C Master Registers (E-DDC) */
-#define HDMI_I2CM_SLAVE 0x7E00
-#define HDMI_I2CMESS 0x7E01
-#define HDMI_I2CM_DATAO 0x7E02
-#define HDMI_I2CM_DATAI 0x7E03
-#define HDMI_I2CM_OPERATION 0x7E04
-#define HDMI_I2CM_INT 0x7E05
-#define HDMI_I2CM_CTLINT 0x7E06
-#define HDMI_I2CM_DIV 0x7E07
-#define HDMI_I2CM_SEGADDR 0x7E08
-#define HDMI_I2CM_SOFTRSTZ 0x7E09
-#define HDMI_I2CM_SEGPTR 0x7E0A
-#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
-#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
-#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
-#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
-#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
-#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
-#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
-#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
-
-/* Random Number Generator Registers (RNG) */
-#define HDMI_RNG_BASE 0x8000
-
+struct hdmi_regs {
+ /*Identification Registers */
+ u8 design_id; /* 0x000 */
+ u8 revision_id; /* 0x001 */
+ u8 product_id0; /* 0x002 */
+ u8 product_id1; /* 0x003 */
+ u8 config0_id; /* 0x004 */
+ u8 config1_id; /* 0x005 */
+ u8 config2_id; /* 0x006 */
+ u8 config3_id; /* 0x007 */
+ u8 reserved1[0xf8];
+ /* Interrupt Registers */
+ u8 ih_fc_stat0; /* 0x100 */
+ u8 ih_fc_stat1; /* 0x101 */
+ u8 ih_fc_stat2; /* 0x102 */
+ u8 ih_as_stat0; /* 0x103 */
+ u8 ih_phy_stat0; /* 0x104 */
+ u8 ih_i2cm_stat0; /* 0x105 */
+ u8 ih_cec_stat0; /* 0x106 */
+ u8 ih_vp_stat0; /* 0x107 */
+ u8 ih_i2cmphy_stat0; /* 0x108 */
+ u8 ih_ahbdmaaud_stat0; /* 0x109 */
+ u8 reserved2[0x76];
+ u8 ih_mute_fc_stat0; /* 0x180 */
+ u8 ih_mute_fc_stat1; /* 0x181 */
+ u8 ih_mute_fc_stat2; /* 0x182 */
+ u8 ih_mute_as_stat0; /* 0x183 */
+ u8 ih_mute_phy_stat0; /* 0x184 */
+ u8 ih_mute_i2cm_stat0; /* 0x185 */
+ u8 ih_mute_cec_stat0; /* 0x186 */
+ u8 ih_mute_vp_stat0; /* 0x187 */
+ u8 ih_mute_i2cmphy_stat0; /* 0x188 */
+ u8 ih_mute_ahbdmaaud_stat0; /* 0x189 */
+ u8 reserved3[0x75];
+ u8 ih_mute; /* 0x1ff */
+ /* Video Sample Registers */
+ u8 tx_invid0; /* 0x200 */
+ u8 tx_instuffing; /* 0x201 */
+ u8 tx_gydata0; /* 0x202 */
+ u8 tx_gydata1; /* 0x203 */
+ u8 tx_rcrdata0; /* 0x204 */
+ u8 tx_rcrdata1; /* 0x205 */
+ u8 tx_bcbdata0; /* 0x206 */
+ u8 tx_bcbdata1; /* 0x207 */
+ u8 reserved4[0x5f8];
+ /* Video Packetizer Registers */
+ u8 vp_status; /* 0x800 */
+ u8 vp_pr_cd; /* 0x801 */
+ u8 vp_stuff; /* 0x802 */
+ u8 vp_remap; /* 0x803 */
+ u8 vp_conf; /* 0x804 */
+ u8 vp_stat; /* 0x805 */
+ u8 vp_int; /* 0x806 */
+ u8 vp_mask; /* 0x807 */
+ u8 vp_pol; /* 0x808 */
+ u8 reserved5[0x7f7];
+ /* Frame Composer Registers */
+ u8 fc_invidconf; /* 0x1000 */
+ u8 fc_inhactv0; /* 0x1001 */
+ u8 fc_inhactv1; /* 0x1002 */
+ u8 fc_inhblank0; /* 0x1003 */
+ u8 fc_inhblank1; /* 0x1004 */
+ u8 fc_invactv0; /* 0x1005 */
+ u8 fc_invactv1; /* 0x1006 */
+ u8 fc_invblank; /* 0x1007 */
+ u8 fc_hsyncindelay0; /* 0x1008 */
+ u8 fc_hsyncindelay1; /* 0x1009 */
+ u8 fc_hsyncinwidth0; /* 0x100a */
+ u8 fc_hsyncinwidth1; /* 0x100b */
+ u8 fc_vsyncindelay; /* 0x100c */
+ u8 fc_vsyncinwidth; /* 0x100d */
+ u8 fc_infreq0; /* 0x100e */
+ u8 fc_infreq1; /* 0x100f */
+ u8 fc_infreq2; /* 0x1010 */
+ u8 fc_ctrldur; /* 0x1011 */
+ u8 fc_exctrldur; /* 0x1012 */
+ u8 fc_exctrlspac; /* 0x1013 */
+ u8 fc_ch0pream; /* 0x1014 */
+ u8 fc_ch1pream; /* 0x1015 */
+ u8 fc_ch2pream; /* 0x1016 */
+ u8 fc_aviconf3; /* 0x1017 */
+ u8 fc_gcp; /* 0x1018 */
+ u8 fc_aviconf0; /* 0x1019 */
+ u8 fc_aviconf1; /* 0x101a */
+ u8 fc_aviconf2; /* 0x101b */
+ u8 fc_avivid; /* 0x101c */
+ u8 fc_avietb0; /* 0x101d */
+ u8 fc_avietb1; /* 0x101e */
+ u8 fc_avisbb0; /* 0x101f */
+ u8 fc_avisbb1; /* 0x1020 */
+ u8 fc_avielb0; /* 0x1021 */
+ u8 fc_avielb1; /* 0x1022 */
+ u8 fc_avisrb0; /* 0x1023 */
+ u8 fc_avisrb1; /* 0x1024 */
+ u8 fc_audiconf0; /* 0x1025 */
+ u8 fc_audiconf1; /* 0x1026 */
+ u8 fc_audiconf2; /* 0x1027 */
+ u8 fc_audiconf3; /* 0x1028 */
+ u8 fc_vsdieeeid0; /* 0x1029 */
+ u8 fc_vsdsize; /* 0x102a */
+ u8 reserved6[5];
+ u8 fc_vsdieeeid1; /* 0x1030 */
+ u8 fc_vsdieeeid2; /* 0x1031 */
+ u8 fc_vsdpayload0; /* 0x1032 */
+ u8 fc_vsdpayload1; /* 0x1033 */
+ u8 fc_vsdpayload2; /* 0x1034 */
+ u8 fc_vsdpayload3; /* 0x1035 */
+ u8 fc_vsdpayload4; /* 0x1036 */
+ u8 fc_vsdpayload5; /* 0x1037 */
+ u8 fc_vsdpayload6; /* 0x1038 */
+ u8 fc_vsdpayload7; /* 0x1039 */
+ u8 fc_vsdpayload8; /* 0x103a */
+ u8 fc_vsdpayload9; /* 0x103b */
+ u8 fc_vsdpayload10; /* 0x103c */
+ u8 fc_vsdpayload11; /* 0x103d */
+ u8 fc_vsdpayload12; /* 0x103e */
+ u8 fc_vsdpayload13; /* 0x103f */
+ u8 fc_vsdpayload14; /* 0x1040 */
+ u8 fc_vsdpayload15; /* 0x1041 */
+ u8 fc_vsdpayload16; /* 0x1042 */
+ u8 fc_vsdpayload17; /* 0x1043 */
+ u8 fc_vsdpayload18; /* 0x1044 */
+ u8 fc_vsdpayload19; /* 0x1045 */
+ u8 fc_vsdpayload20; /* 0x1046 */
+ u8 fc_vsdpayload21; /* 0x1047 */
+ u8 fc_vsdpayload22; /* 0x1048 */
+ u8 fc_vsdpayload23; /* 0x1049 */
+ u8 fc_spdvendorname0; /* 0x104a */
+ u8 fc_spdvendorname1; /* 0x104b */
+ u8 fc_spdvendorname2; /* 0x104c */
+ u8 fc_spdvendorname3; /* 0x104d */
+ u8 fc_spdvendorname4; /* 0x104e */
+ u8 fc_spdvendorname5; /* 0x104f */
+ u8 fc_spdvendorname6; /* 0x1050 */
+ u8 fc_spdvendorname7; /* 0x1051 */
+ u8 fc_sdpproductname0; /* 0x1052 */
+ u8 fc_sdpproductname1; /* 0x1053 */
+ u8 fc_sdpproductname2; /* 0x1054 */
+ u8 fc_sdpproductname3; /* 0x1055 */
+ u8 fc_sdpproductname4; /* 0x1056 */
+ u8 fc_sdpproductname5; /* 0x1057 */
+ u8 fc_sdpproductname6; /* 0x1058 */
+ u8 fc_sdpproductname7; /* 0x1059 */
+ u8 fc_sdpproductname8; /* 0x105a */
+ u8 fc_sdpproductname9; /* 0x105b */
+ u8 fc_sdpproductname10; /* 0x105c */
+ u8 fc_sdpproductname11; /* 0x105d */
+ u8 fc_sdpproductname12; /* 0x105e */
+ u8 fc_sdpproductname13; /* 0x105f */
+ u8 fc_sdpproductname14; /* 0x1060 */
+ u8 fc_spdproductname15; /* 0x1061 */
+ u8 fc_spddeviceinf; /* 0x1062 */
+ u8 fc_audsconf; /* 0x1063 */
+ u8 fc_audsstat; /* 0x1064 */
+ u8 reserved7[0xb];
+ u8 fc_datach0fill; /* 0x1070 */
+ u8 fc_datach1fill; /* 0x1071 */
+ u8 fc_datach2fill; /* 0x1072 */
+ u8 fc_ctrlqhigh; /* 0x1073 */
+ u8 fc_ctrlqlow; /* 0x1074 */
+ u8 fc_acp0; /* 0x1075 */
+ u8 fc_acp28; /* 0x1076 */
+ u8 fc_acp27; /* 0x1077 */
+ u8 fc_acp26; /* 0x1078 */
+ u8 fc_acp25; /* 0x1079 */
+ u8 fc_acp24; /* 0x107a */
+ u8 fc_acp23; /* 0x107b */
+ u8 fc_acp22; /* 0x107c */
+ u8 fc_acp21; /* 0x107d */
+ u8 fc_acp20; /* 0x107e */
+ u8 fc_acp19; /* 0x107f */
+ u8 fc_acp18; /* 0x1080 */
+ u8 fc_acp17; /* 0x1081 */
+ u8 fc_acp16; /* 0x1082 */
+ u8 fc_acp15; /* 0x1083 */
+ u8 fc_acp14; /* 0x1084 */
+ u8 fc_acp13; /* 0x1085 */
+ u8 fc_acp12; /* 0x1086 */
+ u8 fc_acp11; /* 0x1087 */
+ u8 fc_acp10; /* 0x1088 */
+ u8 fc_acp9; /* 0x1089 */
+ u8 fc_acp8; /* 0x108a */
+ u8 fc_acp7; /* 0x108b */
+ u8 fc_acp6; /* 0x108c */
+ u8 fc_acp5; /* 0x108d */
+ u8 fc_acp4; /* 0x108e */
+ u8 fc_acp3; /* 0x108f */
+ u8 fc_acp2; /* 0x1090 */
+ u8 fc_acp1; /* 0x1091 */
+ u8 fc_iscr1_0; /* 0x1092 */
+ u8 fc_iscr1_16; /* 0x1093 */
+ u8 fc_iscr1_15; /* 0x1094 */
+ u8 fc_iscr1_14; /* 0x1095 */
+ u8 fc_iscr1_13; /* 0x1096 */
+ u8 fc_iscr1_12; /* 0x1097 */
+ u8 fc_iscr1_11; /* 0x1098 */
+ u8 fc_iscr1_10; /* 0x1099 */
+ u8 fc_iscr1_9; /* 0x109a */
+ u8 fc_iscr1_8; /* 0x109b */
+ u8 fc_iscr1_7; /* 0x109c */
+ u8 fc_iscr1_6; /* 0x109d */
+ u8 fc_iscr1_5; /* 0x109e */
+ u8 fc_iscr1_4; /* 0x109f */
+ u8 fc_iscr1_3; /* 0x10a0 */
+ u8 fc_iscr1_2; /* 0x10a1 */
+ u8 fc_iscr1_1; /* 0x10a2 */
+ u8 fc_iscr2_15; /* 0x10a3 */
+ u8 fc_iscr2_14; /* 0x10a4 */
+ u8 fc_iscr2_13; /* 0x10a5 */
+ u8 fc_iscr2_12; /* 0x10a6 */
+ u8 fc_iscr2_11; /* 0x10a7 */
+ u8 fc_iscr2_10; /* 0x10a8 */
+ u8 fc_iscr2_9; /* 0x10a9 */
+ u8 fc_iscr2_8; /* 0x10aa */
+ u8 fc_iscr2_7; /* 0x10ab */
+ u8 fc_iscr2_6; /* 0x10ac */
+ u8 fc_iscr2_5; /* 0x10ad */
+ u8 fc_iscr2_4; /* 0x10ae */
+ u8 fc_iscr2_3; /* 0x10af */
+ u8 fc_iscr2_2; /* 0x10b0 */
+ u8 fc_iscr2_1; /* 0x10b1 */
+ u8 fc_iscr2_0; /* 0x10b2 */
+ u8 fc_datauto0; /* 0x10b3 */
+ u8 fc_datauto1; /* 0x10b4 */
+ u8 fc_datauto2; /* 0x10b5 */
+ u8 fc_datman; /* 0x10b6 */
+ u8 fc_datauto3; /* 0x10b7 */
+ u8 fc_rdrb0; /* 0x10b8 */
+ u8 fc_rdrb1; /* 0x10b9 */
+ u8 fc_rdrb2; /* 0x10ba */
+ u8 fc_rdrb3; /* 0x10bb */
+ u8 fc_rdrb4; /* 0x10bc */
+ u8 fc_rdrb5; /* 0x10bd */
+ u8 fc_rdrb6; /* 0x10be */
+ u8 fc_rdrb7; /* 0x10bf */
+ u8 reserved8[0x10];
+ u8 fc_stat0; /* 0x10d0 */
+ u8 fc_int0; /* 0x10d1 */
+ u8 fc_mask0; /* 0x10d2 */
+ u8 fc_pol0; /* 0x10d3 */
+ u8 fc_stat1; /* 0x10d4 */
+ u8 fc_int1; /* 0x10d5 */
+ u8 fc_mask1; /* 0x10d6 */
+ u8 fc_pol1; /* 0x10d7 */
+ u8 fc_stat2; /* 0x10d8 */
+ u8 fc_int2; /* 0x10d9 */
+ u8 fc_mask2; /* 0x10da */
+ u8 fc_pol2; /* 0x10db */
+ u8 reserved9[0x4];
+ u8 fc_prconf; /* 0x10e0 */
+ u8 reserved10[0x1f];
+ u8 fc_gmd_stat; /* 0x1100 */
+ u8 fc_gmd_en; /* 0x1101 */
+ u8 fc_gmd_up; /* 0x1102 */
+ u8 fc_gmd_conf; /* 0x1103 */
+ u8 fc_gmd_hb; /* 0x1104 */
+ u8 fc_gmd_pb0; /* 0x1105 */
+ u8 fc_gmd_pb1; /* 0x1106 */
+ u8 fc_gmd_pb2; /* 0x1107 */
+ u8 fc_gmd_pb3; /* 0x1108 */
+ u8 fc_gmd_pb4; /* 0x1109 */
+ u8 fc_gmd_pb5; /* 0x110a */
+ u8 fc_gmd_pb6; /* 0x110b */
+ u8 fc_gmd_pb7; /* 0x110c */
+ u8 fc_gmd_pb8; /* 0x110d */
+ u8 fc_gmd_pb9; /* 0x110e */
+ u8 fc_gmd_pb10; /* 0x110f */
+ u8 fc_gmd_pb11; /* 0x1110 */
+ u8 fc_gmd_pb12; /* 0x1111 */
+ u8 fc_gmd_pb13; /* 0x1112 */
+ u8 fc_gmd_pb14; /* 0x1113 */
+ u8 fc_gmd_pb15; /* 0x1114 */
+ u8 fc_gmd_pb16; /* 0x1115 */
+ u8 fc_gmd_pb17; /* 0x1116 */
+ u8 fc_gmd_pb18; /* 0x1117 */
+ u8 fc_gmd_pb19; /* 0x1118 */
+ u8 fc_gmd_pb20; /* 0x1119 */
+ u8 fc_gmd_pb21; /* 0x111a */
+ u8 fc_gmd_pb22; /* 0x111b */
+ u8 fc_gmd_pb23; /* 0x111c */
+ u8 fc_gmd_pb24; /* 0x111d */
+ u8 fc_gmd_pb25; /* 0x111e */
+ u8 fc_gmd_pb26; /* 0x111f */
+ u8 fc_gmd_pb27; /* 0x1120 */
+ u8 reserved11[0xdf];
+ u8 fc_dbgforce; /* 0x1200 */
+ u8 fc_dbgaud0ch0; /* 0x1201 */
+ u8 fc_dbgaud1ch0; /* 0x1202 */
+ u8 fc_dbgaud2ch0; /* 0x1203 */
+ u8 fc_dbgaud0ch1; /* 0x1204 */
+ u8 fc_dbgaud1ch1; /* 0x1205 */
+ u8 fc_dbgaud2ch1; /* 0x1206 */
+ u8 fc_dbgaud0ch2; /* 0x1207 */
+ u8 fc_dbgaud1ch2; /* 0x1208 */
+ u8 fc_dbgaud2ch2; /* 0x1209 */
+ u8 fc_dbgaud0ch3; /* 0x120a */
+ u8 fc_dbgaud1ch3; /* 0x120b */
+ u8 fc_dbgaud2ch3; /* 0x120c */
+ u8 fc_dbgaud0ch4; /* 0x120d */
+ u8 fc_dbgaud1ch4; /* 0x120e */
+ u8 fc_dbgaud2ch4; /* 0x120f */
+ u8 fc_dbgaud0ch5; /* 0x1210 */
+ u8 fc_dbgaud1ch5; /* 0x1211 */
+ u8 fc_dbgaud2ch5; /* 0x1212 */
+ u8 fc_dbgaud0ch6; /* 0x1213 */
+ u8 fc_dbgaud1ch6; /* 0x1214 */
+ u8 fc_dbgaud2ch6; /* 0x1215 */
+ u8 fc_dbgaud0ch7; /* 0x1216 */
+ u8 fc_dbgaud1ch7; /* 0x1217 */
+ u8 fc_dbgaud2ch7; /* 0x1218 */
+ u8 fc_dbgtmds0; /* 0x1219 */
+ u8 fc_dbgtmds1; /* 0x121a */
+ u8 fc_dbgtmds2; /* 0x121b */
+ u8 reserved12[0x1de4];
+ /* Hdmi Source Phy Registers */
+ u8 phy_conf0; /* 0x3000 */
+ u8 phy_tst0; /* 0x3001 */
+ u8 phy_tst1; /* 0x3002 */
+ u8 phy_tst2; /* 0x3003 */
+ u8 phy_stat0; /* 0x3004 */
+ u8 phy_int0; /* 0x3005 */
+ u8 phy_mask0; /* 0x3006 */
+ u8 phy_pol0; /* 0x3007 */
+ u8 reserved13[0x18];
+ /* Hdmi Master Phy Registers */
+ u8 phy_i2cm_slave_addr; /* 0x3020 */
+ u8 phy_i2cm_address_addr; /* 0x3021 */
+ u8 phy_i2cm_datao_1_addr; /* 0x3022 */
+ u8 phy_i2cm_datao_0_addr; /* 0x3023 */
+ u8 phy_i2cm_datai_1_addr; /* 0x3024 */
+ u8 phy_i2cm_datai_0_addr; /* 0x3025 */
+ u8 phy_i2cm_operation_addr; /* 0x3026 */
+ u8 phy_i2cm_int_addr; /* 0x3027 */
+ u8 phy_i2cm_ctlint_addr; /* 0x3028 */
+ u8 phy_i2cm_div_addr; /* 0x3029 */
+ u8 phy_i2cm_softrstz_addr; /* 0x302a */
+ u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */
+ u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */
+ u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */
+ u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */
+ u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */
+ u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */
+ u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */
+ u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */
+ u8 reserved14[0xcd];
+ /* Audio Sampler Registers */
+ u8 aud_conf0; /* 0x3100 */
+ u8 aud_conf1; /* 0x3101 */
+ u8 aud_int; /* 0x3102 */
+ u8 aud_conf2; /* 0x3103 */
+ u8 reserved15[0xfc];
+ u8 aud_n1; /* 0x3200 */
+ u8 aud_n2; /* 0x3201 */
+ u8 aud_n3; /* 0x3202 */
+ u8 aud_cts1; /* 0x3203 */
+ u8 aud_cts2; /* 0x3204 */
+ u8 aud_cts3; /* 0x3205 */
+ u8 aud_inputclkfs; /* 0x3206 */
+ u8 reserved16[0xfb];
+ u8 aud_spdifint; /* 0x3302 */
+ u8 reserved17[0xfd];
+ u8 aud_conf0_hbr; /* 0x3400 */
+ u8 aud_hbr_status; /* 0x3401 */
+ u8 aud_hbr_int; /* 0x3402 */
+ u8 aud_hbr_pol; /* 0x3403 */
+ u8 aud_hbr_mask; /* 0x3404 */
+ u8 reserved18[0xfb];
+ /*
+ * Generic Parallel Audio Interface Registers
+ * Not used as GPAUD interface is not enabled in hw
+ */
+ u8 gp_conf0; /* 0x3500 */
+ u8 gp_conf1; /* 0x3501 */
+ u8 gp_conf2; /* 0x3502 */
+ u8 gp_stat; /* 0x3503 */
+ u8 gp_int; /* 0x3504 */
+ u8 gp_mask; /* 0x3505 */
+ u8 gp_pol; /* 0x3506 */
+ u8 reserved19[0xf9];
+ /* Audio DMA Registers */
+ u8 ahb_dma_conf0; /* 0x3600 */
+ u8 ahb_dma_start; /* 0x3601 */
+ u8 ahb_dma_stop; /* 0x3602 */
+ u8 ahb_dma_thrsld; /* 0x3603 */
+ u8 ahb_dma_straddr0; /* 0x3604 */
+ u8 ahb_dma_straddr1; /* 0x3605 */
+ u8 ahb_dma_straddr2; /* 0x3606 */
+ u8 ahb_dma_straddr3; /* 0x3607 */
+ u8 ahb_dma_stpaddr0; /* 0x3608 */
+ u8 ahb_dma_stpaddr1; /* 0x3609 */
+ u8 ahb_dma_stpaddr2; /* 0x360a */
+ u8 ahb_dma_stpaddr3; /* 0x360b */
+ u8 ahb_dma_bstaddr0; /* 0x360c */
+ u8 ahb_dma_bstaddr1; /* 0x360d */
+ u8 ahb_dma_bstaddr2; /* 0x360e */
+ u8 ahb_dma_bstaddr3; /* 0x360f */
+ u8 ahb_dma_mblength0; /* 0x3610 */
+ u8 ahb_dma_mblength1; /* 0x3611 */
+ u8 ahb_dma_stat; /* 0x3612 */
+ u8 ahb_dma_int; /* 0x3613 */
+ u8 ahb_dma_mask; /* 0x3614 */
+ u8 ahb_dma_pol; /* 0x3615 */
+ u8 ahb_dma_conf1; /* 0x3616 */
+ u8 ahb_dma_buffstat; /* 0x3617 */
+ u8 ahb_dma_buffint; /* 0x3618 */
+ u8 ahb_dma_buffmask; /* 0x3619 */
+ u8 ahb_dma_buffpol; /* 0x361a */
+ u8 reserved20[0x9e5];
+ /* Main Controller Registers */
+ u8 mc_sfrdiv; /* 0x4000 */
+ u8 mc_clkdis; /* 0x4001 */
+ u8 mc_swrstz; /* 0x4002 */
+ u8 mc_opctrl; /* 0x4003 */
+ u8 mc_flowctrl; /* 0x4004 */
+ u8 mc_phyrstz; /* 0x4005 */
+ u8 mc_lockonclock; /* 0x4006 */
+ u8 mc_heacphy_rst; /* 0x4007 */
+ u8 reserved21[0xf8];
+ /* Colorspace Converter Registers */
+ u8 csc_cfg; /* 0x4100 */
+ u8 csc_scale; /* 0x4101 */
+ u8 csc_coef_a1_msb; /* 0x4102 */
+ u8 csc_coef_a1_lsb; /* 0x4103 */
+ u8 csc_coef_a2_msb; /* 0x4104 */
+ u8 csc_coef_a2_lsb; /* 0x4105 */
+ u8 csc_coef_a3_msb; /* 0x4106 */
+ u8 csc_coef_a3_lsb; /* 0x4107 */
+ u8 csc_coef_a4_msb; /* 0x4108 */
+ u8 csc_coef_a4_lsb; /* 0x4109 */
+ u8 csc_coef_b1_msb; /* 0x410a */
+ u8 csc_coef_b1_lsb; /* 0x410b */
+ u8 csc_coef_b2_msb; /* 0x410c */
+ u8 csc_coef_b2_lsb; /* 0x410d */
+ u8 csc_coef_b3_msb; /* 0x410e */
+ u8 csc_coef_b3_lsb; /* 0x410f */
+ u8 csc_coef_b4_msb; /* 0x4110 */
+ u8 csc_coef_b4_lsb; /* 0x4111 */
+ u8 csc_coef_c1_msb; /* 0x4112 */
+ u8 csc_coef_c1_lsb; /* 0x4113 */
+ u8 csc_coef_c2_msb; /* 0x4114 */
+ u8 csc_coef_c2_lsb; /* 0x4115 */
+ u8 csc_coef_c3_msb; /* 0x4116 */
+ u8 csc_coef_c3_lsb; /* 0x4117 */
+ u8 csc_coef_c4_msb; /* 0x4118 */
+ u8 csc_coef_c4_lsb; /* 0x4119 */
+ u8 reserved22[0xee6];
+ /* HDCP Encryption Engine Registers */
+ u8 a_hdcpcfg0; /* 0x5000 */
+ u8 a_hdcpcfg1; /* 0x5001 */
+ u8 a_hdcpobs0; /* 0x5002 */
+ u8 a_hdcpobs1; /* 0x5003 */
+ u8 a_hdcpobs2; /* 0x5004 */
+ u8 a_hdcpobs3; /* 0x5005 */
+ u8 a_apiintclr; /* 0x5006 */
+ u8 a_apiintstat; /* 0x5007 */
+ u8 a_apiintmsk; /* 0x5008 */
+ u8 a_vidpolcfg; /* 0x5009 */
+ u8 a_oesswcfg; /* 0x500a */
+ u8 a_timer1setup0; /* 0x500b */
+ u8 a_timer1setup1; /* 0x500c */
+ u8 a_timer2setup0; /* 0x500d */
+ u8 a_timer2setup1; /* 0x500e */
+ u8 a_100mscfg; /* 0x500f */
+ u8 a_2scfg0; /* 0x5010 */
+ u8 a_2scfg1; /* 0x5011 */
+ u8 a_5scfg0; /* 0x5012 */
+ u8 a_5scfg1; /* 0x5013 */
+ u8 a_srmverlsb; /* 0x5014 */
+ u8 a_srmvermsb; /* 0x5015 */
+ u8 a_srmctrl; /* 0x5016 */
+ u8 a_sfrsetup; /* 0x5017 */
+ u8 a_i2chsetup; /* 0x5018 */
+ u8 a_intsetup; /* 0x5019 */
+ u8 a_presetup; /* 0x501a */
+ u8 reserved23[0x5];
+ u8 a_srm_base; /* 0x5020 */
+ u8 reserved24[0x2cdf];
+ /* CEC Engine Registers */
+ u8 cec_ctrl; /* 0x7d00 */
+ u8 cec_stat; /* 0x7d01 */
+ u8 cec_mask; /* 0x7d02 */
+ u8 cec_polarity; /* 0x7d03 */
+ u8 cec_int; /* 0x7d04 */
+ u8 cec_addr_l; /* 0x7d05 */
+ u8 cec_addr_h; /* 0x7d06 */
+ u8 cec_tx_cnt; /* 0x7d07 */
+ u8 cec_rx_cnt; /* 0x7d08 */
+ u8 reserved25[0x7];
+ u8 cec_tx_data0; /* 0x7d10 */
+ u8 cec_tx_data1; /* 0x7d11 */
+ u8 cec_tx_data2; /* 0x7d12 */
+ u8 cec_tx_data3; /* 0x7d13 */
+ u8 cec_tx_data4; /* 0x7d14 */
+ u8 cec_tx_data5; /* 0x7d15 */
+ u8 cec_tx_data6; /* 0x7d16 */
+ u8 cec_tx_data7; /* 0x7d17 */
+ u8 cec_tx_data8; /* 0x7d18 */
+ u8 cec_tx_data9; /* 0x7d19 */
+ u8 cec_tx_data10; /* 0x7d1a */
+ u8 cec_tx_data11; /* 0x7d1b */
+ u8 cec_tx_data12; /* 0x7d1c */
+ u8 cec_tx_data13; /* 0x7d1d */
+ u8 cec_tx_data14; /* 0x7d1e */
+ u8 cec_tx_data15; /* 0x7d1f */
+ u8 cec_rx_data0; /* 0x7d20 */
+ u8 cec_rx_data1; /* 0x7d21 */
+ u8 cec_rx_data2; /* 0x7d22 */
+ u8 cec_rx_data3; /* 0x7d23 */
+ u8 cec_rx_data4; /* 0x7d24 */
+ u8 cec_rx_data5; /* 0x7d25 */
+ u8 cec_rx_data6; /* 0x7d26 */
+ u8 cec_rx_data7; /* 0x7d27 */
+ u8 cec_rx_data8; /* 0x7d28 */
+ u8 cec_rx_data9; /* 0x7d29 */
+ u8 cec_rx_data10; /* 0x7d2a */
+ u8 cec_rx_data11; /* 0x7d2b */
+ u8 cec_rx_data12; /* 0x7d2c */
+ u8 cec_rx_data13; /* 0x7d2d */
+ u8 cec_rx_data14; /* 0x7d2e */
+ u8 cec_rx_data15; /* 0x7d2f */
+ u8 cec_lock; /* 0x7d30 */
+ u8 cec_wkupctrl; /* 0x7d31 */
+ u8 reserved26[0xce];
+ /* I2C Master Registers (E-DDC) */
+ u8 i2cm_slave; /* 0x7e00 */
+ u8 i2cmess; /* 0x7e01 */
+ u8 i2cm_datao; /* 0x7e02 */
+ u8 i2cm_datai; /* 0x7e03 */
+ u8 i2cm_operation; /* 0x7e04 */
+ u8 i2cm_int; /* 0x7e05 */
+ u8 i2cm_ctlint; /* 0x7e06 */
+ u8 i2cm_div; /* 0x7e07 */
+ u8 i2cm_segaddr; /* 0x7e08 */
+ u8 i2cm_softrstz; /* 0x7e09 */
+ u8 i2cm_segptr; /* 0x7e0a */
+ u8 i2cm_ss_scl_hcnt_1_addr; /* 0x7e0b */
+ u8 i2cm_ss_scl_hcnt_0_addr; /* 0x7e0c */
+ u8 i2cm_ss_scl_lcnt_1_addr; /* 0x7e0d */
+ u8 i2cm_ss_scl_lcnt_0_addr; /* 0x7e0e */
+ u8 i2cm_fs_scl_hcnt_1_addr; /* 0x7e0f */
+ u8 i2cm_fs_scl_hcnt_0_addr; /* 0x7e10 */
+ u8 i2cm_fs_scl_lcnt_1_addr; /* 0x7e11 */
+ u8 i2cm_fs_scl_lcnt_0_addr; /* 0x7e12 */
+ u8 reserved27[0x1ed];
+ /* Random Number Generator Registers (RNG) */
+ u8 rng_base; /* 0x8000 */
+};
/*
* Register field definitions
diff --git a/arch/arm/include/asm/arch-mxs/dma.h b/arch/arm/include/asm/arch-mxs/dma.h
index a0a0ea5010..1ac8696e64 100644
--- a/arch/arm/include/asm/arch-mxs/dma.h
+++ b/arch/arm/include/asm/arch-mxs/dma.h
@@ -40,6 +40,19 @@
/*
* MXS DMA channels
*/
+#if defined(CONFIG_MX23)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX28)
enum {
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
@@ -53,9 +66,13 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
- MXS_DMA_CHANNEL_AHB_APBH_SSP,
+ MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
+#endif
/*
* MXS DMA hardware command.
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 05eb63c6d2..8f67497760 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -36,6 +36,8 @@
#include <asm/arch/regs-rtc.h>
#include <asm/arch/regs-ssp.h>
#include <asm/arch/regs-timrot.h>
+#include <asm/arch/regs-usb.h>
+#include <asm/arch/regs-usbphy.h>
#ifdef CONFIG_MX23
#include <asm/arch/regs-clkctrl-mx23.h>
diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h
index 7abdf58b8b..42887154c4 100644
--- a/arch/arm/include/asm/arch-mxs/iomux.h
+++ b/arch/arm/include/asm/arch-mxs/iomux.h
@@ -21,6 +21,10 @@
#ifndef __MACH_MXS_IOMUX_H__
#define __MACH_MXS_IOMUX_H__
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
/*
* IOMUX/PAD Bit field definitions
*
@@ -165,4 +169,5 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad);
*/
int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
+#endif /* __ASSEMBLY__ */
#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
index 9b30f56f54..5920f9b4dc 100644
--- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -74,6 +74,32 @@ struct mxs_ssp_regs {
};
#endif
+static inline int mxs_ssp_bus_id_valid(int bus)
+{
+#if defined(CONFIG_MX23)
+ const unsigned int mxs_ssp_chan_count = 2;
+#elif defined(CONFIG_MX28)
+ const unsigned int mxs_ssp_chan_count = 4;
+#endif
+
+ if (bus >= mxs_ssp_chan_count)
+ return 0;
+
+ if (bus < 0)
+ return 0;
+
+ return 1;
+}
+
+static inline int mxs_ssp_clock_by_bus(unsigned int clock)
+{
+#if defined(CONFIG_MX23)
+ return 0;
+#elif defined(CONFIG_MX28)
+ return clock;
+#endif
+}
+
static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
{
switch (port) {
diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h
index 529a3bcdd1..f8537f1636 100644
--- a/arch/arm/include/asm/arch-mxs/regs-timrot.h
+++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h
@@ -31,6 +31,16 @@
struct mxs_timrot_regs {
mxs_reg_32(hw_timrot_rotctrl)
mxs_reg_32(hw_timrot_rotcount)
+#if defined(CONFIG_MX23)
+ mxs_reg_32(hw_timrot_timctrl0)
+ mxs_reg_32(hw_timrot_timcount0)
+ mxs_reg_32(hw_timrot_timctrl1)
+ mxs_reg_32(hw_timrot_timcount1)
+ mxs_reg_32(hw_timrot_timctrl2)
+ mxs_reg_32(hw_timrot_timcount2)
+ mxs_reg_32(hw_timrot_timctrl3)
+ mxs_reg_32(hw_timrot_timcount3)
+#elif defined(CONFIG_MX28)
mxs_reg_32(hw_timrot_timctrl0)
mxs_reg_32(hw_timrot_running_count0)
mxs_reg_32(hw_timrot_fixed_count0)
@@ -47,6 +57,7 @@ struct mxs_timrot_regs {
mxs_reg_32(hw_timrot_running_count3)
mxs_reg_32(hw_timrot_fixed_count3)
mxs_reg_32(hw_timrot_match_count3)
+#endif
mxs_reg_32(hw_timrot_version)
};
#endif
@@ -71,7 +82,11 @@ struct mxs_timrot_regs {
#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10)
#define TIMROT_ROTCTRL_POLARITY_B (1 << 9)
#define TIMROT_ROTCTRL_POLARITY_A (1 << 8)
+#if defined(CONFIG_MX23)
+#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4)
+#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
+#endif
#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
@@ -79,12 +94,21 @@ struct mxs_timrot_regs {
#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4)
+#if defined(CONFIG_MX23)
+#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4)
+#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4)
+#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4)
+#endif
+#if defined(CONFIG_MX23)
+#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7
+#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf
+#endif
#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0
#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0
#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1
@@ -92,18 +116,25 @@ struct mxs_timrot_regs {
#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3
#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4
#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5
+#if defined(CONFIG_MX23)
+#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6
+#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7
+#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6
#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7
#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8
#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9
#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa
+#endif
#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff
#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0
#define TIMROT_TIMCTRLn_IRQ (1 << 15)
#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
+#if defined(CONFIG_MX28)
#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11)
+#endif
#define TIMROT_TIMCTRLn_POLARITY (1 << 8)
#define TIMROT_TIMCTRLn_UPDATE (1 << 7)
#define TIMROT_TIMCTRLn_RELOAD (1 << 6)
@@ -121,6 +152,15 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3
#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4
#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5
+#if defined(CONFIG_MX23)
+#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6
+#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7
+#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8
+#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9
+#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa
+#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb
+#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc
+#elif defined(CONFIG_MX28)
#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6
#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7
#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8
@@ -131,15 +171,28 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd
#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe
#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf
+#endif
+#if defined(CONFIG_MX23)
+#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16)
+#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16
+#elif defined(CONFIG_MX28)
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0
+#endif
+#if defined(CONFIG_MX23)
+#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff
+#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
+#elif defined(CONFIG_MX28)
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
+#endif
+#if defined(CONFIG_MX28)
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0
+#endif
#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
@@ -149,6 +202,15 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
+#if defined(CONFIG_MX23)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16)
+#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16)
+#elif defined(CONFIG_MX28)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
@@ -159,7 +221,46 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
+#endif
+#if defined(CONFIG_MX23)
+#define TIMROT_TIMCTRL3_IRQ (1 << 15)
+#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14)
+#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10)
+#endif
#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9)
+#if defined(CONFIG_MX23)
+#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8)
+#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8
+#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8)
+#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8)
+#define TIMROT_TIMCTRL3_UPDATE (1 << 7)
+#define TIMROT_TIMCTRL3_RELOAD (1 << 6)
+#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4)
+#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4
+#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4)
+#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4)
+#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4)
+#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4)
+#define TIMROT_TIMCTRL3_SELECT_MASK 0xf
+#define TIMROT_TIMCTRL3_SELECT_OFFSET 0
+#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0
+#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1
+#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2
+#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3
+#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4
+#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5
+#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6
+#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7
+#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8
+#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9
+#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa
+#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb
+#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc
+#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16)
+#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16
+#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff
+#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0
+#endif
#define TIMROT_VERSION_MAJOR_MASK (0xff << 24)
#define TIMROT_VERSION_MAJOR_OFFSET 24
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index ffaffbb3bf..ae0babf17c 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -167,6 +167,36 @@ struct venc_regs {
#define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16
+/* LCD display type */
+#define PASSIVE_DISPLAY 0
+#define ACTIVE_DISPLAY 1
+
+/* TFTDATALINES */
+#define LCD_INTERFACE_12_BIT 0
+#define LCD_INTERFACE_16_BIT 1
+#define LCD_INTERFACE_18_BIT 2
+#define LCD_INTERFACE_24_BIT 3
+
+/* Polarity */
+#define DSS_IVS (1 << 12)
+#define DSS_IHS (1 << 13)
+#define DSS_IPC (1 << 14)
+#define DSS_IEO (1 << 15)
+
+/* GFX format */
+#define GFXFORMAT_BITMAP1 (0x0 << 1)
+#define GFXFORMAT_BITMAP2 (0x1 << 1)
+#define GFXFORMAT_BITMAP4 (0x2 << 1)
+#define GFXFORMAT_BITMAP8 (0x3 << 1)
+#define GFXFORMAT_RGB12 (0x4 << 1)
+#define GFXFORMAT_ARGB16 (0x5 << 1)
+#define GFXFORMAT_RGB16 (0x6 << 1)
+#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1)
+#define GFXFORMAT_RGB24_PACKED (0x9 << 1)
+#define GFXFORMAT_ARGB32 (0xC << 1)
+#define GFXFORMAT_RGBA32 (0xD << 1)
+#define GFXFORMAT_RGBx32 (0xE << 1)
+
/* Panel Configuration */
struct panel_config {
u32 timing_h;
@@ -178,6 +208,7 @@ struct panel_config {
u32 data_lines;
u32 load_mode;
u32 panel_color;
+ u32 gfx_format;
void *frame_buffer;
};
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index 3ce1f07b8a..0ba621a1b8 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -25,6 +25,8 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/* T2 Register definitions */
#define T2_BASE 0x48002000
@@ -59,142 +61,5 @@ typedef struct t2 {
#define OMAP_HSMMC2_BASE 0x480B4000
#define OMAP_HSMMC3_BASE 0x480AD000
-struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-};
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h
index 404e16a5a0..dec4dacbad 100644
--- a/arch/arm/include/asm/arch-omap3/spl.h
+++ b/arch/arm/include/asm/arch-omap3/spl.h
@@ -26,7 +26,7 @@
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_NAND 2
-#define BOOT_DEVICE_ONE_NAND 3
+#define BOOT_DEVICE_ONENAND 3
#define BOOT_DEVICE_MMC2 5 /*emmc*/
#define BOOT_DEVICE_MMC1 6
#define BOOT_DEVICE_XIPWAIT 7
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index be20fc0ce6..ed7a1c8be7 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -25,6 +25,7 @@
#ifndef _CLOCKS_OMAP4_H_
#define _CLOCKS_OMAP4_H_
#include <common.h>
+#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
@@ -38,479 +39,6 @@
#define CM_CLKMODE_DPLL_MPU 0x4A004160
#define CM_CLKSEL_CORE 0x4A004100
-struct omap4_prcm_regs {
- /* cm1.ckgen */
- u32 cm_clksel_core;
- u32 pad001[1];
- u32 cm_clksel_abe;
- u32 pad002[1];
- u32 cm_dll_ctrl;
- u32 pad003[3];
- u32 cm_clkmode_dpll_core;
- u32 cm_idlest_dpll_core;
- u32 cm_autoidle_dpll_core;
- u32 cm_clksel_dpll_core;
- u32 cm_div_m2_dpll_core;
- u32 cm_div_m3_dpll_core;
- u32 cm_div_m4_dpll_core;
- u32 cm_div_m5_dpll_core;
- u32 cm_div_m6_dpll_core;
- u32 cm_div_m7_dpll_core;
- u32 cm_ssc_deltamstep_dpll_core;
- u32 cm_ssc_modfreqdiv_dpll_core;
- u32 cm_emu_override_dpll_core;
- u32 pad004[3];
- u32 cm_clkmode_dpll_mpu;
- u32 cm_idlest_dpll_mpu;
- u32 cm_autoidle_dpll_mpu;
- u32 cm_clksel_dpll_mpu;
- u32 cm_div_m2_dpll_mpu;
- u32 pad005[5];
- u32 cm_ssc_deltamstep_dpll_mpu;
- u32 cm_ssc_modfreqdiv_dpll_mpu;
- u32 pad006[3];
- u32 cm_bypclk_dpll_mpu;
- u32 cm_clkmode_dpll_iva;
- u32 cm_idlest_dpll_iva;
- u32 cm_autoidle_dpll_iva;
- u32 cm_clksel_dpll_iva;
- u32 pad007[2];
- u32 cm_div_m4_dpll_iva;
- u32 cm_div_m5_dpll_iva;
- u32 pad008[2];
- u32 cm_ssc_deltamstep_dpll_iva;
- u32 cm_ssc_modfreqdiv_dpll_iva;
- u32 pad009[3];
- u32 cm_bypclk_dpll_iva;
- u32 cm_clkmode_dpll_abe;
- u32 cm_idlest_dpll_abe;
- u32 cm_autoidle_dpll_abe;
- u32 cm_clksel_dpll_abe;
- u32 cm_div_m2_dpll_abe;
- u32 cm_div_m3_dpll_abe;
- u32 pad010[4];
- u32 cm_ssc_deltamstep_dpll_abe;
- u32 cm_ssc_modfreqdiv_dpll_abe;
- u32 pad011[4];
- u32 cm_clkmode_dpll_ddrphy;
- u32 cm_idlest_dpll_ddrphy;
- u32 cm_autoidle_dpll_ddrphy;
- u32 cm_clksel_dpll_ddrphy;
- u32 cm_div_m2_dpll_ddrphy;
- u32 pad012[1];
- u32 cm_div_m4_dpll_ddrphy;
- u32 cm_div_m5_dpll_ddrphy;
- u32 cm_div_m6_dpll_ddrphy;
- u32 pad013[1];
- u32 cm_ssc_deltamstep_dpll_ddrphy;
- u32 pad014[5];
- u32 cm_shadow_freq_config1;
- u32 pad0141[47];
- u32 cm_mpu_mpu_clkctrl;
-
- /* cm1.dsp */
- u32 pad015[55];
- u32 cm_dsp_clkstctrl;
- u32 pad016[7];
- u32 cm_dsp_dsp_clkctrl;
-
- /* cm1.abe */
- u32 pad017[55];
- u32 cm1_abe_clkstctrl;
- u32 pad018[7];
- u32 cm1_abe_l4abe_clkctrl;
- u32 pad019[1];
- u32 cm1_abe_aess_clkctrl;
- u32 pad020[1];
- u32 cm1_abe_pdm_clkctrl;
- u32 pad021[1];
- u32 cm1_abe_dmic_clkctrl;
- u32 pad022[1];
- u32 cm1_abe_mcasp_clkctrl;
- u32 pad023[1];
- u32 cm1_abe_mcbsp1_clkctrl;
- u32 pad024[1];
- u32 cm1_abe_mcbsp2_clkctrl;
- u32 pad025[1];
- u32 cm1_abe_mcbsp3_clkctrl;
- u32 pad026[1];
- u32 cm1_abe_slimbus_clkctrl;
- u32 pad027[1];
- u32 cm1_abe_timer5_clkctrl;
- u32 pad028[1];
- u32 cm1_abe_timer6_clkctrl;
- u32 pad029[1];
- u32 cm1_abe_timer7_clkctrl;
- u32 pad030[1];
- u32 cm1_abe_timer8_clkctrl;
- u32 pad031[1];
- u32 cm1_abe_wdt3_clkctrl;
-
- /* cm2.ckgen */
- u32 pad032[3805];
- u32 cm_clksel_mpu_m3_iss_root;
- u32 cm_clksel_usb_60mhz;
- u32 cm_scale_fclk;
- u32 pad033[1];
- u32 cm_core_dvfs_perf1;
- u32 cm_core_dvfs_perf2;
- u32 cm_core_dvfs_perf3;
- u32 cm_core_dvfs_perf4;
- u32 pad034[1];
- u32 cm_core_dvfs_current;
- u32 cm_iva_dvfs_perf_tesla;
- u32 cm_iva_dvfs_perf_ivahd;
- u32 cm_iva_dvfs_perf_abe;
- u32 pad035[1];
- u32 cm_iva_dvfs_current;
- u32 pad036[1];
- u32 cm_clkmode_dpll_per;
- u32 cm_idlest_dpll_per;
- u32 cm_autoidle_dpll_per;
- u32 cm_clksel_dpll_per;
- u32 cm_div_m2_dpll_per;
- u32 cm_div_m3_dpll_per;
- u32 cm_div_m4_dpll_per;
- u32 cm_div_m5_dpll_per;
- u32 cm_div_m6_dpll_per;
- u32 cm_div_m7_dpll_per;
- u32 cm_ssc_deltamstep_dpll_per;
- u32 cm_ssc_modfreqdiv_dpll_per;
- u32 cm_emu_override_dpll_per;
- u32 pad037[3];
- u32 cm_clkmode_dpll_usb;
- u32 cm_idlest_dpll_usb;
- u32 cm_autoidle_dpll_usb;
- u32 cm_clksel_dpll_usb;
- u32 cm_div_m2_dpll_usb;
- u32 pad038[5];
- u32 cm_ssc_deltamstep_dpll_usb;
- u32 cm_ssc_modfreqdiv_dpll_usb;
- u32 pad039[1];
- u32 cm_clkdcoldo_dpll_usb;
- u32 pad040[2];
- u32 cm_clkmode_dpll_unipro;
- u32 cm_idlest_dpll_unipro;
- u32 cm_autoidle_dpll_unipro;
- u32 cm_clksel_dpll_unipro;
- u32 cm_div_m2_dpll_unipro;
- u32 pad041[5];
- u32 cm_ssc_deltamstep_dpll_unipro;
- u32 cm_ssc_modfreqdiv_dpll_unipro;
-
- /* cm2.core */
- u32 pad0411[324];
- u32 cm_l3_1_clkstctrl;
- u32 pad042[1];
- u32 cm_l3_1_dynamicdep;
- u32 pad043[5];
- u32 cm_l3_1_l3_1_clkctrl;
- u32 pad044[55];
- u32 cm_l3_2_clkstctrl;
- u32 pad045[1];
- u32 cm_l3_2_dynamicdep;
- u32 pad046[5];
- u32 cm_l3_2_l3_2_clkctrl;
- u32 pad047[1];
- u32 cm_l3_2_gpmc_clkctrl;
- u32 pad048[1];
- u32 cm_l3_2_ocmc_ram_clkctrl;
- u32 pad049[51];
- u32 cm_mpu_m3_clkstctrl;
- u32 cm_mpu_m3_staticdep;
- u32 cm_mpu_m3_dynamicdep;
- u32 pad050[5];
- u32 cm_mpu_m3_mpu_m3_clkctrl;
- u32 pad051[55];
- u32 cm_sdma_clkstctrl;
- u32 cm_sdma_staticdep;
- u32 cm_sdma_dynamicdep;
- u32 pad052[5];
- u32 cm_sdma_sdma_clkctrl;
- u32 pad053[55];
- u32 cm_memif_clkstctrl;
- u32 pad054[7];
- u32 cm_memif_dmm_clkctrl;
- u32 pad055[1];
- u32 cm_memif_emif_fw_clkctrl;
- u32 pad056[1];
- u32 cm_memif_emif_1_clkctrl;
- u32 pad057[1];
- u32 cm_memif_emif_2_clkctrl;
- u32 pad058[1];
- u32 cm_memif_dll_clkctrl;
- u32 pad059[3];
- u32 cm_memif_emif_h1_clkctrl;
- u32 pad060[1];
- u32 cm_memif_emif_h2_clkctrl;
- u32 pad061[1];
- u32 cm_memif_dll_h_clkctrl;
- u32 pad062[39];
- u32 cm_c2c_clkstctrl;
- u32 cm_c2c_staticdep;
- u32 cm_c2c_dynamicdep;
- u32 pad063[5];
- u32 cm_c2c_sad2d_clkctrl;
- u32 pad064[1];
- u32 cm_c2c_modem_icr_clkctrl;
- u32 pad065[1];
- u32 cm_c2c_sad2d_fw_clkctrl;
- u32 pad066[51];
- u32 cm_l4cfg_clkstctrl;
- u32 pad067[1];
- u32 cm_l4cfg_dynamicdep;
- u32 pad068[5];
- u32 cm_l4cfg_l4_cfg_clkctrl;
- u32 pad069[1];
- u32 cm_l4cfg_hw_sem_clkctrl;
- u32 pad070[1];
- u32 cm_l4cfg_mailbox_clkctrl;
- u32 pad071[1];
- u32 cm_l4cfg_sar_rom_clkctrl;
- u32 pad072[49];
- u32 cm_l3instr_clkstctrl;
- u32 pad073[7];
- u32 cm_l3instr_l3_3_clkctrl;
- u32 pad074[1];
- u32 cm_l3instr_l3_instr_clkctrl;
- u32 pad075[5];
- u32 cm_l3instr_intrconn_wp1_clkctrl;
-
-
- /* cm2.ivahd */
- u32 pad076[47];
- u32 cm_ivahd_clkstctrl;
- u32 pad077[7];
- u32 cm_ivahd_ivahd_clkctrl;
- u32 pad078[1];
- u32 cm_ivahd_sl2_clkctrl;
-
- /* cm2.cam */
- u32 pad079[53];
- u32 cm_cam_clkstctrl;
- u32 pad080[7];
- u32 cm_cam_iss_clkctrl;
- u32 pad081[1];
- u32 cm_cam_fdif_clkctrl;
-
- /* cm2.dss */
- u32 pad082[53];
- u32 cm_dss_clkstctrl;
- u32 pad083[7];
- u32 cm_dss_dss_clkctrl;
-
- /* cm2.sgx */
- u32 pad084[55];
- u32 cm_sgx_clkstctrl;
- u32 pad085[7];
- u32 cm_sgx_sgx_clkctrl;
-
- /* cm2.l3init */
- u32 pad086[55];
- u32 cm_l3init_clkstctrl;
-
- /* cm2.l3init */
- u32 pad087[9];
- u32 cm_l3init_hsmmc1_clkctrl;
- u32 pad088[1];
- u32 cm_l3init_hsmmc2_clkctrl;
- u32 pad089[1];
- u32 cm_l3init_hsi_clkctrl;
- u32 pad090[7];
- u32 cm_l3init_hsusbhost_clkctrl;
- u32 pad091[1];
- u32 cm_l3init_hsusbotg_clkctrl;
- u32 pad092[1];
- u32 cm_l3init_hsusbtll_clkctrl;
- u32 pad093[3];
- u32 cm_l3init_p1500_clkctrl;
- u32 pad094[21];
- u32 cm_l3init_fsusb_clkctrl;
- u32 pad095[3];
- u32 cm_l3init_usbphy_clkctrl;
-
- /* cm2.l4per */
- u32 pad096[7];
- u32 cm_l4per_clkstctrl;
- u32 pad097[1];
- u32 cm_l4per_dynamicdep;
- u32 pad098[5];
- u32 cm_l4per_adc_clkctrl;
- u32 pad100[1];
- u32 cm_l4per_gptimer10_clkctrl;
- u32 pad101[1];
- u32 cm_l4per_gptimer11_clkctrl;
- u32 pad102[1];
- u32 cm_l4per_gptimer2_clkctrl;
- u32 pad103[1];
- u32 cm_l4per_gptimer3_clkctrl;
- u32 pad104[1];
- u32 cm_l4per_gptimer4_clkctrl;
- u32 pad105[1];
- u32 cm_l4per_gptimer9_clkctrl;
- u32 pad106[1];
- u32 cm_l4per_elm_clkctrl;
- u32 pad107[1];
- u32 cm_l4per_gpio2_clkctrl;
- u32 pad108[1];
- u32 cm_l4per_gpio3_clkctrl;
- u32 pad109[1];
- u32 cm_l4per_gpio4_clkctrl;
- u32 pad110[1];
- u32 cm_l4per_gpio5_clkctrl;
- u32 pad111[1];
- u32 cm_l4per_gpio6_clkctrl;
- u32 pad112[1];
- u32 cm_l4per_hdq1w_clkctrl;
- u32 pad113[1];
- u32 cm_l4per_hecc1_clkctrl;
- u32 pad114[1];
- u32 cm_l4per_hecc2_clkctrl;
- u32 pad115[1];
- u32 cm_l4per_i2c1_clkctrl;
- u32 pad116[1];
- u32 cm_l4per_i2c2_clkctrl;
- u32 pad117[1];
- u32 cm_l4per_i2c3_clkctrl;
- u32 pad118[1];
- u32 cm_l4per_i2c4_clkctrl;
- u32 pad119[1];
- u32 cm_l4per_l4per_clkctrl;
- u32 pad1191[3];
- u32 cm_l4per_mcasp2_clkctrl;
- u32 pad120[1];
- u32 cm_l4per_mcasp3_clkctrl;
- u32 pad121[1];
- u32 cm_l4per_mcbsp4_clkctrl;
- u32 pad122[1];
- u32 cm_l4per_mgate_clkctrl;
- u32 pad123[1];
- u32 cm_l4per_mcspi1_clkctrl;
- u32 pad124[1];
- u32 cm_l4per_mcspi2_clkctrl;
- u32 pad125[1];
- u32 cm_l4per_mcspi3_clkctrl;
- u32 pad126[1];
- u32 cm_l4per_mcspi4_clkctrl;
- u32 pad127[5];
- u32 cm_l4per_mmcsd3_clkctrl;
- u32 pad128[1];
- u32 cm_l4per_mmcsd4_clkctrl;
- u32 pad129[1];
- u32 cm_l4per_msprohg_clkctrl;
- u32 pad130[1];
- u32 cm_l4per_slimbus2_clkctrl;
- u32 pad131[1];
- u32 cm_l4per_uart1_clkctrl;
- u32 pad132[1];
- u32 cm_l4per_uart2_clkctrl;
- u32 pad133[1];
- u32 cm_l4per_uart3_clkctrl;
- u32 pad134[1];
- u32 cm_l4per_uart4_clkctrl;
- u32 pad135[1];
- u32 cm_l4per_mmcsd5_clkctrl;
- u32 pad136[1];
- u32 cm_l4per_i2c5_clkctrl;
- u32 pad137[5];
- u32 cm_l4sec_clkstctrl;
- u32 cm_l4sec_staticdep;
- u32 cm_l4sec_dynamicdep;
- u32 pad138[5];
- u32 cm_l4sec_aes1_clkctrl;
- u32 pad139[1];
- u32 cm_l4sec_aes2_clkctrl;
- u32 pad140[1];
- u32 cm_l4sec_des3des_clkctrl;
- u32 pad141[1];
- u32 cm_l4sec_pkaeip29_clkctrl;
- u32 pad142[1];
- u32 cm_l4sec_rng_clkctrl;
- u32 pad143[1];
- u32 cm_l4sec_sha2md51_clkctrl;
- u32 pad144[3];
- u32 cm_l4sec_cryptodma_clkctrl;
- u32 pad145[776841];
-
- /* l4 wkup regs */
- u32 pad201[6211];
- u32 cm_abe_pll_ref_clksel;
- u32 cm_sys_clksel;
- u32 pad202[1467];
- u32 cm_wkup_clkstctrl;
- u32 pad203[7];
- u32 cm_wkup_l4wkup_clkctrl;
- u32 pad204;
- u32 cm_wkup_wdtimer1_clkctrl;
- u32 pad205;
- u32 cm_wkup_wdtimer2_clkctrl;
- u32 pad206;
- u32 cm_wkup_gpio1_clkctrl;
- u32 pad207;
- u32 cm_wkup_gptimer1_clkctrl;
- u32 pad208;
- u32 cm_wkup_gptimer12_clkctrl;
- u32 pad209;
- u32 cm_wkup_synctimer_clkctrl;
- u32 pad210;
- u32 cm_wkup_usim_clkctrl;
- u32 pad211;
- u32 cm_wkup_sarram_clkctrl;
- u32 pad212[5];
- u32 cm_wkup_keyboard_clkctrl;
- u32 pad213;
- u32 cm_wkup_rtc_clkctrl;
- u32 pad214;
- u32 cm_wkup_bandgap_clkctrl;
- u32 pad215[197];
- u32 prm_vc_val_bypass;
- u32 prm_vc_cfg_channel;
- u32 prm_vc_cfg_i2c_mode;
- u32 prm_vc_cfg_i2c_clk;
-
-};
-
-struct omap4_scrm_regs {
- u32 revision; /* 0x0000 */
- u32 pad00[63];
- u32 clksetuptime; /* 0x0100 */
- u32 pmicsetuptime; /* 0x0104 */
- u32 pad01[2];
- u32 altclksrc; /* 0x0110 */
- u32 pad02[2];
- u32 c2cclkm; /* 0x011c */
- u32 pad03[56];
- u32 extclkreq; /* 0x0200 */
- u32 accclkreq; /* 0x0204 */
- u32 pwrreq; /* 0x0208 */
- u32 pad04[1];
- u32 auxclkreq0; /* 0x0210 */
- u32 auxclkreq1; /* 0x0214 */
- u32 auxclkreq2; /* 0x0218 */
- u32 auxclkreq3; /* 0x021c */
- u32 auxclkreq4; /* 0x0220 */
- u32 auxclkreq5; /* 0x0224 */
- u32 pad05[3];
- u32 c2cclkreq; /* 0x0234 */
- u32 pad06[54];
- u32 auxclk0; /* 0x0310 */
- u32 auxclk1; /* 0x0314 */
- u32 auxclk2; /* 0x0318 */
- u32 auxclk3; /* 0x031c */
- u32 auxclk4; /* 0x0320 */
- u32 auxclk5; /* 0x0324 */
- u32 pad07[54];
- u32 rsttime_reg; /* 0x0400 */
- u32 pad08[6];
- u32 c2crstctrl; /* 0x041c */
- u32 extpwronrstctrl; /* 0x0420 */
- u32 pad09[59];
- u32 extwarmrstst_reg; /* 0x0510 */
- u32 apewarmrstst_reg; /* 0x0514 */
- u32 pad10[1];
- u32 c2cwarmrstst_reg; /* 0x051C */
-};
-
/* DPLL register offsets */
#define CM_CLKMODE_DPLL 0
#define CM_IDLEST_DPLL 0x4
@@ -714,54 +242,44 @@ struct omap4_scrm_regs {
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
-#define NUM_SYS_CLKS 7
-
-struct dpll_regs {
- u32 cm_clkmode_dpll;
- u32 cm_idlest_dpll;
- u32 cm_autoidle_dpll;
- u32 cm_clksel_dpll;
- u32 cm_div_m2_dpll;
- u32 cm_div_m3_dpll;
- u32 cm_div_m4_dpll;
- u32 cm_div_m5_dpll;
- u32 cm_div_m6_dpll;
- u32 cm_div_m7_dpll;
-};
-
-/* DPLL parameter table */
-struct dpll_params {
- u32 m;
- u32 n;
- s8 m2;
- s8 m3;
- s8 m4;
- s8 m5;
- s8 m6;
- s8 m7;
+struct omap4_scrm_regs {
+ u32 revision; /* 0x0000 */
+ u32 pad00[63];
+ u32 clksetuptime; /* 0x0100 */
+ u32 pmicsetuptime; /* 0x0104 */
+ u32 pad01[2];
+ u32 altclksrc; /* 0x0110 */
+ u32 pad02[2];
+ u32 c2cclkm; /* 0x011c */
+ u32 pad03[56];
+ u32 extclkreq; /* 0x0200 */
+ u32 accclkreq; /* 0x0204 */
+ u32 pwrreq; /* 0x0208 */
+ u32 pad04[1];
+ u32 auxclkreq0; /* 0x0210 */
+ u32 auxclkreq1; /* 0x0214 */
+ u32 auxclkreq2; /* 0x0218 */
+ u32 auxclkreq3; /* 0x021c */
+ u32 auxclkreq4; /* 0x0220 */
+ u32 auxclkreq5; /* 0x0224 */
+ u32 pad05[3];
+ u32 c2cclkreq; /* 0x0234 */
+ u32 pad06[54];
+ u32 auxclk0; /* 0x0310 */
+ u32 auxclk1; /* 0x0314 */
+ u32 auxclk2; /* 0x0318 */
+ u32 auxclk3; /* 0x031c */
+ u32 auxclk4; /* 0x0320 */
+ u32 auxclk5; /* 0x0324 */
+ u32 pad07[54];
+ u32 rsttime_reg; /* 0x0400 */
+ u32 pad08[6];
+ u32 c2crstctrl; /* 0x041c */
+ u32 extpwronrstctrl; /* 0x0420 */
+ u32 pad09[59];
+ u32 extwarmrstst_reg; /* 0x0510 */
+ u32 apewarmrstst_reg; /* 0x0514 */
+ u32 pad10[1];
+ u32 c2cwarmrstst_reg; /* 0x051C */
};
-
-extern struct omap4_prcm_regs *const prcm;
-extern const u32 sys_clk_array[8];
-
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-u32 omap_ddr_clk(void);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 *const base, const struct dpll_params *params);
-u32 get_sys_clk_index(void);
-void enable_basic_clocks(void);
-void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_hw_auto,
- u32 *const *clk_modules_explicit_en,
- u8 wait_for_enable);
-const struct dpll_params *get_mpu_dpll_params(void);
-const struct dpll_params *get_core_dpll_params(void);
-const struct dpll_params *get_per_dpll_params(void);
-const struct dpll_params *get_iva_dpll_params(void);
-const struct dpll_params *get_usb_dpll_params(void);
-const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index 2114046e71..9c8ccb6c83 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -25,6 +25,8 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/*
* OMAP HSMMC register definitions
*/
@@ -33,142 +35,4 @@
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
-struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-};
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index d4b5076108..5f321fe6f0 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -132,34 +132,6 @@ struct s32ktimer {
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
-struct omap_sys_ctrl_regs {
- unsigned int pad1[129];
- unsigned int control_id_code; /* 0x4A002204 */
- unsigned int pad11[22];
- unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
- unsigned int pad2[24]; /* 0x4a002264 */
- unsigned int control_status; /* 0x4a0022c4 */
- unsigned int pad3[22]; /* 0x4a0022c8 */
- unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
- unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
- unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
- unsigned int pad4[260277];
- unsigned int control_pbiaslite; /* 0x4A100600 */
- unsigned int pad5[63];
- unsigned int control_efuse_1; /* 0x4A100700 */
- unsigned int control_efuse_2; /* 0x4A100704 */
-};
-
-struct control_lpddr2io_regs {
- unsigned int control_lpddr2io1_0;
- unsigned int control_lpddr2io1_1;
- unsigned int control_lpddr2io1_2;
- unsigned int control_lpddr2io1_3;
- unsigned int control_lpddr2io2_0;
- unsigned int control_lpddr2io2_1;
- unsigned int control_lpddr2io2_2;
- unsigned int control_lpddr2io2_3;
-};
#endif /* __ASSEMBLY__ */
/*
@@ -178,7 +150,11 @@ struct control_lpddr2io_regs {
#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* ROM code defines */
/* Boot device */
diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h
index cec84dc548..4e094f9c60 100644
--- a/arch/arm/include/asm/arch-omap4/spl.h
+++ b/arch/arm/include/asm/arch-omap4/spl.h
@@ -27,7 +27,7 @@
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 0xFF
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index b48f81dc33..d5f1868eee 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,7 +44,7 @@ void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
void setup_clocks_for_console(void);
void prcm_init(void);
-void bypass_dpll(u32 *const base);
+void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap4_ddr_clk(void);
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 5f1a7aa770..cfde374333 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -26,6 +26,7 @@
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
#include <common.h>
+#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
@@ -39,456 +40,6 @@
#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
-struct omap5_prcm_regs {
- /* cm1.ckgen */
- u32 cm_clksel_core; /* 4a004100 */
- u32 pad001[1]; /* 4a004104 */
- u32 cm_clksel_abe; /* 4a004108 */
- u32 pad002[1]; /* 4a00410c */
- u32 cm_dll_ctrl; /* 4a004110 */
- u32 pad003[3]; /* 4a004114 */
- u32 cm_clkmode_dpll_core; /* 4a004120 */
- u32 cm_idlest_dpll_core; /* 4a004124 */
- u32 cm_autoidle_dpll_core; /* 4a004128 */
- u32 cm_clksel_dpll_core; /* 4a00412c */
- u32 cm_div_m2_dpll_core; /* 4a004130 */
- u32 cm_div_m3_dpll_core; /* 4a004134 */
- u32 cm_div_h11_dpll_core; /* 4a004138 */
- u32 cm_div_h12_dpll_core; /* 4a00413c */
- u32 cm_div_h13_dpll_core; /* 4a004140 */
- u32 cm_div_h14_dpll_core; /* 4a004144 */
- u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
- u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
- u32 cm_emu_override_dpll_core; /* 4a004150 */
-
- u32 cm_div_h22_dpllcore; /* 4a004154 */
- u32 cm_div_h23_dpll_core; /* 4a004158 */
- u32 pad0041[1]; /* 4a00415c */
- u32 cm_clkmode_dpll_mpu; /* 4a004160 */
- u32 cm_idlest_dpll_mpu; /* 4a004164 */
- u32 cm_autoidle_dpll_mpu; /* 4a004168 */
- u32 cm_clksel_dpll_mpu; /* 4a00416c */
- u32 cm_div_m2_dpll_mpu; /* 4a004170 */
- u32 pad005[5]; /* 4a004174 */
- u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
- u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
- u32 pad006[3]; /* 4a004190 */
- u32 cm_bypclk_dpll_mpu; /* 4a00419c */
- u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
- u32 cm_idlest_dpll_iva; /* 4a0041a4 */
- u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
- u32 cm_clksel_dpll_iva; /* 4a0041ac */
- u32 pad007[2]; /* 4a0041b0 */
- u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
- u32 cm_div_h12_dpll_iva; /* 4a0041bc */
- u32 pad008[2]; /* 4a0041c0 */
- u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
- u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
- u32 pad009[3]; /* 4a0041d0 */
- u32 cm_bypclk_dpll_iva; /* 4a0041dc */
- u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
- u32 cm_idlest_dpll_abe; /* 4a0041e4 */
- u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
- u32 cm_clksel_dpll_abe; /* 4a0041ec */
- u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
- u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
- u32 pad010[4]; /* 4a0041f8 */
- u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
- u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
- u32 pad011[4]; /* 4a004210 */
- u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
- u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
- u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
- u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
- u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
- u32 pad012[1]; /* 4a004234 */
- u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
- u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
- u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
- u32 pad013[1]; /* 4a004244 */
- u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
- u32 pad014[5]; /* 4a00424c */
- u32 cm_shadow_freq_config1; /* 4a004260 */
- u32 pad0141[47]; /* 4a004264 */
- u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
-
-
- /* cm1.dsp */
- u32 pad015[55]; /* 4a004324 */
- u32 cm_dsp_clkstctrl; /* 4a004400 */
- u32 pad016[7]; /* 4a004404 */
- u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
-
- /* cm1.abe */
- u32 pad017[55]; /* 4a004424 */
- u32 cm1_abe_clkstctrl; /* 4a004500 */
- u32 pad018[7]; /* 4a004504 */
- u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
- u32 pad019[1]; /* 4a004524 */
- u32 cm1_abe_aess_clkctrl; /* 4a004528 */
- u32 pad020[1]; /* 4a00452c */
- u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
- u32 pad021[1]; /* 4a004534 */
- u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
- u32 pad022[1]; /* 4a00453c */
- u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
- u32 pad023[1]; /* 4a004544 */
- u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
- u32 pad024[1]; /* 4a00454c */
- u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
- u32 pad025[1]; /* 4a004554 */
- u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
- u32 pad026[1]; /* 4a00455c */
- u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
- u32 pad027[1]; /* 4a004564 */
- u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
- u32 pad028[1]; /* 4a00456c */
- u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
- u32 pad029[1]; /* 4a004574 */
- u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
- u32 pad030[1]; /* 4a00457c */
- u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
- u32 pad031[1]; /* 4a004584 */
- u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
-
- /* cm2.ckgen */
- u32 pad032[3805]; /* 4a00458c */
- u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
- u32 cm_clksel_usb_60mhz; /* 4a008104 */
- u32 cm_scale_fclk; /* 4a008108 */
- u32 pad033[1]; /* 4a00810c */
- u32 cm_core_dvfs_perf1; /* 4a008110 */
- u32 cm_core_dvfs_perf2; /* 4a008114 */
- u32 cm_core_dvfs_perf3; /* 4a008118 */
- u32 cm_core_dvfs_perf4; /* 4a00811c */
- u32 pad034[1]; /* 4a008120 */
- u32 cm_core_dvfs_current; /* 4a008124 */
- u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
- u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
- u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
- u32 pad035[1]; /* 4a008134 */
- u32 cm_iva_dvfs_current; /* 4a008138 */
- u32 pad036[1]; /* 4a00813c */
- u32 cm_clkmode_dpll_per; /* 4a008140 */
- u32 cm_idlest_dpll_per; /* 4a008144 */
- u32 cm_autoidle_dpll_per; /* 4a008148 */
- u32 cm_clksel_dpll_per; /* 4a00814c */
- u32 cm_div_m2_dpll_per; /* 4a008150 */
- u32 cm_div_m3_dpll_per; /* 4a008154 */
- u32 cm_div_h11_dpll_per; /* 4a008158 */
- u32 cm_div_h12_dpll_per; /* 4a00815c */
- u32 pad0361[1]; /* 4a008160 */
- u32 cm_div_h14_dpll_per; /* 4a008164 */
- u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
- u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
- u32 cm_emu_override_dpll_per; /* 4a008170 */
- u32 pad037[3]; /* 4a008174 */
- u32 cm_clkmode_dpll_usb; /* 4a008180 */
- u32 cm_idlest_dpll_usb; /* 4a008184 */
- u32 cm_autoidle_dpll_usb; /* 4a008188 */
- u32 cm_clksel_dpll_usb; /* 4a00818c */
- u32 cm_div_m2_dpll_usb; /* 4a008190 */
- u32 pad038[5]; /* 4a008194 */
- u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
- u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
- u32 pad039[1]; /* 4a0081b0 */
- u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
- u32 pad040[2]; /* 4a0081b8 */
- u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
- u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
- u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
- u32 cm_clksel_dpll_unipro; /* 4a0081cc */
- u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
- u32 pad041[5]; /* 4a0081d4 */
- u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
- u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
-
- /* cm2.core */
- u32 pad0411[324]; /* 4a0081f0 */
- u32 cm_l3_1_clkstctrl; /* 4a008700 */
- u32 pad042[1]; /* 4a008704 */
- u32 cm_l3_1_dynamicdep; /* 4a008708 */
- u32 pad043[5]; /* 4a00870c */
- u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
- u32 pad044[55]; /* 4a008724 */
- u32 cm_l3_2_clkstctrl; /* 4a008800 */
- u32 pad045[1]; /* 4a008804 */
- u32 cm_l3_2_dynamicdep; /* 4a008808 */
- u32 pad046[5]; /* 4a00880c */
- u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
- u32 pad047[1]; /* 4a008824 */
- u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
- u32 pad048[1]; /* 4a00882c */
- u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
- u32 pad049[51]; /* 4a008834 */
- u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
- u32 cm_mpu_m3_staticdep; /* 4a008904 */
- u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
- u32 pad050[5]; /* 4a00890c */
- u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
- u32 pad051[55]; /* 4a008924 */
- u32 cm_sdma_clkstctrl; /* 4a008a00 */
- u32 cm_sdma_staticdep; /* 4a008a04 */
- u32 cm_sdma_dynamicdep; /* 4a008a08 */
- u32 pad052[5]; /* 4a008a0c */
- u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
- u32 pad053[55]; /* 4a008a24 */
- u32 cm_memif_clkstctrl; /* 4a008b00 */
- u32 pad054[7]; /* 4a008b04 */
- u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
- u32 pad055[1]; /* 4a008b24 */
- u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
- u32 pad056[1]; /* 4a008b2c */
- u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
- u32 pad057[1]; /* 4a008b34 */
- u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
- u32 pad058[1]; /* 4a008b3c */
- u32 cm_memif_dll_clkctrl; /* 4a008b40 */
- u32 pad059[3]; /* 4a008b44 */
- u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
- u32 pad060[1]; /* 4a008b54 */
- u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
- u32 pad061[1]; /* 4a008b5c */
- u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
- u32 pad062[39]; /* 4a008b64 */
- u32 cm_c2c_clkstctrl; /* 4a008c00 */
- u32 cm_c2c_staticdep; /* 4a008c04 */
- u32 cm_c2c_dynamicdep; /* 4a008c08 */
- u32 pad063[5]; /* 4a008c0c */
- u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
- u32 pad064[1]; /* 4a008c24 */
- u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
- u32 pad065[1]; /* 4a008c2c */
- u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
- u32 pad066[51]; /* 4a008c34 */
- u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
- u32 pad067[1]; /* 4a008d04 */
- u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
- u32 pad068[5]; /* 4a008d0c */
- u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
- u32 pad069[1]; /* 4a008d24 */
- u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
- u32 pad070[1]; /* 4a008d2c */
- u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
- u32 pad071[1]; /* 4a008d34 */
- u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
- u32 pad072[49]; /* 4a008d3c */
- u32 cm_l3instr_clkstctrl; /* 4a008e00 */
- u32 pad073[7]; /* 4a008e04 */
- u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
- u32 pad074[1]; /* 4a008e24 */
- u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
- u32 pad075[5]; /* 4a008e2c */
- u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
-
-
- /* cm2.ivahd */
- u32 pad076[47]; /* 4a008e44 */
- u32 cm_ivahd_clkstctrl; /* 4a008f00 */
- u32 pad077[7]; /* 4a008f04 */
- u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
- u32 pad078[1]; /* 4a008f24 */
- u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
-
- /* cm2.cam */
- u32 pad079[53]; /* 4a008f2c */
- u32 cm_cam_clkstctrl; /* 4a009000 */
- u32 pad080[7]; /* 4a009004 */
- u32 cm_cam_iss_clkctrl; /* 4a009020 */
- u32 pad081[1]; /* 4a009024 */
- u32 cm_cam_fdif_clkctrl; /* 4a009028 */
-
- /* cm2.dss */
- u32 pad082[53]; /* 4a00902c */
- u32 cm_dss_clkstctrl; /* 4a009100 */
- u32 pad083[7]; /* 4a009104 */
- u32 cm_dss_dss_clkctrl; /* 4a009120 */
-
- /* cm2.sgx */
- u32 pad084[55]; /* 4a009124 */
- u32 cm_sgx_clkstctrl; /* 4a009200 */
- u32 pad085[7]; /* 4a009204 */
- u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
-
- /* cm2.l3init */
- u32 pad086[55]; /* 4a009224 */
- u32 cm_l3init_clkstctrl; /* 4a009300 */
-
- /* cm2.l3init */
- u32 pad087[9]; /* 4a009304 */
- u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
- u32 pad088[1]; /* 4a00932c */
- u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
- u32 pad089[1]; /* 4a009334 */
- u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
- u32 pad090[7]; /* 4a00933c */
- u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
- u32 pad091[1]; /* 4a00935c */
- u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
- u32 pad092[1]; /* 4a009364 */
- u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
- u32 pad093[3]; /* 4a00936c */
- u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
- u32 pad094[21]; /* 4a00937c */
- u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
- u32 pad095[3]; /* 4a0093d4 */
- u32 cm_l3init_ocp2scp1_clkctrl;
-
- /* cm2.l4per */
- u32 pad096[7]; /* 4a0093e4 */
- u32 cm_l4per_clkstctrl; /* 4a009400 */
- u32 pad097[1]; /* 4a009404 */
- u32 cm_l4per_dynamicdep; /* 4a009408 */
- u32 pad098[5]; /* 4a00940c */
- u32 cm_l4per_adc_clkctrl; /* 4a009420 */
- u32 pad100[1]; /* 4a009424 */
- u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
- u32 pad101[1]; /* 4a00942c */
- u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
- u32 pad102[1]; /* 4a009434 */
- u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
- u32 pad103[1]; /* 4a00943c */
- u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
- u32 pad104[1]; /* 4a009444 */
- u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
- u32 pad105[1]; /* 4a00944c */
- u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
- u32 pad106[1]; /* 4a009454 */
- u32 cm_l4per_elm_clkctrl; /* 4a009458 */
- u32 pad107[1]; /* 4a00945c */
- u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
- u32 pad108[1]; /* 4a009464 */
- u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
- u32 pad109[1]; /* 4a00946c */
- u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
- u32 pad110[1]; /* 4a009474 */
- u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
- u32 pad111[1]; /* 4a00947c */
- u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
- u32 pad112[1]; /* 4a009484 */
- u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
- u32 pad113[1]; /* 4a00948c */
- u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
- u32 pad114[1]; /* 4a009494 */
- u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
- u32 pad115[1]; /* 4a00949c */
- u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
- u32 pad116[1]; /* 4a0094a4 */
- u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
- u32 pad117[1]; /* 4a0094ac */
- u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
- u32 pad118[1]; /* 4a0094b4 */
- u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
- u32 pad119[1]; /* 4a0094bc */
- u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
- u32 pad1191[3]; /* 4a0094c4 */
- u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
- u32 pad120[1]; /* 4a0094d4 */
- u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
- u32 pad121[3]; /* 4a0094dc */
- u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
- u32 pad123[1]; /* 4a0094ec */
- u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
- u32 pad124[1]; /* 4a0094f4 */
- u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
- u32 pad125[1]; /* 4a0094fc */
- u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
- u32 pad126[1]; /* 4a009504 */
- u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
- u32 pad127[1]; /* 4a00950c */
- u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
- u32 pad1271[1]; /* 4a009514 */
- u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
- u32 pad1272[1]; /* 4a00951c */
- u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
- u32 pad128[1]; /* 4a009524 */
- u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
- u32 pad129[1]; /* 4a00952c */
- u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
- u32 pad130[1]; /* 4a009534 */
- u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
- u32 pad131[1]; /* 4a00953c */
- u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
- u32 pad132[1]; /* 4a009544 */
- u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
- u32 pad133[1]; /* 4a00954c */
- u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
- u32 pad134[1]; /* 4a009554 */
- u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
- u32 pad135[1]; /* 4a00955c */
- u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
- u32 pad136[1]; /* 4a009564 */
- u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
- u32 pad1371[1]; /* 4a00956c */
- u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
- u32 pad1372[1]; /* 4a009574 */
- u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
- u32 pad1374[1]; /* 4a00957c */
- u32 cm_l4sec_clkstctrl; /* 4a009580 */
- u32 cm_l4sec_staticdep; /* 4a009584 */
- u32 cm_l4sec_dynamicdep; /* 4a009588 */
- u32 pad138[5]; /* 4a00958c */
- u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
- u32 pad139[1]; /* 4a0095a4 */
- u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
- u32 pad140[1]; /* 4a0095ac */
- u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
- u32 pad141[1]; /* 4a0095b4 */
- u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
- u32 pad142[1]; /* 4a0095bc */
- u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
- u32 pad143[1]; /* 4a0095c4 */
- u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
- u32 pad144[3]; /* 4a0095cc */
- u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
- u32 pad145[3660425]; /* 4a0095dc */
-
- /* l4 wkup regs */
- u32 pad201[6211]; /* 4ae00000 */
- u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
- u32 cm_sys_clksel; /* 4ae06110 */
- u32 pad202[1467]; /* 4ae06114 */
- u32 cm_wkup_clkstctrl; /* 4ae07800 */
- u32 pad203[7]; /* 4ae07804 */
- u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
- u32 pad204; /* 4ae07824 */
- u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
- u32 pad205; /* 4ae0782c */
- u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
- u32 pad206; /* 4ae07834 */
- u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
- u32 pad207; /* 4ae0783c */
- u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
- u32 pad208; /* 4ae07844 */
- u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
- u32 pad209; /* 4ae0784c */
- u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
- u32 pad210; /* 4ae07854 */
- u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
- u32 pad211; /* 4ae0785c */
- u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
- u32 pad212[5]; /* 4ae07864 */
- u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
- u32 pad213; /* 4ae0787c */
- u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
- u32 pad214; /* 4ae07884 */
- u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
- u32 pad215[1]; /* 4ae0788c */
- u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */
- u32 pad216[195];
- u32 prm_vc_val_bypass; /* 4ae07ba0 */
- u32 pad217[4];
- u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
- u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
- u32 pad218[2];
- u32 prm_sldo_core_setup; /* 4ae07bc4 */
- u32 prm_sldo_core_ctrl; /* 4ae07bc8 */
- u32 prm_sldo_mpu_setup; /* 4ae07bcc */
- u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */
- u32 prm_sldo_mm_setup; /* 4ae07bd4 */
- u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */
-};
-
/* DPLL register offsets */
#define CM_CLKMODE_DPLL 0
#define CM_IDLEST_DPLL 0x4
@@ -625,9 +176,9 @@ struct omap5_prcm_regs {
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
/* CM_WKUPAON_SCRM_CLKCTRL */
#define OPTFCLKEN_SCRM_PER_SHIFT 9
@@ -635,6 +186,10 @@ struct omap5_prcm_regs {
#define OPTFCLKEN_SCRM_CORE_SHIFT 8
#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
+/* CM_COREAON_IO_SRCOMP_CLKCTRL */
+#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
+#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
+
/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
@@ -650,12 +205,25 @@ struct omap5_prcm_regs {
#define SMPS_REG_ADDR_8_CORE 0x37
/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
-#define VDD_MPU 1000
-#define VDD_MM 1000
+/* ES1.0 settings */
+#define VDD_MPU 1040
+#define VDD_MM 1040
#define VDD_CORE 1040
-#define VDD_MPU_5432 1150
-#define VDD_MM_5432 1150
-#define VDD_CORE_5432 1150
+
+#define VDD_MPU_LOW 890
+#define VDD_MM_LOW 890
+#define VDD_CORE_LOW 890
+
+/* ES2.0 settings */
+#define VDD_MPU_ES2 1060
+#define VDD_MM_ES2 1025
+#define VDD_CORE_ES2 1040
+
+#define VDD_MPU_ES2_HIGH 1250
+#define VDD_MM_ES2_OD 1120
+
+#define VDD_MPU_ES2_LOW 880
+#define VDD_MM_ES2_LOW 880
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
@@ -683,59 +251,4 @@ struct omap5_prcm_regs {
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
-#define NUM_SYS_CLKS 7
-
-struct dpll_regs {
- u32 cm_clkmode_dpll;
- u32 cm_idlest_dpll;
- u32 cm_autoidle_dpll;
- u32 cm_clksel_dpll;
- u32 cm_div_m2_dpll;
- u32 cm_div_m3_dpll;
- u32 cm_div_h11_dpll;
- u32 cm_div_h12_dpll;
- u32 cm_div_h13_dpll;
- u32 cm_div_h14_dpll;
- u32 reserved[3];
- u32 cm_div_h22_dpll;
- u32 cm_div_h23_dpll;
-};
-
-/* DPLL parameter table */
-struct dpll_params {
- u32 m;
- u32 n;
- s8 m2;
- s8 m3;
- s8 h11;
- s8 h12;
- s8 h13;
- s8 h14;
- s8 h22;
- s8 h23;
-};
-
-extern struct omap5_prcm_regs *const prcm;
-extern const u32 sys_clk_array[8];
-
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-u32 omap_ddr_clk(void);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 *const base, const struct dpll_params *params);
-u32 get_sys_clk_index(void);
-void enable_basic_clocks(void);
-void enable_non_essential_clocks(void);
-void enable_basic_uboot_clocks(void);
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_hw_auto,
- u32 *const *clk_modules_explicit_en,
- u8 wait_for_enable);
-const struct dpll_params *get_mpu_dpll_params(void);
-const struct dpll_params *get_core_dpll_params(void);
-const struct dpll_params *get_per_dpll_params(void);
-const struct dpll_params *get_iva_dpll_params(void);
-const struct dpll_params *get_usb_dpll_params(void);
-const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
index 2114046e71..9c8ccb6c83 100644
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -25,6 +25,8 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/*
* OMAP HSMMC register definitions
*/
@@ -33,142 +35,4 @@
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
-struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-};
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
new file mode 100644
index 0000000000..55e9de6041
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated
+ *
+ * Nishant Kamat <nskamat@ti.com>
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_DRA7XX_H_
+#define _MUX_DRA7XX_H_
+
+#include <asm/types.h>
+
+#define IEN (1 << 18)
+#define IDIS (0 << 18)
+
+#define PTU (3 << 16)
+#define PTD (1 << 16)
+#define PEN (1 << 16)
+#define PDIS (0 << 16)
+
+#define WKEN (1 << 24)
+#define WKDIS (0 << 24)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+#define M8 8
+#define M9 9
+#define M10 10
+#define M11 11
+#define M12 12
+#define M13 13
+#define M14 14
+#define M15 15
+
+#define SAFE_MODE M15
+
+#define GPMC_AD0 0x000
+#define GPMC_AD1 0x004
+#define GPMC_AD2 0x008
+#define GPMC_AD3 0x00C
+#define GPMC_AD4 0x010
+#define GPMC_AD5 0x014
+#define GPMC_AD6 0x018
+#define GPMC_AD7 0x01C
+#define GPMC_AD8 0x020
+#define GPMC_AD9 0x024
+#define GPMC_AD10 0x028
+#define GPMC_AD11 0x02C
+#define GPMC_AD12 0x030
+#define GPMC_AD13 0x034
+#define GPMC_AD14 0x038
+#define GPMC_AD15 0x03C
+#define GPMC_A0 0x040
+#define GPMC_A1 0x044
+#define GPMC_A2 0x048
+#define GPMC_A3 0x04C
+#define GPMC_A4 0x050
+#define GPMC_A5 0x054
+#define GPMC_A6 0x058
+#define GPMC_A7 0x05C
+#define GPMC_A8 0x060
+#define GPMC_A9 0x064
+#define GPMC_A10 0x068
+#define GPMC_A11 0x06C
+#define GPMC_A12 0x070
+#define GPMC_A13 0x074
+#define GPMC_A14 0x078
+#define GPMC_A15 0x07C
+#define GPMC_A16 0x080
+#define GPMC_A17 0x084
+#define GPMC_A18 0x088
+#define GPMC_A19 0x08C
+#define GPMC_A20 0x090
+#define GPMC_A21 0x094
+#define GPMC_A22 0x098
+#define GPMC_A23 0x09C
+#define GPMC_A24 0x0A0
+#define GPMC_A25 0x0A4
+#define GPMC_A26 0x0A8
+#define GPMC_A27 0x0AC
+#define GPMC_CS1 0x0B0
+#define GPMC_CS0 0x0B4
+#define GPMC_CS2 0x0B8
+#define GPMC_CS3 0x0BC
+#define GPMC_CLK 0x0C0
+#define GPMC_ADVN_ALE 0x0C4
+#define GPMC_OEN_REN 0x0C8
+#define GPMC_WEN 0x0CC
+#define GPMC_BEN0 0x0D0
+#define GPMC_BEN1 0x0D4
+#define GPMC_WAIT0 0x0D8
+#define VIN1A_CLK0 0x0DC
+#define VIN1B_CLK1 0x0E0
+#define VIN1A_DE0 0x0E4
+#define VIN1A_FLD0 0x0E8
+#define VIN1A_HSYNC0 0x0EC
+#define VIN1A_VSYNC0 0x0F0
+#define VIN1A_D0 0x0F4
+#define VIN1A_D1 0x0F8
+#define VIN1A_D2 0x0FC
+#define VIN1A_D3 0x100
+#define VIN1A_D4 0x104
+#define VIN1A_D5 0x108
+#define VIN1A_D6 0x10C
+#define VIN1A_D7 0x110
+#define VIN1A_D8 0x114
+#define VIN1A_D9 0x118
+#define VIN1A_D10 0x11C
+#define VIN1A_D11 0x120
+#define VIN1A_D12 0x124
+#define VIN1A_D13 0x128
+#define VIN1A_D14 0x12C
+#define VIN1A_D15 0x130
+#define VIN1A_D16 0x134
+#define VIN1A_D17 0x138
+#define VIN1A_D18 0x13C
+#define VIN1A_D19 0x140
+#define VIN1A_D20 0x144
+#define VIN1A_D21 0x148
+#define VIN1A_D22 0x14C
+#define VIN1A_D23 0x150
+#define VIN2A_CLK0 0x154
+#define VIN2A_DE0 0x158
+#define VIN2A_FLD0 0x15C
+#define VIN2A_HSYNC0 0x160
+#define VIN2A_VSYNC0 0x164
+#define VIN2A_D0 0x168
+#define VIN2A_D1 0x16C
+#define VIN2A_D2 0x170
+#define VIN2A_D3 0x174
+#define VIN2A_D4 0x178
+#define VIN2A_D5 0x17C
+#define VIN2A_D6 0x180
+#define VIN2A_D7 0x184
+#define VIN2A_D8 0x188
+#define VIN2A_D9 0x18C
+#define VIN2A_D10 0x190
+#define VIN2A_D11 0x194
+#define VIN2A_D12 0x198
+#define VIN2A_D13 0x19C
+#define VIN2A_D14 0x1A0
+#define VIN2A_D15 0x1A4
+#define VIN2A_D16 0x1A8
+#define VIN2A_D17 0x1AC
+#define VIN2A_D18 0x1B0
+#define VIN2A_D19 0x1B4
+#define VIN2A_D20 0x1B8
+#define VIN2A_D21 0x1BC
+#define VIN2A_D22 0x1C0
+#define VIN2A_D23 0x1C4
+#define VOUT1_CLK 0x1C8
+#define VOUT1_DE 0x1CC
+#define VOUT1_FLD 0x1D0
+#define VOUT1_HSYNC 0x1D4
+#define VOUT1_VSYNC 0x1D8
+#define VOUT1_D0 0x1DC
+#define VOUT1_D1 0x1E0
+#define VOUT1_D2 0x1E4
+#define VOUT1_D3 0x1E8
+#define VOUT1_D4 0x1EC
+#define VOUT1_D5 0x1F0
+#define VOUT1_D6 0x1F4
+#define VOUT1_D7 0x1F8
+#define VOUT1_D8 0x1FC
+#define VOUT1_D9 0x200
+#define VOUT1_D10 0x204
+#define VOUT1_D11 0x208
+#define VOUT1_D12 0x20C
+#define VOUT1_D13 0x210
+#define VOUT1_D14 0x214
+#define VOUT1_D15 0x218
+#define VOUT1_D16 0x21C
+#define VOUT1_D17 0x220
+#define VOUT1_D18 0x224
+#define VOUT1_D19 0x228
+#define VOUT1_D20 0x22C
+#define VOUT1_D21 0x230
+#define VOUT1_D22 0x234
+#define VOUT1_D23 0x238
+#define MDIO_MCLK 0x23C
+#define MDIO_D 0x240
+#define RMII_MHZ_50_CLK 0x244
+#define UART3_RXD 0x248
+#define UART3_TXD 0x24C
+#define RGMII0_TXC 0x250
+#define RGMII0_TXCTL 0x254
+#define RGMII0_TXD3 0x258
+#define RGMII0_TXD2 0x25C
+#define RGMII0_TXD1 0x260
+#define RGMII0_TXD0 0x264
+#define RGMII0_RXC 0x268
+#define RGMII0_RXCTL 0x26C
+#define RGMII0_RXD3 0x270
+#define RGMII0_RXD2 0x274
+#define RGMII0_RXD1 0x278
+#define RGMII0_RXD0 0x27C
+#define USB1_DRVVBUS 0x280
+#define USB2_DRVVBUS 0x284
+#define GPIO6_14 0x288
+#define GPIO6_15 0x28C
+#define GPIO6_16 0x290
+#define XREF_CLK0 0x294
+#define XREF_CLK1 0x298
+#define XREF_CLK2 0x29C
+#define XREF_CLK3 0x2A0
+#define MCASP1_ACLKX 0x2A4
+#define MCASP1_FSX 0x2A8
+#define MCASP1_ACLKR 0x2AC
+#define MCASP1_FSR 0x2B0
+#define MCASP1_AXR0 0x2B4
+#define MCASP1_AXR1 0x2B8
+#define MCASP1_AXR2 0x2BC
+#define MCASP1_AXR3 0x2C0
+#define MCASP1_AXR4 0x2C4
+#define MCASP1_AXR5 0x2C8
+#define MCASP1_AXR6 0x2CC
+#define MCASP1_AXR7 0x2D0
+#define MCASP1_AXR8 0x2D4
+#define MCASP1_AXR9 0x2D8
+#define MCASP1_AXR10 0x2DC
+#define MCASP1_AXR11 0x2E0
+#define MCASP1_AXR12 0x2E4
+#define MCASP1_AXR13 0x2E8
+#define MCASP1_AXR14 0x2EC
+#define MCASP1_AXR15 0x2F0
+#define MCASP2_ACLKX 0x2F4
+#define MCASP2_FSX 0x2F8
+#define MCASP2_ACLKR 0x2FC
+#define MCASP2_FSR 0x300
+#define MCASP2_AXR0 0x304
+#define MCASP2_AXR1 0x308
+#define MCASP2_AXR2 0x30C
+#define MCASP2_AXR3 0x310
+#define MCASP2_AXR4 0x314
+#define MCASP2_AXR5 0x318
+#define MCASP2_AXR6 0x31C
+#define MCASP2_AXR7 0x320
+#define MCASP3_ACLKX 0x324
+#define MCASP3_FSX 0x328
+#define MCASP3_AXR0 0x32C
+#define MCASP3_AXR1 0x330
+#define MCASP4_ACLKX 0x334
+#define MCASP4_FSX 0x338
+#define MCASP4_AXR0 0x33C
+#define MCASP4_AXR1 0x340
+#define MCASP5_ACLKX 0x344
+#define MCASP5_FSX 0x348
+#define MCASP5_AXR0 0x34C
+#define MCASP5_AXR1 0x350
+#define MMC1_CLK 0x354
+#define MMC1_CMD 0x358
+#define MMC1_DAT0 0x35C
+#define MMC1_DAT1 0x360
+#define MMC1_DAT2 0x364
+#define MMC1_DAT3 0x368
+#define MMC1_SDCD 0x36C
+#define MMC1_SDWP 0x370
+#define GPIO6_10 0x374
+#define GPIO6_11 0x378
+#define MMC3_CLK 0x37C
+#define MMC3_CMD 0x380
+#define MMC3_DAT0 0x384
+#define MMC3_DAT1 0x388
+#define MMC3_DAT2 0x38C
+#define MMC3_DAT3 0x390
+#define MMC3_DAT4 0x394
+#define MMC3_DAT5 0x398
+#define MMC3_DAT6 0x39C
+#define MMC3_DAT7 0x3A0
+#define SPI1_SCLK 0x3A4
+#define SPI1_D1 0x3A8
+#define SPI1_D0 0x3AC
+#define SPI1_CS0 0x3B0
+#define SPI1_CS1 0x3B4
+#define SPI1_CS2 0x3B8
+#define SPI1_CS3 0x3BC
+#define SPI2_SCLK 0x3C0
+#define SPI2_D1 0x3C4
+#define SPI2_D0 0x3C8
+#define SPI2_CS0 0x3CC
+#define DCAN1_TX 0x3D0
+#define DCAN1_RX 0x3D4
+#define DCAN2_TX 0x3D8
+#define DCAN2_RX 0x3DC
+#define UART1_RXD 0x3E0
+#define UART1_TXD 0x3E4
+#define UART1_CTSN 0x3E8
+#define UART1_RTSN 0x3EC
+#define UART2_RXD 0x3F0
+#define UART2_TXD 0x3F4
+#define UART2_CTSN 0x3F8
+#define UART2_RTSN 0x3FC
+#define I2C1_SDA 0x400
+#define I2C1_SCL 0x404
+#define I2C2_SDA 0x408
+#define I2C2_SCL 0x40C
+#define I2C3_SDA 0x410
+#define I2C3_SCL 0x414
+#define WAKEUP0 0x418
+#define WAKEUP1 0x41C
+#define WAKEUP2 0x420
+#define WAKEUP3 0x424
+#define ON_OFF 0x428
+#define RTC_PORZ 0x42C
+#define TMS 0x430
+#define TDI 0x434
+#define TDO 0x438
+#define TCLK 0x43C
+#define TRSTN 0x440
+#define RTCK 0x444
+#define EMU0 0x448
+#define EMU1 0x44C
+#define EMU2 0x450
+#define EMU3 0x454
+#define EMU4 0x458
+#define RESETN 0x45C
+#define NMIN 0x460
+#define RSTOUTN 0x464
+
+#endif /* _MUX_DRA7XX_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
index 4a6ed8b455..34b0dbd063 100644
--- a/arch/arm/include/asm/arch-omap5/mux_omap5.h
+++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h
@@ -28,14 +28,6 @@
#include <asm/types.h>
-struct pad_conf_entry {
-
- u16 offset;
-
- u16 val;
-
-};
-
#ifdef CONFIG_OFF_PADCONF
#define OFF_PD (1 << 12)
#define OFF_PU (3 << 12)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 9dce49ac4b..b632635d3e 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -57,7 +57,10 @@
/* To be verified */
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
+#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
+#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
+#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
@@ -131,87 +134,6 @@ struct s32ktimer {
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
-struct omap_sys_ctrl_regs {
- u32 pad0[77]; /* 0x4A002000 */
- u32 control_status; /* 0x4A002134 */
- u32 pad1[794]; /* 0x4A002138 */
- u32 control_paconf_global; /* 0x4A002DA0 */
- u32 control_paconf_mode; /* 0x4A002DA4 */
- u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
- u32 control_smart1io_padconf_1; /* 0x4A002DAC */
- u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
- u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
- u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
- u32 control_smart2io_padconf_2; /* 0x4A002DBC */
- u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
- u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
- u32 pad2[14];
- u32 control_pbias; /* 0x4A002E00 */
- u32 control_i2c_0; /* 0x4A002E04 */
- u32 control_camera_rx; /* 0x4A002E08 */
- u32 control_hdmi_tx_phy; /* 0x4A002E0C */
- u32 control_uniportm; /* 0x4A002E10 */
- u32 control_dsiphy; /* 0x4A002E14 */
- u32 control_mcbsplp; /* 0x4A002E18 */
- u32 control_usb2phycore; /* 0x4A002E1C */
- u32 control_hdmi_1; /*0x4A002E20*/
- u32 control_hsi; /*0x4A002E24*/
- u32 pad3[2];
- u32 control_ddr3ch1_0; /*0x4A002E30*/
- u32 control_ddr3ch2_0; /*0x4A002E34*/
- u32 control_ddrch1_0; /*0x4A002E38*/
- u32 control_ddrch1_1; /*0x4A002E3C*/
- u32 control_ddrch2_0; /*0x4A002E40*/
- u32 control_ddrch2_1; /*0x4A002E44*/
- u32 control_lpddr2ch1_0; /*0x4A002E48*/
- u32 control_lpddr2ch1_1; /*0x4A002E4C*/
- u32 control_ddrio_0; /*0x4A002E50*/
- u32 control_ddrio_1; /*0x4A002E54*/
- u32 control_ddrio_2; /*0x4A002E58*/
- u32 control_hyst_1; /*0x4A002E5C*/
- u32 control_usbb_hsic_control; /*0x4A002E60*/
- u32 control_c2c; /*0x4A002E64*/
- u32 control_core_control_spare_rw; /*0x4A002E68*/
- u32 control_core_control_spare_r; /*0x4A002E6C*/
- u32 control_core_control_spare_r_c0; /*0x4A002E70*/
- u32 control_srcomp_north_side; /*0x4A002E74*/
- u32 control_srcomp_south_side; /*0x4A002E78*/
- u32 control_srcomp_east_side; /*0x4A002E7C*/
- u32 control_srcomp_west_side; /*0x4A002E80*/
- u32 control_srcomp_code_latch; /*0x4A002E84*/
- u32 pad4[3679394];
- u32 control_port_emif1_sdram_config; /*0x4AE0C110*/
- u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/
- u32 control_port_emif2_sdram_config; /*0x4AE0C118*/
- u32 pad5[10];
- u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */
- u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */
- u32 pad6[789];
- u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
- u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
- u32 control_padconf_mode; /* 0x4AE0CDA8 */
- u32 control_xtal_oscillator; /* 0x4AE0CDAC */
- u32 control_i2c_2; /* 0x4AE0CDB0 */
- u32 control_ckobuffer; /* 0x4AE0CDB4 */
- u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
- u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
- u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
- u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
- u32 control_efuse_1; /* 0x4AE0CDC8 */
- u32 control_efuse_2; /* 0x4AE0CDCC */
- u32 control_efuse_3; /* 0x4AE0CDD0 */
- u32 control_efuse_4; /* 0x4AE0CDD4 */
- u32 control_efuse_5; /* 0x4AE0CDD8 */
- u32 control_efuse_6; /* 0x4AE0CDDC */
- u32 control_efuse_7; /* 0x4AE0CDE0 */
- u32 control_efuse_8; /* 0x4AE0CDE4 */
- u32 control_efuse_9; /* 0x4AE0CDE8 */
- u32 control_efuse_10; /* 0x4AE0CDEC */
- u32 control_efuse_11; /* 0x4AE0CDF0 */
- u32 control_efuse_12; /* 0x4AE0CDF4 */
- u32 control_efuse_13; /* 0x4AE0CDF8 */
-};
-
/* Output impedance control */
#define ds_120_ohm 0x0
#define ds_60_ohm 0x1
@@ -247,6 +169,12 @@ struct omap_sys_ctrl_regs {
#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
#define EFUSE_1 0x45145100
#define EFUSE_2 0x45145100
#define EFUSE_3 0x45145100
@@ -271,7 +199,11 @@ struct omap_sys_ctrl_regs {
#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
@@ -298,7 +230,26 @@ struct omap_sys_ctrl_regs {
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
+/* CONTROL_SRCOMP_XXX_SIDE */
+#define OVERRIDE_XS_SHIFT 30
+#define OVERRIDE_XS_MASK (1 << 30)
+#define SRCODE_READ_XS_SHIFT 12
+#define SRCODE_READ_XS_MASK (0xff << 12)
+#define PWRDWN_XS_SHIFT 11
+#define PWRDWN_XS_MASK (1 << 11)
+#define DIVIDE_FACTOR_XS_SHIFT 4
+#define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
+#define MULTIPLY_FACTOR_XS_SHIFT 1
+#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
+#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
+#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
+
#ifndef __ASSEMBLY__
+struct srcomp_params {
+ s8 divide_factor;
+ s8 multiply_factor;
+};
+
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
@@ -306,5 +257,15 @@ struct omap_boot_parameters {
unsigned char reset_reason;
unsigned char ch_flags;
};
+
+struct ctrl_ioregs {
+ u32 ctrl_ddrch;
+ u32 ctrl_lpddr2ch;
+ u32 ctrl_ddr3ch;
+ u32 ctrl_ddrio_0;
+ u32 ctrl_ddrio_1;
+ u32 ctrl_ddrio_2;
+ u32 ctrl_emif_sdram_config_ext;
+};
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
index d125c61f4c..323cd63551 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -27,7 +27,7 @@
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 72e9df7881..e66ab44341 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -25,9 +25,13 @@
#include <asm/io.h>
#include <asm/arch/clocks.h>
#include <asm/omap_common.h>
-#include <asm/arch/mux_omap5.h>
#include <asm/arch/clocks.h>
+struct pad_conf_entry {
+ u32 offset;
+ u32 val;
+};
+
struct omap_sysinfo {
char *board_string;
};
@@ -44,7 +48,7 @@ u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void setup_clocks_for_console(void);
void prcm_init(void);
-void bypass_dpll(u32 *const base);
+void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap5_ddr_clk(void);
@@ -58,6 +62,8 @@ void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
+void get_ioregs(const struct ctrl_ioregs **regs);
+void srcomp_enable(void);
/*
* This is used to verify if the configuration header
diff --git a/arch/arm/include/asm/arch-tegra/mmc.h b/arch/arm/include/asm/arch-tegra/mmc.h
index 5c95047998..71ad407511 100644
--- a/arch/arm/include/asm/arch-tegra/mmc.h
+++ b/arch/arm/include/asm/arch-tegra/mmc.h
@@ -22,6 +22,6 @@
#ifndef _TEGRA_MMC_H_
#define _TEGRA_MMC_H_
-int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+void tegra_mmc_init(void);
#endif /* _TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
index 2650744718..853e59bb6e 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
@@ -105,6 +105,7 @@ struct i2c_ctlr {
u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
u32 reserved_2[4]; /* 40: */
struct i2c_control control; /* 50 ~ 68 */
+ u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
};
/* bit fields definitions for IO Packet Header 1 format */
@@ -154,6 +155,11 @@ struct i2c_ctlr {
#define I2C_INT_ARBITRATION_LOST_SHIFT 2
#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
+/* I2C_CLK_DIVISOR_REGISTER */
+#define CLK_DIV_STD_FAST_MODE 0x19
+#define CLK_DIV_HS_MODE 1
+#define CLK_MULT_STD_FAST_MODE 8
+
/**
* Returns the bus number of the DVC controller
*
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index dd746cae0d..2a3f830cc5 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -22,10 +22,9 @@
#ifndef __TEGRA_MMC_H_
#define __TEGRA_MMC_H_
-#define TEGRA_SDMMC1_BASE 0xC8000000
-#define TEGRA_SDMMC2_BASE 0xC8000200
-#define TEGRA_SDMMC3_BASE 0xC8000400
-#define TEGRA_SDMMC4_BASE 0xC8000600
+#include <fdtdec.h>
+
+#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
#ifndef __ASSEMBLY__
struct tegra_mmc {
@@ -62,12 +61,30 @@ struct tegra_mmc {
unsigned char admaerr; /* offset 54h */
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
- unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
+ unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
- unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
+ unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
+ unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */
+ unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */
+ unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */
+ unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */
+ unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
+ unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
+ unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
+ unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */
+ unsigned int res6[47]; /* 0x124 ~ 0x1DC */
+ unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */
+ unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */
+ unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */
+ unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */
};
+#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1)
+
#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
@@ -117,15 +134,26 @@ struct tegra_mmc {
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define MEMCOMP_PADCTRL_VREF 7
+#define AUTO_CAL_ENABLED (1 << 29)
+#define AUTO_CAL_PD_OFFSET (0x70 << 8)
+#define AUTO_CAL_PU_OFFSET (0x62 << 0)
+
struct mmc_host {
struct tegra_mmc *reg;
+ int id; /* device id/number, 0-3 */
+ int enabled; /* 1 to enable, 0 to disable */
+ int width; /* Bus Width, 1, 4 or 8 */
+ enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
+ struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
+ struct fdt_gpio_state pwr_gpio; /* Power GPIO */
+ struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
- unsigned int base; /* Base address, SDMMC1/2/3/4 */
- enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
- int pwr_gpio; /* Power GPIO */
- int cd_gpio; /* Change Detect GPIO */
};
+void pad_init_mmc(struct mmc_host *host);
+
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index fdbd127e6c..ef6c089be2 100644
--- a/arch/arm/include/asm/arch-tegra20/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -243,29 +243,7 @@ struct usb_ctlr {
#define VBUS_VLD_STS (1 << 26)
-/* Change the USB host port into host mode */
-void usb_set_host_mode(void);
-
/* Setup USB on the board */
int board_usb_init(const void *blob);
-/**
- * Start up the given port number (ports are numbered from 0 on each board).
- * This returns values for the appropriate hccr and hcor addresses to use for
- * USB EHCI operations.
- *
- * @param portnum port number to start
- * @param hccr returns start address of EHCI HCCR registers
- * @param hcor returns start address of EHCI HCOR registers
- * @return 0 if ok, -1 on error (generally invalid port number)
- */
-int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor);
-
-/**
- * Stop the current port
- *
- * @return 0 if ok, -1 if no port was active
- */
-int tegrausb_stop_port(int portnum);
-
#endif /* _TEGRA_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
index c538bdd052..1ef1a1484d 100644
--- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
@@ -27,7 +27,7 @@ struct apb_misc_gp_ctlr {
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
- u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
@@ -35,25 +35,43 @@ struct apb_misc_gp_ctlr {
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
- u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+ u32 reserved1; /* 0x8C: */
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
- u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
- u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
- u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+ u32 reserved2[3]; /* 0xA4 - 0xAC: */
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
- u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
- u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
- u32 reserved1[7]; /* 0xD0-0xE8: */
+ u32 reserved3[9]; /* 0xC8-0xE8: */
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+ u32 reserved4[3]; /* 0xF0-0xF8: */
+ u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+ u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+ u32 reserved5[3]; /* 0x104-0x10C: */
+ u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+ u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+ u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+ u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+ u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+ u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+ u32 reserved6; /* 0x128: */
+ u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+ u32 reserved7[2]; /* 0x130 - 0x134: */
+ u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+ u32 reserved8[22]; /* 0x13C - 0x190: */
+ u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+ u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+ u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+ u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+ u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+ u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+ u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
#endif /* _TEGRA114_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index fd2293039d..9c22c08b6e 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -50,72 +50,12 @@ enum pmux_pingrp {
PINGRP_SDMMC1_DAT2,
PINGRP_SDMMC1_DAT1,
PINGRP_SDMMC1_DAT0,
- PINGRP_GPIO_PV2,
- PINGRP_GPIO_PV3,
- PINGRP_CLK2_OUT,
+ PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
PINGRP_CLK2_REQ,
- PINGRP_LCD_PWR1,
- PINGRP_LCD_PWR2,
- PINGRP_LCD_SDIN,
- PINGRP_LCD_SDOUT,
- PINGRP_LCD_WR_N,
- PINGRP_LCD_CS0_N,
- PINGRP_LCD_DC0,
- PINGRP_LCD_SCK,
- PINGRP_LCD_PWR0,
- PINGRP_LCD_PCLK,
- PINGRP_LCD_DE,
- PINGRP_LCD_HSYNC,
- PINGRP_LCD_VSYNC,
- PINGRP_LCD_D0,
- PINGRP_LCD_D1,
- PINGRP_LCD_D2,
- PINGRP_LCD_D3,
- PINGRP_LCD_D4,
- PINGRP_LCD_D5,
- PINGRP_LCD_D6,
- PINGRP_LCD_D7,
- PINGRP_LCD_D8,
- PINGRP_LCD_D9,
- PINGRP_LCD_D10,
- PINGRP_LCD_D11,
- PINGRP_LCD_D12,
- PINGRP_LCD_D13,
- PINGRP_LCD_D14,
- PINGRP_LCD_D15,
- PINGRP_LCD_D16,
- PINGRP_LCD_D17,
- PINGRP_LCD_D18,
- PINGRP_LCD_D19,
- PINGRP_LCD_D20,
- PINGRP_LCD_D21,
- PINGRP_LCD_D22,
- PINGRP_LCD_D23,
- PINGRP_LCD_CS1_N,
- PINGRP_LCD_M1,
- PINGRP_LCD_DC1,
- PINGRP_HDMI_INT,
+ PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
PINGRP_DDC_SCL,
PINGRP_DDC_SDA,
- PINGRP_CRT_HSYNC,
- PINGRP_CRT_VSYNC,
- PINGRP_VI_D0,
- PINGRP_VI_D1,
- PINGRP_VI_D2,
- PINGRP_VI_D3,
- PINGRP_VI_D4,
- PINGRP_VI_D5,
- PINGRP_VI_D6,
- PINGRP_VI_D7,
- PINGRP_VI_D8,
- PINGRP_VI_D9,
- PINGRP_VI_D10,
- PINGRP_VI_D11,
- PINGRP_VI_PCLK,
- PINGRP_VI_MCLK,
- PINGRP_VI_VSYNC,
- PINGRP_VI_HSYNC,
- PINGRP_UART2_RXD,
+ PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
PINGRP_UART2_TXD,
PINGRP_UART2_RTS_N,
PINGRP_UART2_CTS_N,
@@ -186,8 +126,7 @@ enum pmux_pingrp {
PINGRP_SDMMC4_DAT5,
PINGRP_SDMMC4_DAT6,
PINGRP_SDMMC4_DAT7,
- PINGRP_SDMMC4_RST_N,
- PINGRP_CAM_MCLK,
+ PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
PINGRP_GPIO_PCC1,
PINGRP_GPIO_PBB0,
PINGRP_CAM_I2C_SCL,
@@ -212,12 +151,7 @@ enum pmux_pingrp {
PINGRP_KB_ROW8,
PINGRP_KB_ROW9,
PINGRP_KB_ROW10,
- PINGRP_KB_ROW11,
- PINGRP_KB_ROW12,
- PINGRP_KB_ROW13,
- PINGRP_KB_ROW14,
- PINGRP_KB_ROW15,
- PINGRP_KB_COL0,
+ PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
PINGRP_KB_COL1,
PINGRP_KB_COL2,
PINGRP_KB_COL3,
@@ -244,47 +178,30 @@ enum pmux_pingrp {
PINGRP_DAP2_DIN,
PINGRP_DAP2_DOUT,
PINGRP_DAP2_SCLK,
- PINGRP_SPI2_MOSI,
- PINGRP_SPI2_MISO,
- PINGRP_SPI2_CS0_N,
- PINGRP_SPI2_SCK,
- PINGRP_SPI1_MOSI,
- PINGRP_SPI1_SCK,
- PINGRP_SPI1_CS0_N,
- PINGRP_SPI1_MISO,
- PINGRP_SPI2_CS1_N,
- PINGRP_SPI2_CS2_N,
- PINGRP_SDMMC3_CLK,
+ PINGRP_DVFS_PWM,
+ PINGRP_GPIO_X1_AUD,
+ PINGRP_GPIO_X3_AUD,
+ PINGRP_DVFS_CLK,
+ PINGRP_GPIO_X4_AUD,
+ PINGRP_GPIO_X5_AUD,
+ PINGRP_GPIO_X6_AUD,
+ PINGRP_GPIO_X7_AUD,
+ PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
PINGRP_SDMMC3_CMD,
PINGRP_SDMMC3_DAT0,
PINGRP_SDMMC3_DAT1,
PINGRP_SDMMC3_DAT2,
PINGRP_SDMMC3_DAT3,
- PINGRP_SDMMC3_DAT4,
- PINGRP_SDMMC3_DAT5,
- PINGRP_SDMMC3_DAT6,
- PINGRP_SDMMC3_DAT7,
- PINGRP_PEX_L0_PRSNT_N,
- PINGRP_PEX_L0_RST_N,
- PINGRP_PEX_L0_CLKREQ_N,
- PINGRP_PEX_WAKE_N,
- PINGRP_PEX_L1_PRSNT_N,
- PINGRP_PEX_L1_RST_N,
- PINGRP_PEX_L1_CLKREQ_N,
- PINGRP_PEX_L2_PRSNT_N,
- PINGRP_PEX_L2_RST_N,
- PINGRP_PEX_L2_CLKREQ_N,
- PINGRP_HDMI_CEC, /* offset 0x33e0 */
+ PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
PINGRP_SDMMC1_WP_N,
PINGRP_SDMMC3_CD_N,
- PINGRP_SPI1_CS1_N,
- PINGRP_SPI1_CS2_N,
- PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
+ PINGRP_GPIO_W2_AUD,
+ PINGRP_GPIO_W3_AUD,
+ PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
PINGRP_USB_VBUS_EN1,
PINGRP_SDMMC3_CLK_LB_IN,
PINGRP_SDMMC3_CLK_LB_OUT,
- PINGRP_NAND_GMI_CLK_LB,
- PINGRP_RESET_OUT_N,
+ PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
PINGRP_COUNT,
};
@@ -298,41 +215,35 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_AT5,
PDRIVE_PINGROUP_CDEV1,
PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_CSUS,
- PDRIVE_PINGROUP_DAP1,
+ PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
PDRIVE_PINGROUP_DAP2,
PDRIVE_PINGROUP_DAP3,
PDRIVE_PINGROUP_DAP4,
PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_LCD1,
- PDRIVE_PINGROUP_LCD2,
- PDRIVE_PINGROUP_SDIO2,
- PDRIVE_PINGROUP_SDIO3,
+ PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
PDRIVE_PINGROUP_SPI,
PDRIVE_PINGROUP_UAA,
PDRIVE_PINGROUP_UAB,
PDRIVE_PINGROUP_UART2,
PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
- PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
- PDRIVE_PINGROUP_DDC,
+ PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
+ PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GMB,
- PDRIVE_PINGROUP_GMC,
- PDRIVE_PINGROUP_GMD,
- PDRIVE_PINGROUP_GME,
+ PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
PDRIVE_PINGROUP_GMF,
PDRIVE_PINGROUP_GMG,
PDRIVE_PINGROUP_GMH,
PDRIVE_PINGROUP_OWR,
PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_GPV,
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_AT6,
+ PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
PDRIVE_PINGROUP_DAP5,
PDRIVE_PINGROUP_VBUS,
+ PDRIVE_PINGROUP_AO3,
+ PDRIVE_PINGROUP_HVC,
+ PDRIVE_PINGROUP_SDIO4,
+ PDRIVE_PINGROUP_AO0,
PDRIVE_PINGROUP_COUNT,
};
@@ -401,6 +312,7 @@ enum pmux_func {
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
+ /* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLK12,
@@ -444,7 +356,7 @@ enum pmux_func {
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
-
+ /* End of Tegra3 MUX selectors */
PMUX_FUNC_USB,
PMUX_FUNC_SOC,
PMUX_FUNC_CPU,
@@ -453,10 +365,12 @@ enum pmux_func {
PMUX_FUNC_PMI,
PMUX_FUNC_CLDVFS,
PMUX_FUNC_RESET_OUT_N,
+ /* End of Tegra114 MUX selectors */
PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
+ PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
@@ -492,6 +406,7 @@ enum pmux_tristate {
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
+ PMUX_PIN_NONE,
};
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
@@ -525,6 +440,16 @@ enum pmux_pin_ioreset {
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+enum pmux_pin_rcv_sel {
+ PMUX_PIN_RCV_SEL_DEFAULT = 0,
+ PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_HIGH,
+};
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+ (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
+ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
@@ -546,10 +471,73 @@ enum pmux_vddio {
PMUX_VDDIO_NONE
};
-/* T114 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
+#define PGRP_SLWF_NONE -1
+#define PGRP_SLWF_MAX 3
+#define PGRP_SLWR_NONE PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE -1
+#define PGRP_DRVUP_MAX 127
+#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
+
+#define PGRP_SCHMT_NONE -1
+#define PGRP_HSM_NONE PGRP_SCHMT_NONE
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
+ (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
+ (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
+ (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+ PGRP_LPMD_X8 = 0,
+ PGRP_LPMD_X4,
+ PGRP_LPMD_X2,
+ PGRP_LPMD_X,
+ PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+ PGRP_SCHMT_DISABLE = 0,
+ PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+ PGRP_HSM_DISABLE = 0,
+ PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+ enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
+ int slwf; /* falling edge slew */
+ int slwr; /* rising edge slew */
+ int drvup; /* pull-up drive strength */
+ int drvdn; /* pull-down drive strength */
+ enum pgrp_lpmd lpmd; /* low-power mode selection */
+ enum pgrp_schmt schmt; /* schmidt enable */
+ enum pgrp_hsm hsm; /* high-speed mode enable */
+};
+
+/* t114 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+ PDRIVE_PINGROUP_COUNT)
struct pmux_tri_ctlr {
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
@@ -581,6 +569,8 @@ struct pingroup_config {
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
enum pmux_pin_od od; /* open-drain or push-pull driver */
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+ enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
+ /* VIL/VIH receivers */
};
/* Set a pin group to tristate */
@@ -615,4 +605,12 @@ void pinmux_config_table(struct pingroup_config *config, int len);
/* Set a group of pins from a table */
void pinmux_init(void);
-#endif /* _TEGRA114_PINMUX_H_ */
+/**
+ * Set the GP pad configs
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
+#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index e1de0447ff..ad5c01d1f4 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -29,7 +29,6 @@
#include <asm/arch-tegra/tegra.h>
#define TEGRA_USB1_BASE 0xC5000000
-#define TEGRA_USB3_BASE 0xC5008000
#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
index 9b383d0e74..23d184f2dd 100644
--- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
@@ -56,4 +56,10 @@ struct apb_misc_gp_ctlr {
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
};
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define SDIOCFG_DRVUP_SLWF 1
+#define SDIOCFG_DRVDN_SLWR 1
+#define SDIOCFG_DRVUP 0x2E
+#define SDIOCFG_DRVDN 0x2A
+
#endif /* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index 341951bfcb..a9e1b462c4 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -531,6 +531,63 @@ enum pmux_vddio {
PMUX_VDDIO_NONE
};
+#define PGRP_SLWF_NONE -1
+#define PGRP_SLWF_MAX 3
+#define PGRP_SLWR_NONE PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE -1
+#define PGRP_DRVUP_MAX 127
+#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+ PGRP_LPMD_X8 = 0,
+ PGRP_LPMD_X4,
+ PGRP_LPMD_X2,
+ PGRP_LPMD_X,
+ PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+ PGRP_SCHMT_DISABLE = 0,
+ PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+ PGRP_HSM_DISABLE = 0,
+ PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+ enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
+ int slwf; /* falling edge slew */
+ int slwr; /* rising edge slew */
+ int drvup; /* pull-up drive strength */
+ int drvdn; /* pull-down drive strength */
+ enum pgrp_lpmd lpmd; /* low-power mode selection */
+ enum pgrp_schmt schmt; /* schmidt enable */
+ enum pgrp_hsm hsm; /* high-speed mode enable */
+};
+
/* t30 pin drive group and pin mux registers */
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
@@ -600,4 +657,12 @@ void pinmux_config_table(struct pingroup_config *config, int len);
/* Set a group of pins from a table */
void pinmux_init(void);
+/**
+ * Set the GP pad configs
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index decf564d13..c02c5d8500 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -21,6 +21,8 @@
#include <asm/arch-tegra/tegra.h>
+#define TEGRA_USB1_BASE 0x7D000000
+
#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
#define MAX_NUM_CPU 4
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
new file mode 100644
index 0000000000..d0c69da971
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
+#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
+#define XPSS_SCU_BASEADDR 0xF8F00000
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+ u32 scl; /* 0x0 */
+ u32 slcr_lock; /* 0x4 */
+ u32 slcr_unlock; /* 0x8 */
+ u32 reserved1[125];
+ u32 pss_rst_ctrl; /* 0x200 */
+ u32 reserved2[15];
+ u32 fpga_rst_ctrl; /* 0x240 */
+ u32 reserved3[5];
+ u32 reboot_status; /* 0x258 */
+ u32 boot_mode; /* 0x25c */
+ u32 reserved4[116];
+ u32 trust_zone; /* 0x430 */ /* FIXME */
+ u32 reserved5[115];
+ u32 ddr_urgent; /* 0x600 */
+ u32 reserved6[6];
+ u32 ddr_urgent_sel; /* 0x61c */
+ u32 reserved7[188];
+ u32 ocm_cfg; /* 0x910 */
+};
+
+#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+
+struct devcfg_regs {
+ u32 ctrl; /* 0x0 */
+ u32 lock; /* 0x4 */
+ u32 cfg; /* 0x8 */
+ u32 int_sts; /* 0xc */
+ u32 int_mask; /* 0x10 */
+ u32 status; /* 0x14 */
+ u32 dma_src_addr; /* 0x18 */
+ u32 dma_dst_addr; /* 0x1c */
+ u32 dma_src_len; /* 0x20 */
+ u32 dma_dst_len; /* 0x24 */
+ u32 rom_shadow; /* 0x28 */
+ u32 reserved1[2];
+ u32 unlock; /* 0x34 */
+ u32 reserved2[18];
+ u32 mctrl; /* 0x80 */
+ u32 reserved3;
+ u32 write_count; /* 0x88 */
+ u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+ u32 reserved1[16];
+ u32 filter_start; /* 0x40 */
+ u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
new file mode 100644
index 0000000000..e78890011a
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+extern void zynq_slcr_lock(void);
+extern void zynq_slcr_unlock(void);
+extern void zynq_slcr_cpu_reset(void);
+
+#endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index ad9a875de5..a73630bc4d 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -33,6 +33,7 @@
/* Cortex-A15 revisions */
#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
+#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ed251ec8ec..c5d1e6c837 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -519,6 +519,7 @@
#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
/* DMM */
#define DMM_BASE 0x4E000040
@@ -696,11 +697,9 @@ struct dmm_lisa_map_regs {
u32 dmm_lisa_map_1;
u32 dmm_lisa_map_2;
u32 dmm_lisa_map_3;
+ u8 is_ma_present;
};
-extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
#define CS0 0
#define CS1 1
/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -1027,6 +1026,11 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
#define MR8_IO_WIDTH_SHIFT 0x6
#define MR8_IO_WIDTH_MASK (0x3 << 0x6)
+/* SDRAM TYPE */
+#define EMIF_SDRAM_TYPE_DDR2 0x2
+#define EMIF_SDRAM_TYPE_DDR3 0x3
+#define EMIF_SDRAM_TYPE_LPDDR2 0x4
+
struct lpddr2_addressing {
u8 num_banks;
u8 t_REFI_us_x10;
@@ -1129,6 +1133,14 @@ struct emif_regs {
u32 emif_rd_wr_exec_thresh;
};
+struct lpddr2_mr_regs {
+ s8 mr1;
+ s8 mr2;
+ s8 mr3;
+ s8 mr10;
+ s8 mr16;
+};
+
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })
@@ -1148,6 +1160,7 @@ void emif_get_device_timings(u32 emif_nr,
#endif
void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern u32 *const T_num;
@@ -1156,4 +1169,5 @@ extern u32 *const emif_sizes;
#endif
void config_data_eye_leveling_samples(u32 emif_base);
+u32 emif_sdram_type(void);
#endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 2a40b898e3..091ddb508d 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,524 @@
#ifndef _OMAP_COMMON_H_
#define _OMAP_COMMON_H_
+#include <common.h>
+
+#define NUM_SYS_CLKS 8
+
+struct prcm_regs {
+ /* cm1.ckgen */
+ u32 cm_clksel_core;
+ u32 cm_clksel_abe;
+ u32 cm_dll_ctrl;
+ u32 cm_clkmode_dpll_core;
+ u32 cm_idlest_dpll_core;
+ u32 cm_autoidle_dpll_core;
+ u32 cm_clksel_dpll_core;
+ u32 cm_div_m2_dpll_core;
+ u32 cm_div_m3_dpll_core;
+ u32 cm_div_h11_dpll_core;
+ u32 cm_div_h12_dpll_core;
+ u32 cm_div_h13_dpll_core;
+ u32 cm_div_h14_dpll_core;
+ u32 cm_div_h21_dpll_core;
+ u32 cm_div_h24_dpll_core;
+ u32 cm_ssc_deltamstep_dpll_core;
+ u32 cm_ssc_modfreqdiv_dpll_core;
+ u32 cm_emu_override_dpll_core;
+ u32 cm_div_h22_dpllcore;
+ u32 cm_div_h23_dpll_core;
+ u32 cm_clkmode_dpll_mpu;
+ u32 cm_idlest_dpll_mpu;
+ u32 cm_autoidle_dpll_mpu;
+ u32 cm_clksel_dpll_mpu;
+ u32 cm_div_m2_dpll_mpu;
+ u32 cm_ssc_deltamstep_dpll_mpu;
+ u32 cm_ssc_modfreqdiv_dpll_mpu;
+ u32 cm_bypclk_dpll_mpu;
+ u32 cm_clkmode_dpll_iva;
+ u32 cm_idlest_dpll_iva;
+ u32 cm_autoidle_dpll_iva;
+ u32 cm_clksel_dpll_iva;
+ u32 cm_div_h11_dpll_iva;
+ u32 cm_div_h12_dpll_iva;
+ u32 cm_ssc_deltamstep_dpll_iva;
+ u32 cm_ssc_modfreqdiv_dpll_iva;
+ u32 cm_bypclk_dpll_iva;
+ u32 cm_clkmode_dpll_abe;
+ u32 cm_idlest_dpll_abe;
+ u32 cm_autoidle_dpll_abe;
+ u32 cm_clksel_dpll_abe;
+ u32 cm_div_m2_dpll_abe;
+ u32 cm_div_m3_dpll_abe;
+ u32 cm_ssc_deltamstep_dpll_abe;
+ u32 cm_ssc_modfreqdiv_dpll_abe;
+ u32 cm_clkmode_dpll_ddrphy;
+ u32 cm_idlest_dpll_ddrphy;
+ u32 cm_autoidle_dpll_ddrphy;
+ u32 cm_clksel_dpll_ddrphy;
+ u32 cm_div_m2_dpll_ddrphy;
+ u32 cm_div_h11_dpll_ddrphy;
+ u32 cm_div_h12_dpll_ddrphy;
+ u32 cm_div_h13_dpll_ddrphy;
+ u32 cm_ssc_deltamstep_dpll_ddrphy;
+ u32 cm_clkmode_dpll_dsp;
+ u32 cm_shadow_freq_config1;
+ u32 cm_mpu_mpu_clkctrl;
+
+ /* cm1.dsp */
+ u32 cm_dsp_clkstctrl;
+ u32 cm_dsp_dsp_clkctrl;
+
+ /* cm1.abe */
+ u32 cm1_abe_clkstctrl;
+ u32 cm1_abe_l4abe_clkctrl;
+ u32 cm1_abe_aess_clkctrl;
+ u32 cm1_abe_pdm_clkctrl;
+ u32 cm1_abe_dmic_clkctrl;
+ u32 cm1_abe_mcasp_clkctrl;
+ u32 cm1_abe_mcbsp1_clkctrl;
+ u32 cm1_abe_mcbsp2_clkctrl;
+ u32 cm1_abe_mcbsp3_clkctrl;
+ u32 cm1_abe_slimbus_clkctrl;
+ u32 cm1_abe_timer5_clkctrl;
+ u32 cm1_abe_timer6_clkctrl;
+ u32 cm1_abe_timer7_clkctrl;
+ u32 cm1_abe_timer8_clkctrl;
+ u32 cm1_abe_wdt3_clkctrl;
+
+ /* cm2.ckgen */
+ u32 cm_clksel_mpu_m3_iss_root;
+ u32 cm_clksel_usb_60mhz;
+ u32 cm_scale_fclk;
+ u32 cm_core_dvfs_perf1;
+ u32 cm_core_dvfs_perf2;
+ u32 cm_core_dvfs_perf3;
+ u32 cm_core_dvfs_perf4;
+ u32 cm_core_dvfs_current;
+ u32 cm_iva_dvfs_perf_tesla;
+ u32 cm_iva_dvfs_perf_ivahd;
+ u32 cm_iva_dvfs_perf_abe;
+ u32 cm_iva_dvfs_current;
+ u32 cm_clkmode_dpll_per;
+ u32 cm_idlest_dpll_per;
+ u32 cm_autoidle_dpll_per;
+ u32 cm_clksel_dpll_per;
+ u32 cm_div_m2_dpll_per;
+ u32 cm_div_m3_dpll_per;
+ u32 cm_div_h11_dpll_per;
+ u32 cm_div_h12_dpll_per;
+ u32 cm_div_h13_dpll_per;
+ u32 cm_div_h14_dpll_per;
+ u32 cm_ssc_deltamstep_dpll_per;
+ u32 cm_ssc_modfreqdiv_dpll_per;
+ u32 cm_emu_override_dpll_per;
+ u32 cm_clkmode_dpll_usb;
+ u32 cm_idlest_dpll_usb;
+ u32 cm_autoidle_dpll_usb;
+ u32 cm_clksel_dpll_usb;
+ u32 cm_div_m2_dpll_usb;
+ u32 cm_ssc_deltamstep_dpll_usb;
+ u32 cm_ssc_modfreqdiv_dpll_usb;
+ u32 cm_clkdcoldo_dpll_usb;
+ u32 cm_clkmode_dpll_pcie_ref;
+ u32 cm_clkmode_apll_pcie;
+ u32 cm_idlest_apll_pcie;
+ u32 cm_div_m2_apll_pcie;
+ u32 cm_clkvcoldo_apll_pcie;
+ u32 cm_clkmode_dpll_unipro;
+ u32 cm_idlest_dpll_unipro;
+ u32 cm_autoidle_dpll_unipro;
+ u32 cm_clksel_dpll_unipro;
+ u32 cm_div_m2_dpll_unipro;
+ u32 cm_ssc_deltamstep_dpll_unipro;
+ u32 cm_ssc_modfreqdiv_dpll_unipro;
+
+ /* cm2.core */
+ u32 cm_coreaon_bandgap_clkctrl;
+ u32 cm_coreaon_io_srcomp_clkctrl;
+ u32 cm_l3_1_clkstctrl;
+ u32 cm_l3_1_dynamicdep;
+ u32 cm_l3_1_l3_1_clkctrl;
+ u32 cm_l3_2_clkstctrl;
+ u32 cm_l3_2_dynamicdep;
+ u32 cm_l3_2_l3_2_clkctrl;
+ u32 cm_l3_gpmc_clkctrl;
+ u32 cm_l3_2_ocmc_ram_clkctrl;
+ u32 cm_mpu_m3_clkstctrl;
+ u32 cm_mpu_m3_staticdep;
+ u32 cm_mpu_m3_dynamicdep;
+ u32 cm_mpu_m3_mpu_m3_clkctrl;
+ u32 cm_sdma_clkstctrl;
+ u32 cm_sdma_staticdep;
+ u32 cm_sdma_dynamicdep;
+ u32 cm_sdma_sdma_clkctrl;
+ u32 cm_memif_clkstctrl;
+ u32 cm_memif_dmm_clkctrl;
+ u32 cm_memif_emif_fw_clkctrl;
+ u32 cm_memif_emif_1_clkctrl;
+ u32 cm_memif_emif_2_clkctrl;
+ u32 cm_memif_dll_clkctrl;
+ u32 cm_memif_emif_h1_clkctrl;
+ u32 cm_memif_emif_h2_clkctrl;
+ u32 cm_memif_dll_h_clkctrl;
+ u32 cm_c2c_clkstctrl;
+ u32 cm_c2c_staticdep;
+ u32 cm_c2c_dynamicdep;
+ u32 cm_c2c_sad2d_clkctrl;
+ u32 cm_c2c_modem_icr_clkctrl;
+ u32 cm_c2c_sad2d_fw_clkctrl;
+ u32 cm_l4cfg_clkstctrl;
+ u32 cm_l4cfg_dynamicdep;
+ u32 cm_l4cfg_l4_cfg_clkctrl;
+ u32 cm_l4cfg_hw_sem_clkctrl;
+ u32 cm_l4cfg_mailbox_clkctrl;
+ u32 cm_l4cfg_sar_rom_clkctrl;
+ u32 cm_l3instr_clkstctrl;
+ u32 cm_l3instr_l3_3_clkctrl;
+ u32 cm_l3instr_l3_instr_clkctrl;
+ u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+ /* cm2.ivahd */
+ u32 cm_ivahd_clkstctrl;
+ u32 cm_ivahd_ivahd_clkctrl;
+ u32 cm_ivahd_sl2_clkctrl;
+
+ /* cm2.cam */
+ u32 cm_cam_clkstctrl;
+ u32 cm_cam_iss_clkctrl;
+ u32 cm_cam_fdif_clkctrl;
+ u32 cm_cam_vip1_clkctrl;
+ u32 cm_cam_vip2_clkctrl;
+ u32 cm_cam_vip3_clkctrl;
+ u32 cm_cam_lvdsrx_clkctrl;
+ u32 cm_cam_csi1_clkctrl;
+ u32 cm_cam_csi2_clkctrl;
+
+ /* cm2.dss */
+ u32 cm_dss_clkstctrl;
+ u32 cm_dss_dss_clkctrl;
+
+ /* cm2.sgx */
+ u32 cm_sgx_clkstctrl;
+ u32 cm_sgx_sgx_clkctrl;
+
+ /* cm2.l3init */
+ u32 cm_l3init_clkstctrl;
+
+ /* cm2.l3init */
+ u32 cm_l3init_hsmmc1_clkctrl;
+ u32 cm_l3init_hsmmc2_clkctrl;
+ u32 cm_l3init_hsi_clkctrl;
+ u32 cm_l3init_hsusbhost_clkctrl;
+ u32 cm_l3init_hsusbotg_clkctrl;
+ u32 cm_l3init_hsusbtll_clkctrl;
+ u32 cm_l3init_p1500_clkctrl;
+ u32 cm_l3init_fsusb_clkctrl;
+ u32 cm_l3init_ocp2scp1_clkctrl;
+
+ /* cm2.l4per */
+ u32 cm_l4per_clkstctrl;
+ u32 cm_l4per_dynamicdep;
+ u32 cm_l4per_adc_clkctrl;
+ u32 cm_l4per_gptimer10_clkctrl;
+ u32 cm_l4per_gptimer11_clkctrl;
+ u32 cm_l4per_gptimer2_clkctrl;
+ u32 cm_l4per_gptimer3_clkctrl;
+ u32 cm_l4per_gptimer4_clkctrl;
+ u32 cm_l4per_gptimer9_clkctrl;
+ u32 cm_l4per_elm_clkctrl;
+ u32 cm_l4per_gpio2_clkctrl;
+ u32 cm_l4per_gpio3_clkctrl;
+ u32 cm_l4per_gpio4_clkctrl;
+ u32 cm_l4per_gpio5_clkctrl;
+ u32 cm_l4per_gpio6_clkctrl;
+ u32 cm_l4per_hdq1w_clkctrl;
+ u32 cm_l4per_hecc1_clkctrl;
+ u32 cm_l4per_hecc2_clkctrl;
+ u32 cm_l4per_i2c1_clkctrl;
+ u32 cm_l4per_i2c2_clkctrl;
+ u32 cm_l4per_i2c3_clkctrl;
+ u32 cm_l4per_i2c4_clkctrl;
+ u32 cm_l4per_l4per_clkctrl;
+ u32 cm_l4per_mcasp2_clkctrl;
+ u32 cm_l4per_mcasp3_clkctrl;
+ u32 cm_l4per_mgate_clkctrl;
+ u32 cm_l4per_mcspi1_clkctrl;
+ u32 cm_l4per_mcspi2_clkctrl;
+ u32 cm_l4per_mcspi3_clkctrl;
+ u32 cm_l4per_mcspi4_clkctrl;
+ u32 cm_l4per_gpio7_clkctrl;
+ u32 cm_l4per_gpio8_clkctrl;
+ u32 cm_l4per_mmcsd3_clkctrl;
+ u32 cm_l4per_mmcsd4_clkctrl;
+ u32 cm_l4per_msprohg_clkctrl;
+ u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_uart1_clkctrl;
+ u32 cm_l4per_uart2_clkctrl;
+ u32 cm_l4per_uart3_clkctrl;
+ u32 cm_l4per_uart4_clkctrl;
+ u32 cm_l4per_mmcsd5_clkctrl;
+ u32 cm_l4per_i2c5_clkctrl;
+ u32 cm_l4per_uart5_clkctrl;
+ u32 cm_l4per_uart6_clkctrl;
+ u32 cm_l4sec_clkstctrl;
+ u32 cm_l4sec_staticdep;
+ u32 cm_l4sec_dynamicdep;
+ u32 cm_l4sec_aes1_clkctrl;
+ u32 cm_l4sec_aes2_clkctrl;
+ u32 cm_l4sec_des3des_clkctrl;
+ u32 cm_l4sec_pkaeip29_clkctrl;
+ u32 cm_l4sec_rng_clkctrl;
+ u32 cm_l4sec_sha2md51_clkctrl;
+ u32 cm_l4sec_cryptodma_clkctrl;
+
+ /* l4 wkup regs */
+ u32 cm_abe_pll_ref_clksel;
+ u32 cm_sys_clksel;
+ u32 cm_wkup_clkstctrl;
+ u32 cm_wkup_l4wkup_clkctrl;
+ u32 cm_wkup_wdtimer1_clkctrl;
+ u32 cm_wkup_wdtimer2_clkctrl;
+ u32 cm_wkup_gpio1_clkctrl;
+ u32 cm_wkup_gptimer1_clkctrl;
+ u32 cm_wkup_gptimer12_clkctrl;
+ u32 cm_wkup_synctimer_clkctrl;
+ u32 cm_wkup_usim_clkctrl;
+ u32 cm_wkup_sarram_clkctrl;
+ u32 cm_wkup_keyboard_clkctrl;
+ u32 cm_wkup_rtc_clkctrl;
+ u32 cm_wkup_bandgap_clkctrl;
+ u32 cm_wkupaon_scrm_clkctrl;
+ u32 cm_wkupaon_io_srcomp_clkctrl;
+ u32 prm_rstctrl;
+ u32 prm_rstst;
+ u32 prm_vc_val_bypass;
+ u32 prm_vc_cfg_i2c_mode;
+ u32 prm_vc_cfg_i2c_clk;
+ u32 prm_sldo_core_setup;
+ u32 prm_sldo_core_ctrl;
+ u32 prm_sldo_mpu_setup;
+ u32 prm_sldo_mpu_ctrl;
+ u32 prm_sldo_mm_setup;
+ u32 prm_sldo_mm_ctrl;
+
+ u32 cm_div_m4_dpll_core;
+ u32 cm_div_m5_dpll_core;
+ u32 cm_div_m6_dpll_core;
+ u32 cm_div_m7_dpll_core;
+ u32 cm_div_m4_dpll_iva;
+ u32 cm_div_m5_dpll_iva;
+ u32 cm_div_m4_dpll_ddrphy;
+ u32 cm_div_m5_dpll_ddrphy;
+ u32 cm_div_m6_dpll_ddrphy;
+ u32 cm_div_m4_dpll_per;
+ u32 cm_div_m5_dpll_per;
+ u32 cm_div_m6_dpll_per;
+ u32 cm_div_m7_dpll_per;
+ u32 cm_l3instr_intrconn_wp1_clkct;
+ u32 cm_l3init_usbphy_clkctrl;
+ u32 cm_l4per_mcbsp4_clkctrl;
+ u32 prm_vc_cfg_channel;
+};
+
+struct omap_sys_ctrl_regs {
+ u32 control_status;
+ u32 control_core_mmr_lock1;
+ u32 control_core_mmr_lock2;
+ u32 control_core_mmr_lock3;
+ u32 control_core_mmr_lock4;
+ u32 control_core_mmr_lock5;
+ u32 control_core_control_io1;
+ u32 control_core_control_io2;
+ u32 control_id_code;
+ u32 control_std_fuse_opp_bgap;
+ u32 control_ldosram_iva_voltage_ctrl;
+ u32 control_ldosram_mpu_voltage_ctrl;
+ u32 control_ldosram_core_voltage_ctrl;
+ u32 control_padconf_core_base;
+ u32 control_paconf_global;
+ u32 control_paconf_mode;
+ u32 control_smart1io_padconf_0;
+ u32 control_smart1io_padconf_1;
+ u32 control_smart1io_padconf_2;
+ u32 control_smart2io_padconf_0;
+ u32 control_smart2io_padconf_1;
+ u32 control_smart2io_padconf_2;
+ u32 control_smart3io_padconf_0;
+ u32 control_smart3io_padconf_1;
+ u32 control_pbias;
+ u32 control_i2c_0;
+ u32 control_camera_rx;
+ u32 control_hdmi_tx_phy;
+ u32 control_uniportm;
+ u32 control_dsiphy;
+ u32 control_mcbsplp;
+ u32 control_usb2phycore;
+ u32 control_hdmi_1;
+ u32 control_hsi;
+ u32 control_ddr3ch1_0;
+ u32 control_ddr3ch2_0;
+ u32 control_ddrch1_0;
+ u32 control_ddrch1_1;
+ u32 control_ddrch2_0;
+ u32 control_ddrch2_1;
+ u32 control_lpddr2ch1_0;
+ u32 control_lpddr2ch1_1;
+ u32 control_ddrio_0;
+ u32 control_ddrio_1;
+ u32 control_ddrio_2;
+ u32 control_lpddr2io1_0;
+ u32 control_lpddr2io1_1;
+ u32 control_lpddr2io1_2;
+ u32 control_lpddr2io1_3;
+ u32 control_lpddr2io2_0;
+ u32 control_lpddr2io2_1;
+ u32 control_lpddr2io2_2;
+ u32 control_lpddr2io2_3;
+ u32 control_hyst_1;
+ u32 control_usbb_hsic_control;
+ u32 control_c2c;
+ u32 control_core_control_spare_rw;
+ u32 control_core_control_spare_r;
+ u32 control_core_control_spare_r_c0;
+ u32 control_srcomp_north_side;
+ u32 control_srcomp_south_side;
+ u32 control_srcomp_east_side;
+ u32 control_srcomp_west_side;
+ u32 control_srcomp_code_latch;
+ u32 control_pbiaslite;
+ u32 control_port_emif1_sdram_config;
+ u32 control_port_emif1_lpddr2_nvm_config;
+ u32 control_port_emif2_sdram_config;
+ u32 control_emif1_sdram_config_ext;
+ u32 control_emif2_sdram_config_ext;
+ u32 control_smart1nopmio_padconf_0;
+ u32 control_smart1nopmio_padconf_1;
+ u32 control_padconf_mode;
+ u32 control_xtal_oscillator;
+ u32 control_i2c_2;
+ u32 control_ckobuffer;
+ u32 control_wkup_control_spare_rw;
+ u32 control_wkup_control_spare_r;
+ u32 control_wkup_control_spare_r_c0;
+ u32 control_srcomp_east_side_wkup;
+ u32 control_efuse_1;
+ u32 control_efuse_2;
+ u32 control_efuse_3;
+ u32 control_efuse_4;
+ u32 control_efuse_5;
+ u32 control_efuse_6;
+ u32 control_efuse_7;
+ u32 control_efuse_8;
+ u32 control_efuse_9;
+ u32 control_efuse_10;
+ u32 control_efuse_11;
+ u32 control_efuse_12;
+ u32 control_efuse_13;
+ u32 control_padconf_wkup_base;
+};
+
+struct dpll_params {
+ u32 m;
+ u32 n;
+ s8 m2;
+ s8 m3;
+ s8 m4_h11;
+ s8 m5_h12;
+ s8 m6_h13;
+ s8 m7_h14;
+ s8 h21;
+ s8 h22;
+ s8 h23;
+ s8 h24;
+};
+
+struct dpll_regs {
+ u32 cm_clkmode_dpll;
+ u32 cm_idlest_dpll;
+ u32 cm_autoidle_dpll;
+ u32 cm_clksel_dpll;
+ u32 cm_div_m2_dpll;
+ u32 cm_div_m3_dpll;
+ u32 cm_div_m4_h11_dpll;
+ u32 cm_div_m5_h12_dpll;
+ u32 cm_div_m6_h13_dpll;
+ u32 cm_div_m7_h14_dpll;
+ u32 reserved[2];
+ u32 cm_div_h21_dpll;
+ u32 cm_div_h22_dpll;
+ u32 cm_div_h23_dpll;
+ u32 cm_div_h24_dpll;
+};
+
+struct dplls {
+ const struct dpll_params *mpu;
+ const struct dpll_params *core;
+ const struct dpll_params *per;
+ const struct dpll_params *abe;
+ const struct dpll_params *iva;
+ const struct dpll_params *usb;
+ const struct dpll_params *ddr;
+};
+
+struct pmic_data {
+ u32 base_offset;
+ u32 step;
+ u32 start_code;
+ unsigned gpio;
+ int gpio_en;
+};
+
+struct volts {
+ u32 value;
+ u32 addr;
+ struct pmic_data *pmic;
+};
+
+struct vcores_data {
+ struct volts mpu;
+ struct volts core;
+ struct volts mm;
+};
+
+extern struct prcm_regs const **prcm;
+extern struct prcm_regs const omap5_es1_prcm;
+extern struct prcm_regs const omap5_es2_prcm;
+extern struct prcm_regs const omap4_prcm;
+extern struct prcm_regs const dra7xx_prcm;
+extern struct dplls const **dplls_data;
+extern struct vcores_data const **omap_vcores;
+extern const u32 sys_clk_array[8];
+extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const omap4_ctrl;
+extern struct omap_sys_ctrl_regs const omap5_ctrl;
+extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+
+void hw_data_init(void);
+
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
+const struct dpll_params *get_core_dpll_params(struct dplls const *);
+const struct dpll_params *get_per_dpll_params(struct dplls const *);
+const struct dpll_params *get_iva_dpll_params(struct dplls const *);
+const struct dpll_params *get_usb_dpll_params(struct dplls const *);
+const struct dpll_params *get_abe_dpll_params(struct dplls const *);
+
+void do_enable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+
+void setup_post_dividers(u32 const base,
+ const struct dpll_params *params);
+u32 omap_ddr_clk(void);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_basic_uboot_clocks(void);
+void enable_non_essential_clocks(void);
+void scale_vcores(struct vcores_data const *);
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
+
/* Max value for DPLL multiplier M */
#define OMAP_DPLL_MAX_N 127
@@ -60,4 +578,9 @@ static inline u32 omap_revision(void)
#define OMAP5430_SILICON_ID_INVALID 0
#define OMAP5430_ES1_0 0x54300100
#define OMAP5432_ES1_0 0x54320100
+#define OMAP5430_ES2_0 0x54300200
+#define OMAP5432_ES2_0 0x54320200
+
+/* DRA7XX */
+#define DRA752_ES1_0 0x07520100
#endif /* _OMAP_COMMON_H_ */
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
new file mode 100644
index 0000000000..617e22fa52
--- /dev/null
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef OMAP_MMC_H_
+#define OMAP_MMC_H_
+
+struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+};
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define MSBS_MULTIBLK (0x1 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define CMDI_MASK (0x1 << 0)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE 96 /* MHz */
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
+ int wp_gpio);
+
+
+#endif /* OMAP_MMC_H_ */
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