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-rw-r--r--.gitignore1
-rw-r--r--MAINTAINERS11
-rw-r--r--Makefile17
-rw-r--r--README29
-rw-r--r--arch/arm/cpu/arm1136/mx35/generic.c2
-rw-r--r--arch/arm/cpu/arm720t/tegra114/cpu.c37
-rw-r--r--arch/arm/cpu/arm920t/ep93xx/u-boot.lds2
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c30
-rw-r--r--arch/arm/cpu/arm926ejs/config.mk2
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/clock.c3
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxs_init.h2
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c16
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_power_init.c2
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/timer.c39
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds6
-rw-r--r--arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds6
-rw-r--r--arch/arm/cpu/armv7/Makefile2
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c4
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c12
-rw-r--r--arch/arm/cpu/armv7/am33xx/u-boot-spl.lds67
-rw-r--r--arch/arm/cpu/armv7/config.mk2
-rw-r--r--arch/arm/cpu/armv7/mx6/Makefile1
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c16
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c7
-rw-r--r--arch/arm/cpu/armv7/omap-common/clocks-common.c312
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c73
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c23
-rw-r--r--arch/arm/cpu/armv7/omap-common/u-boot-spl.lds4
-rw-r--r--arch/arm/cpu/armv7/omap-common/vc.c11
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c6
-rw-r--r--arch/arm/cpu/armv7/omap4/Makefile3
-rw-r--r--arch/arm/cpu/armv7/omap4/clocks.c517
-rw-r--r--arch/arm/cpu/armv7/omap4/hw_data.c491
-rw-r--r--arch/arm/cpu/armv7/omap4/hwinit.c36
-rw-r--r--arch/arm/cpu/armv7/omap4/prcm-regs.c315
-rw-r--r--arch/arm/cpu/armv7/omap4/sdram_elpida.c34
-rw-r--r--arch/arm/cpu/armv7/omap5/Makefile3
-rw-r--r--arch/arm/cpu/armv7/omap5/clocks.c494
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c596
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c292
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c958
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c214
-rw-r--r--arch/arm/cpu/armv7/start.S19
-rw-r--r--arch/arm/cpu/armv7/tegra20/Makefile1
-rw-r--r--arch/arm/cpu/armv7/tegra20/usb.c567
-rw-r--r--arch/arm/cpu/armv7/zynq/Makefile1
-rw-r--r--arch/arm/cpu/armv7/zynq/cpu.c28
-rw-r--r--arch/arm/cpu/armv7/zynq/slcr.c63
-rw-r--r--arch/arm/cpu/ixp/u-boot.lds14
-rw-r--r--arch/arm/cpu/tegra114-common/pinmux.c410
-rw-r--r--arch/arm/cpu/tegra30-common/pinmux.c190
-rw-r--r--arch/arm/cpu/u-boot-spl.lds93
-rw-r--r--arch/arm/cpu/u-boot.lds15
-rw-r--r--arch/arm/dts/tegra114.dtsi75
-rw-r--r--arch/arm/dts/tegra20.dtsi18
-rw-r--r--arch/arm/dts/tegra30.dtsi124
-rw-r--r--arch/arm/include/asm/arch-am33xx/mmc_host_def.h140
-rw-r--r--arch/arm/include/asm/arch-am33xx/spl.h1
-rw-r--r--arch/arm/include/asm/arch-am33xx/sys_proto.h2
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9x5.h6
-rw-r--r--arch/arm/include/asm/arch-davinci/gpio.h7
-rw-r--r--arch/arm/include/asm/arch-mx35/spl.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h12
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h8
-rw-r--r--arch/arm/include/asm/arch-mx6/iomux.h5
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-ddr.h85
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-pins.h31
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6dl-ddr.h71
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6dl_pins.h193
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6q-ddr.h69
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6q_pins.h1671
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6x_pins.h1671
-rw-r--r--arch/arm/include/asm/arch-mx6/mxc_hdmi.h1083
-rw-r--r--arch/arm/include/asm/arch-mxs/dma.h19
-rw-r--r--arch/arm/include/asm/arch-mxs/imx-regs.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/iomux.h5
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-ssp.h26
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-timrot.h101
-rw-r--r--arch/arm/include/asm/arch-omap3/dss.h31
-rw-r--r--arch/arm/include/asm/arch-omap3/mmc_host_def.h139
-rw-r--r--arch/arm/include/asm/arch-omap3/spl.h2
-rw-r--r--arch/arm/include/asm/arch-omap4/clocks.h562
-rw-r--r--arch/arm/include/asm/arch-omap4/mmc_host_def.h140
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h34
-rw-r--r--arch/arm/include/asm/arch-omap4/spl.h2
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/clocks.h539
-rw-r--r--arch/arm/include/asm/arch-omap5/mmc_host_def.h140
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_dra7xx.h344
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_omap5.h8
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h125
-rw-r--r--arch/arm/include/asm/arch-omap5/spl.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h10
-rw-r--r--arch/arm/include/asm/arch-tegra/mmc.h2
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra_i2c.h6
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra_mmc.h48
-rw-r--r--arch/arm/include/asm/arch-tegra/usb.h (renamed from arch/arm/include/asm/arch-tegra20/usb.h)22
-rw-r--r--arch/arm/include/asm/arch-tegra114/gp_padctrl.h34
-rw-r--r--arch/arm/include/asm/arch-tegra114/pinmux.h246
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra.h1
-rw-r--r--arch/arm/include/asm/arch-tegra30/gp_padctrl.h6
-rw-r--r--arch/arm/include/asm/arch-tegra30/pinmux.h67
-rw-r--r--arch/arm/include/asm/arch-tegra30/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h85
-rw-r--r--arch/arm/include/asm/arch-zynq/sys_proto.h (renamed from arch/arm/cpu/armv7/mx6/lowlevel_init.S)27
-rw-r--r--arch/arm/include/asm/armv7.h1
-rw-r--r--arch/arm/include/asm/emif.h20
-rw-r--r--arch/arm/include/asm/omap_common.h523
-rw-r--r--arch/arm/include/asm/omap_mmc.h168
-rw-r--r--arch/arm/lib/Makefile1
-rw-r--r--arch/arm/lib/bss.c39
-rw-r--r--arch/avr32/cpu/u-boot.lds2
-rw-r--r--arch/blackfin/cpu/u-boot.lds2
-rw-r--r--arch/microblaze/cpu/u-boot.lds2
-rw-r--r--arch/mips/cpu/u-boot.lds2
-rw-r--r--arch/nds32/cpu/n1213/u-boot.lds2
-rw-r--r--arch/nios2/cpu/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/74xx_7xx/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc512x/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc5xx/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds2
-rw-r--r--arch/powerpc/cpu/mpc5xxx/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc8220/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc824x/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc8260/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc83xx/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand.lds2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc86xx/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/ppc4xx/u-boot.lds2
-rw-r--r--arch/sandbox/cpu/u-boot.lds2
-rw-r--r--arch/sh/cpu/sh2/u-boot.lds2
-rw-r--r--arch/sh/cpu/sh3/u-boot.lds2
-rw-r--r--arch/sh/cpu/sh4/u-boot.lds2
-rw-r--r--arch/x86/cpu/u-boot.lds2
-rw-r--r--board/BuS/eb_cpu5282/u-boot.lds2
-rw-r--r--board/LEOX/elpt860/u-boot.lds2
-rw-r--r--board/RPXClassic/u-boot.lds2
-rw-r--r--board/RPXClassic/u-boot.lds.debug2
-rw-r--r--board/RPXlite/u-boot.lds2
-rw-r--r--board/RPXlite/u-boot.lds.debug2
-rw-r--r--board/RPXlite_dw/u-boot.lds2
-rw-r--r--board/RPXlite_dw/u-boot.lds.debug2
-rw-r--r--board/RRvision/u-boot.lds2
-rw-r--r--board/actux1/u-boot.lds24
-rw-r--r--board/actux2/u-boot.lds24
-rw-r--r--board/actux3/u-boot.lds18
-rw-r--r--board/adder/u-boot.lds2
-rw-r--r--board/ait/cam_enc_4xx/u-boot-spl.lds4
-rw-r--r--board/altera/nios2-generic/u-boot.lds2
-rw-r--r--board/amcc/acadia/u-boot-nand.lds2
-rw-r--r--board/amcc/bamboo/u-boot-nand.lds2
-rw-r--r--board/amcc/canyonlands/u-boot-nand.lds2
-rw-r--r--board/amcc/kilauea/u-boot-nand.lds2
-rw-r--r--board/amcc/sequoia/u-boot-nand.lds2
-rw-r--r--board/amcc/sequoia/u-boot-ram.lds2
-rw-r--r--board/astro/mcf5373l/u-boot.lds2
-rw-r--r--board/atmel/at91sam9260ek/at91sam9260ek.c7
-rw-r--r--board/avionic-design/common/tamonten.c19
-rw-r--r--board/avionic-design/dts/tegra20-medcom-wide.dts3
-rw-r--r--board/avionic-design/dts/tegra20-plutux.dts3
-rw-r--r--board/avionic-design/dts/tegra20-tamonten.dtsi489
-rw-r--r--board/avionic-design/dts/tegra20-tec.dts3
-rw-r--r--board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg58
-rw-r--r--board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg58
-rw-r--r--board/boundary/nitrogen6x/6x_bootscript.txt63
-rw-r--r--board/boundary/nitrogen6x/6x_bootscript_android.txt64
-rw-r--r--board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt64
-rw-r--r--board/boundary/nitrogen6x/6x_upgrade.txt45
-rw-r--r--board/boundary/nitrogen6x/800mhz_2x128mx16.cfg58
-rw-r--r--board/boundary/nitrogen6x/800mhz_2x256mx16.cfg58
-rw-r--r--board/boundary/nitrogen6x/800mhz_4x128mx16.cfg57
-rw-r--r--board/boundary/nitrogen6x/800mhz_4x256mx16.cfg58
-rw-r--r--board/boundary/nitrogen6x/Makefile41
-rw-r--r--board/boundary/nitrogen6x/README92
-rw-r--r--board/boundary/nitrogen6x/clocks.cfg46
-rw-r--r--board/boundary/nitrogen6x/ddr-setup.cfg112
-rw-r--r--board/boundary/nitrogen6x/nitrogen6dl.cfg45
-rw-r--r--board/boundary/nitrogen6x/nitrogen6dl2g.cfg45
-rw-r--r--board/boundary/nitrogen6x/nitrogen6q.cfg45
-rw-r--r--board/boundary/nitrogen6x/nitrogen6q2g.cfg45
-rw-r--r--board/boundary/nitrogen6x/nitrogen6s.cfg45
-rw-r--r--board/boundary/nitrogen6x/nitrogen6s1g.cfg45
-rw-r--r--board/boundary/nitrogen6x/nitrogen6x.c895
-rw-r--r--board/cm_t35/Makefile1
-rw-r--r--board/cm_t35/cm_t35.c16
-rw-r--r--board/cm_t35/display.c428
-rw-r--r--board/cobra5272/u-boot.lds2
-rw-r--r--board/cogent/u-boot.lds2
-rw-r--r--board/cogent/u-boot.lds.debug2
-rw-r--r--board/comelit/dig297/dig297.c3
-rw-r--r--board/compal/dts/tegra20-paz00.dts21
-rw-r--r--board/compal/paz00/paz00.c26
-rw-r--r--board/compulab/dts/tegra20-trimslice.dts16
-rw-r--r--board/compulab/trimslice/trimslice.c23
-rw-r--r--board/corscience/tricorder/tricorder.c2
-rw-r--r--board/cray/L1/u-boot.lds.debug2
-rw-r--r--board/dave/PPChameleonEVB/u-boot.lds2
-rw-r--r--board/davinci/da8xxevm/u-boot-spl-da850evm.lds5
-rw-r--r--board/davinci/da8xxevm/u-boot-spl-hawk.lds5
-rw-r--r--board/denx/m28evk/m28evk.c4
-rw-r--r--board/dvlhost/u-boot.lds18
-rw-r--r--board/eltec/mhpc/u-boot.lds2
-rw-r--r--board/eltec/mhpc/u-boot.lds.debug2
-rw-r--r--board/emk/top860/u-boot.lds2
-rw-r--r--board/ep88x/u-boot.lds2
-rw-r--r--board/esd/dasa_sim/u-boot.lds2
-rw-r--r--board/esd/pmc440/u-boot-nand.lds2
-rw-r--r--board/esd/tasreg/u-boot.lds2
-rw-r--r--board/esteem192e/u-boot.lds2
-rw-r--r--board/evb64260/u-boot.lds2
-rw-r--r--board/fads/u-boot.lds2
-rw-r--r--board/flagadm/u-boot.lds2
-rw-r--r--board/flagadm/u-boot.lds.debug2
-rw-r--r--board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg10
-rw-r--r--board/freescale/m5208evbe/u-boot.lds2
-rw-r--r--board/freescale/m52277evb/u-boot.lds2
-rw-r--r--board/freescale/m5235evb/u-boot.lds2
-rw-r--r--board/freescale/m5249evb/u-boot.lds2
-rw-r--r--board/freescale/m5253demo/u-boot.lds2
-rw-r--r--board/freescale/m5253evbe/u-boot.lds2
-rw-r--r--board/freescale/m5271evb/u-boot.lds2
-rw-r--r--board/freescale/m5272c3/u-boot.lds2
-rw-r--r--board/freescale/m5275evb/u-boot.lds2
-rw-r--r--board/freescale/m5282evb/u-boot.lds2
-rw-r--r--board/freescale/m53017evb/u-boot.lds2
-rw-r--r--board/freescale/m5329evb/u-boot.lds2
-rw-r--r--board/freescale/m5373evb/u-boot.lds2
-rw-r--r--board/freescale/m54418twr/u-boot.lds2
-rw-r--r--board/freescale/m54451evb/u-boot.lds2
-rw-r--r--board/freescale/m54455evb/u-boot.lds2
-rw-r--r--board/freescale/m547xevb/u-boot.lds2
-rw-r--r--board/freescale/m548xevb/u-boot.lds2
-rw-r--r--board/freescale/mx23evk/spl_boot.c10
-rw-r--r--board/freescale/mx31ads/u-boot.lds16
-rw-r--r--board/freescale/mx6qarm2/mx6qarm2.c78
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c60
-rw-r--r--board/freescale/mx6qsabrelite/mx6qsabrelite.c292
-rw-r--r--board/freescale/mx6qsabresd/mx6qsabresd.c102
-rw-r--r--board/gaisler/gr_cpci_ax2000/u-boot.lds2
-rw-r--r--board/gaisler/gr_ep2s60/u-boot.lds2
-rw-r--r--board/gaisler/gr_xc3s_1500/u-boot.lds2
-rw-r--r--board/gaisler/grsim/u-boot.lds2
-rw-r--r--board/gaisler/grsim_leon2/u-boot.lds2
-rw-r--r--board/gen860t/u-boot-flashenv.lds2
-rw-r--r--board/gen860t/u-boot.lds2
-rw-r--r--board/genietv/u-boot.lds2
-rw-r--r--board/genietv/u-boot.lds.debug2
-rw-r--r--board/hermes/u-boot.lds2
-rw-r--r--board/hermes/u-boot.lds.debug2
-rw-r--r--board/htkw/mcx/mcx.c3
-rw-r--r--board/hymod/u-boot.lds2
-rw-r--r--board/hymod/u-boot.lds.debug2
-rw-r--r--board/icu862/u-boot.lds2
-rw-r--r--board/icu862/u-boot.lds.debug2
-rw-r--r--board/idmr/u-boot.lds2
-rw-r--r--board/ip860/u-boot.lds2
-rw-r--r--board/ip860/u-boot.lds.debug2
-rw-r--r--board/isee/igep00x0/igep00x0.c3
-rw-r--r--board/isee/igep00x0/igep00x0.h7
-rw-r--r--board/ivm/u-boot.lds2
-rw-r--r--board/ivm/u-boot.lds.debug2
-rw-r--r--board/korat/u-boot-F7FC.lds2
-rw-r--r--board/kup/kup4k/u-boot.lds2
-rw-r--r--board/kup/kup4k/u-boot.lds.debug2
-rw-r--r--board/kup/kup4x/u-boot.lds2
-rw-r--r--board/kup/kup4x/u-boot.lds.debug2
-rw-r--r--board/logicpd/am3517evm/am3517evm.c3
-rw-r--r--board/logicpd/omap3som/omap3logic.c2
-rw-r--r--board/logicpd/zoom1/zoom1.c3
-rw-r--r--board/logicpd/zoom2/zoom2.c3
-rw-r--r--board/lwmon/u-boot.lds2
-rw-r--r--board/lwmon/u-boot.lds.debug2
-rw-r--r--board/manroland/uc100/u-boot.lds2
-rw-r--r--board/matrix_vision/mvblx/fpga.c14
-rw-r--r--board/matrix_vision/mvblx/mvblx.c4
-rw-r--r--board/matrix_vision/mvblx/sys_eeprom.c24
-rw-r--r--board/matrix_vision/mvsmr/u-boot.lds2
-rw-r--r--board/mbx8xx/u-boot.lds2
-rw-r--r--board/mbx8xx/u-boot.lds.debug2
-rw-r--r--board/mousse/u-boot.lds2
-rw-r--r--board/mpl/pip405/u-boot.lds.debug2
-rw-r--r--board/mvblue/u-boot.lds2
-rw-r--r--board/netphone/u-boot.lds2
-rw-r--r--board/netphone/u-boot.lds.debug2
-rw-r--r--board/netta/u-boot.lds2
-rw-r--r--board/netta/u-boot.lds.debug2
-rw-r--r--board/netta2/u-boot.lds2
-rw-r--r--board/netta2/u-boot.lds.debug2
-rw-r--r--board/netvia/u-boot.lds2
-rw-r--r--board/netvia/u-boot.lds.debug2
-rw-r--r--board/nokia/rx51/rx51.c4
-rw-r--r--board/ns9750dev/config.mk16
-rw-r--r--board/ns9750dev/flash.c474
-rw-r--r--board/ns9750dev/led.c46
-rw-r--r--board/ns9750dev/lowlevel_init.S298
-rw-r--r--board/ns9750dev/ns9750dev.c125
-rw-r--r--board/nvidia/cardhu/cardhu.c57
-rw-r--r--board/nvidia/cardhu/cardhu.c.mmc151
-rw-r--r--board/nvidia/cardhu/pinmux-config-cardhu.h21
-rw-r--r--board/nvidia/common/board.c56
-rw-r--r--board/nvidia/dalmore/dalmore.c3
-rw-r--r--board/nvidia/dalmore/pinmux-config-dalmore.h475
-rw-r--r--board/nvidia/dts/tegra114-dalmore.dts35
-rw-r--r--board/nvidia/dts/tegra20-harmony.dts20
-rw-r--r--board/nvidia/dts/tegra20-seaboard.dts15
-rw-r--r--board/nvidia/dts/tegra20-ventana.dts17
-rw-r--r--board/nvidia/dts/tegra20-whistler.dts15
-rw-r--r--board/nvidia/dts/tegra30-cardhu.dts23
-rw-r--r--board/nvidia/harmony/harmony.c26
-rw-r--r--board/nvidia/seaboard/seaboard.c25
-rw-r--r--board/nvidia/whistler/whistler.c30
-rw-r--r--board/nx823/u-boot.lds2
-rw-r--r--board/nx823/u-boot.lds.debug2
-rw-r--r--board/olimex/mx23_olinuxino/mx23_olinuxino.c13
-rw-r--r--board/olimex/mx23_olinuxino/spl_boot.c8
-rw-r--r--board/openrisc/openrisc-generic/u-boot.lds2
-rw-r--r--board/overo/overo.c3
-rw-r--r--board/pandora/pandora.c3
-rw-r--r--board/phytec/pcm051/mux.c1
-rw-r--r--board/quantum/u-boot.lds2
-rw-r--r--board/r360mpi/u-boot.lds2
-rw-r--r--board/rbc823/u-boot.lds2
-rw-r--r--board/renesas/sh7752evb/u-boot.lds2
-rw-r--r--board/renesas/sh7757lcr/u-boot.lds2
-rw-r--r--board/rsdproto/u-boot.lds2
-rw-r--r--board/samsung/smdk5250/smdk5250-uboot-spl.lds2
-rw-r--r--board/samsung/smdk6400/u-boot-nand.lds2
-rw-r--r--board/sandburst/karef/u-boot.lds.debug2
-rw-r--r--board/sandburst/metrobox/u-boot.lds.debug2
-rw-r--r--board/sandpoint/u-boot.lds2
-rw-r--r--board/sixnet/u-boot.lds2
-rw-r--r--board/snmc/qs850/u-boot.lds2
-rw-r--r--board/snmc/qs860t/u-boot.lds2
-rw-r--r--board/spc1920/u-boot.lds2
-rw-r--r--board/spd8xx/u-boot.lds2
-rw-r--r--board/spd8xx/u-boot.lds.debug2
-rw-r--r--board/stx/stxxtc/u-boot.lds2
-rw-r--r--board/stx/stxxtc/u-boot.lds.debug2
-rw-r--r--board/svm_sc8xx/u-boot.lds2
-rw-r--r--board/technexion/twister/twister.c2
-rw-r--r--board/teejet/mt_ventoux/mt_ventoux.c4
-rw-r--r--board/ti/am335x/board.c40
-rw-r--r--board/ti/am3517crane/am3517crane.c3
-rw-r--r--board/ti/beagle/beagle.c17
-rw-r--r--board/ti/beagle/beagle.h6
-rw-r--r--board/ti/dra7xx/Makefile (renamed from board/ns9750dev/Makefile)22
-rw-r--r--board/ti/dra7xx/evm.c103
-rw-r--r--board/ti/dra7xx/mux_data.h47
-rw-r--r--board/ti/evm/evm.c3
-rw-r--r--board/ti/omap5_evm/evm.c4
-rw-r--r--board/ti/panda/panda.c3
-rw-r--r--board/ti/sdp3430/sdp.c3
-rw-r--r--board/ti/sdp4430/sdp.c4
-rw-r--r--board/timll/devkit8000/devkit8000.c3
-rw-r--r--board/toradex/colibri_t20_iris/colibri_t20_iris.c11
-rw-r--r--board/toradex/dts/tegra20-colibri_t20_iris.dts9
-rw-r--r--board/tqc/tqm8xx/u-boot.lds2
-rw-r--r--board/v37/u-boot.lds2
-rw-r--r--board/vpac270/u-boot-spl.lds4
-rw-r--r--board/w7o/u-boot.lds.debug2
-rw-r--r--board/xes/xpedite1000/u-boot.lds.debug2
-rw-r--r--boards.cfg12
-rw-r--r--common/cmd_help.c2
-rw-r--r--common/cmd_led.c6
-rw-r--r--common/cmd_mmc.c7
-rw-r--r--common/cmd_sata.c2
-rw-r--r--common/lcd.c41
-rw-r--r--common/spl/Makefile1
-rw-r--r--common/spl/spl.c10
-rw-r--r--common/spl/spl_onenand.c47
-rw-r--r--config.mk2
-rw-r--r--disk/part.c10
-rw-r--r--disk/part_amiga.c6
-rw-r--r--disk/part_dos.c7
-rw-r--r--disk/part_efi.c8
-rw-r--r--disk/part_iso.c7
-rw-r--r--disk/part_mac.c7
-rw-r--r--doc/README.commands18
-rw-r--r--doc/README.displaying-bmps27
-rw-r--r--doc/README.ns9750dev36
-rw-r--r--doc/README.scrapyard163
-rw-r--r--doc/SPL/README.am335x-network92
-rw-r--r--doc/driver-model/UDM-serial.txt2
-rw-r--r--drivers/gpio/da8xx_gpio.c137
-rw-r--r--drivers/i2c/tegra_i2c.c42
-rw-r--r--drivers/mmc/arm_pl180_mmci.c1
-rw-r--r--drivers/mmc/bfin_sdh.c1
-rw-r--r--drivers/mmc/davinci_mmc.c1
-rw-r--r--drivers/mmc/fsl_esdhc.c1
-rw-r--r--drivers/mmc/ftsdc010_esdhc.c1
-rw-r--r--drivers/mmc/gen_atmel_mci.c1
-rw-r--r--drivers/mmc/mmc.c17
-rw-r--r--drivers/mmc/mmc_spi.c1
-rw-r--r--drivers/mmc/mxcmmc.c1
-rw-r--r--drivers/mmc/mxsmmc.c21
-rw-r--r--drivers/mmc/omap_hsmmc.c103
-rw-r--r--drivers/mmc/sdhci.c1
-rw-r--r--drivers/mmc/sh_mmcif.c1
-rw-r--r--drivers/mmc/tegra_mmc.c227
-rw-r--r--drivers/mtd/onenand/onenand_spl.c14
-rw-r--r--drivers/net/cpsw.c20
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/ns9750_serial.c218
-rw-r--r--drivers/serial/serial.c2
-rw-r--r--drivers/spi/mxs_spi.c39
-rw-r--r--drivers/usb/host/ehci-mx6.c1
-rw-r--r--drivers/usb/host/ehci-mxs.c155
-rw-r--r--drivers/usb/host/ehci-tegra.c546
-rw-r--r--drivers/video/omap3_dss.c2
-rw-r--r--dts/Makefile3
-rw-r--r--helper.mk64
-rw-r--r--include/command.h2
-rw-r--r--include/config_fallbacks.h11
-rw-r--r--include/configs/am335x_evm.h85
-rw-r--r--include/configs/apx4devkit.h3
-rw-r--r--include/configs/at91rm9200ek.h3
-rw-r--r--include/configs/at91sam9260ek.h23
-rw-r--r--include/configs/at91sam9261ek.h19
-rw-r--r--include/configs/at91sam9263ek.h20
-rw-r--r--include/configs/at91sam9m10g45ek.h17
-rw-r--r--include/configs/at91sam9rlek.h3
-rw-r--r--include/configs/at91sam9x5ek.h12
-rw-r--r--include/configs/cardhu.h12
-rw-r--r--include/configs/cm_t35.h9
-rw-r--r--include/configs/colibri_t20_iris.h6
-rw-r--r--include/configs/dalmore.h9
-rw-r--r--include/configs/dra7xx_evm.h36
-rw-r--r--include/configs/ea20.h1
-rw-r--r--include/configs/harmony.h8
-rw-r--r--include/configs/igep00x0.h7
-rw-r--r--include/configs/m28evk.h5
-rw-r--r--include/configs/medcom-wide.h5
-rw-r--r--include/configs/mx23_olinuxino.h64
-rw-r--r--include/configs/mx23evk.h14
-rw-r--r--include/configs/mx28evk.h4
-rw-r--r--include/configs/mx6_common.h23
-rw-r--r--include/configs/mx6qarm2.h3
-rw-r--r--include/configs/mx6qsabre_common.h4
-rw-r--r--include/configs/mx6qsabrelite.h4
-rw-r--r--include/configs/nitrogen6x.h285
-rw-r--r--include/configs/ns9750dev.h187
-rw-r--r--include/configs/omap3_beagle.h3
-rw-r--r--include/configs/omap3_mvblx.h25
-rw-r--r--include/configs/omap4_common.h2
-rw-r--r--include/configs/omap5_common.h262
-rw-r--r--include/configs/omap5_evm.h240
-rw-r--r--include/configs/paz00.h8
-rw-r--r--include/configs/pcm051.h2
-rw-r--r--include/configs/plutux.h5
-rw-r--r--include/configs/sc_sps_1.h3
-rw-r--r--include/configs/seaboard.h8
-rw-r--r--include/configs/tec.h5
-rw-r--r--include/configs/tegra-common.h22
-rw-r--r--include/configs/tegra114-common.h3
-rw-r--r--include/configs/tegra20-common.h12
-rw-r--r--include/configs/tegra30-common.h6
-rw-r--r--include/configs/trimslice.h8
-rw-r--r--include/configs/ventana.h8
-rw-r--r--include/configs/whistler.h8
-rw-r--r--include/configs/zynq.h5
-rw-r--r--include/env_callback.h9
-rw-r--r--include/fdtdec.h3
-rw-r--r--include/lcd.h1
-rw-r--r--include/linker_lists.h252
-rw-r--r--include/mmc.h2
-rw-r--r--include/ns9750_bbus.h125
-rw-r--r--include/ns9750_mem.h172
-rw-r--r--include/ns9750_ser.h202
-rw-r--r--include/ns9750_sys.h215
-rw-r--r--include/spl.h3
-rw-r--r--lib/fdtdec.c3
-rw-r--r--nand_spl/board/freescale/mpc8536ds/Makefile7
-rw-r--r--nand_spl/board/freescale/mpc8569mds/Makefile7
-rw-r--r--nand_spl/board/freescale/mpc8572ds/Makefile7
-rw-r--r--nand_spl/board/freescale/mx31pdk/Makefile7
-rw-r--r--nand_spl/board/freescale/mx31pdk/u-boot.lds2
-rw-r--r--nand_spl/board/freescale/p1010rdb/Makefile7
-rw-r--r--nand_spl/board/freescale/p1023rds/Makefile7
-rw-r--r--nand_spl/board/freescale/p1_p2_rdb/Makefile7
-rw-r--r--nand_spl/board/karo/tx25/Makefile7
-rw-r--r--nand_spl/board/karo/tx25/u-boot.lds2
-rw-r--r--nand_spl/board/samsung/smdk6400/u-boot.lds2
-rw-r--r--spl/.gitignore1
-rw-r--r--spl/Makefile10
486 files changed, 15588 insertions, 10407 deletions
diff --git a/.gitignore b/.gitignore
index e40eb7b669..be09894a0b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -44,7 +44,6 @@
/u-boot.dtb
/u-boot.sb
/u-boot.geany
-/include/u-boot.lst
#
# Generated files
diff --git a/MAINTAINERS b/MAINTAINERS
index 6b1f657b7d..d031c3a9df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -606,6 +606,7 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>
igep0020 ARM ARMV7 (OMAP3xx SoC)
igep0030 ARM ARMV7 (OMAP3xx SoC)
+ igep0032 ARM ARMV7 (OMAP3xx SoC)
Eric Benard <eric@eukrea.com>
@@ -974,6 +975,8 @@ Tom Warren <twarren@nvidia.com>
harmony Tegra20 (ARM7 & A9 Dual Core)
seaboard Tegra20 (ARM7 & A9 Dual Core)
+ cardhu Tegra30 (ARM7 & A9 Quad Core)
+ dalmore Tegra114 (ARM7 & A15 Quad Core)
Tom Warren <twarren@nvidia.com>
Stephen Warren <swarren@nvidia.com>
@@ -1035,6 +1038,14 @@ Pali Rohár <pali.rohar@gmail.com>
nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
+Eric Nelson <eric.nelson@boundarydevices.com>
+ nitrogen6dl i.MX6DL 1GB
+ nitrogen6dl2g i.MX6DL 2GB
+ nitrogen6q i.MX6Q/6D 1GB
+ nitrogen6q2g i.MX6Q/6D 2GB
+ nitrogen6s i.MX6S 512MB
+ nitrogen6s1g i.MX6S 1GB
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/Makefile b/Makefile
index 55bd55c8c0..12763ce0f9 100644
--- a/Makefile
+++ b/Makefile
@@ -464,8 +464,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
-$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
- $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
+$(obj)u-boot.imx: $(obj)u-boot.bin depend
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
@@ -556,10 +556,8 @@ GEN_UBOOT = \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
else
GEN_UBOOT = \
- UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
- sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
- $$UNDEF_LST $(__OBJS) \
+ $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
endif
@@ -592,11 +590,7 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
-# The following line expands into whole rule which generates u-boot.lst,
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
-$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
@@ -832,7 +826,6 @@ clean:
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
$(obj)u-boot.lds \
- $(obj)include/u-boot.lst \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@@ -870,7 +863,7 @@ clobber: tidy
@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
- @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
+ @rm -f $(obj)spl/u-boot-spl.lds
@rm -f $(obj)MLO MLO.byteswap
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
diff --git a/README b/README
index a620f0a474..7f2506a9b9 100644
--- a/README
+++ b/README
@@ -485,6 +485,16 @@ The following options need to be configured:
Thumb2 this flag will result in Thumb2 code generated by
GCC.
+ CONFIG_ARM_ERRATA_742230
+ CONFIG_ARM_ERRATA_743622
+ CONFIG_ARM_ERRATA_751472
+
+ If set, the workarounds for these ARM errata are applied early
+ during U-Boot startup. Note that these options force the
+ workarounds to be applied; no CPU-type/version detection
+ exists, unlike the similar options in the Linux kernel. Do not
+ set these options unless they apply!
+
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
@@ -1533,6 +1543,17 @@ CBFS (Coreboot Filesystem) support
allows for a "silent" boot where a splash screen is
loaded very quickly after power-on.
+ CONFIG_SPLASHIMAGE_GUARD
+
+ If this option is set, then U-Boot will prevent the environment
+ variable "splashimage" from being set to a problematic address
+ (see README.displaying-bmps and README.arm-unaligned-accesses).
+ This option is useful for targets where, due to alignment
+ restrictions, an improperly aligned BMP image will cause a data
+ abort. If you think you will not have problems with unaligned
+ accesses (for example because your toolchain prevents them)
+ there is no need to set this option.
+
CONFIG_SPLASH_SCREEN_ALIGN
If this option is set the splash image can be freely positioned
@@ -1553,6 +1574,14 @@ CBFS (Coreboot Filesystem) support
=> vertically centered image
at x = dspWidth - bmpWidth - 9
+ CONFIG_SPLASH_SCREEN_PREPARE
+
+ If this option is set then the board_splash_screen_prepare()
+ function, which must be defined in your code, is called as part
+ of the splash screen display sequence. It gives the board an
+ opportunity to prepare the splash image data before it is
+ processed and sent to the frame buffer by U-Boot.
+
- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
If this option is set, additionally to standard BMP
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index d11e6f6270..46f4b64ff4 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -519,7 +519,7 @@ u32 spl_boot_device(void)
case RCSR_MEM_TYPE_NOR:
return BOOT_DEVICE_NOR;
case RCSR_MEM_TYPE_ONENAND:
- return BOOT_DEVICE_ONE_NAND;
+ return BOOT_DEVICE_ONENAND;
default:
return BOOT_DEVICE_NONE;
}
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 5962e15b4f..6a94179d4a 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -201,6 +201,7 @@ void t114_init_clocks(void)
reset_set_enable(PERIPH_ID_MSELECT, 0);
reset_set_enable(PERIPH_ID_EMC1, 0);
reset_set_enable(PERIPH_ID_MC1, 0);
+ reset_set_enable(PERIPH_ID_DVFS, 0);
debug("t114_init_clocks exit\n");
}
@@ -269,6 +270,8 @@ void powerup_cpus(void)
void start_cpu(u32 reset_vector)
{
+ u32 imme, inst;
+
debug("start_cpu entry, reset_vector = %x\n", reset_vector);
t114_init_clocks();
@@ -285,12 +288,38 @@ void start_cpu(u32 reset_vector)
/* Take CPU(s) out of reset */
remove_cpu_resets();
+ /* Set the entry point for CPU execution from reset */
+
/*
- * Set the entry point for CPU execution from reset,
- * if it's a non-zero value.
+ * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
+ * See nvbug 1193357 for details.
*/
- if (reset_vector)
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+ /* mov r0, #lsb(reset_vector) */
+ imme = reset_vector & 0xffff;
+ inst = imme & 0xfff;
+ inst |= ((imme >> 12) << 16);
+ inst |= 0xe3000000;
+ writel(inst, 0x4003fff0);
+
+ /* movt r0, #msb(reset_vector) */
+ imme = (reset_vector >> 16) & 0xffff;
+ inst = imme & 0xfff;
+ inst |= ((imme >> 12) << 16);
+ inst |= 0xe3400000;
+ writel(inst, 0x4003fff4);
+
+ /* bx r0 */
+ writel(0xe12fff10, 0x4003fff8);
+
+ /* b -12 */
+ imme = (u32)-20;
+ inst = (imme >> 2) & 0xffffff;
+ inst |= 0xea000000;
+ writel(inst, 0x4003fffc);
+
+ /* Write to orignal location for compatibility */
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
/* If the CPU(s) don't already have power, power 'em up */
powerup_cpus();
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index 25d2a32631..e483820f3f 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -51,7 +51,7 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
index 0448c0b133..92185460a1 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -61,20 +61,20 @@ char *get_cpu_name()
if (cpu_is_at91sam9x5()) {
switch (extension_id) {
case ARCH_EXID_AT91SAM9G15:
- return CONFIG_SYS_AT91_G15_CPU_NAME;
+ return "AT91SAM9G15";
case ARCH_EXID_AT91SAM9G25:
- return CONFIG_SYS_AT91_G25_CPU_NAME;
+ return "AT91SAM9G25";
case ARCH_EXID_AT91SAM9G35:
- return CONFIG_SYS_AT91_G35_CPU_NAME;
+ return "AT91SAM9G35";
case ARCH_EXID_AT91SAM9X25:
- return CONFIG_SYS_AT91_X25_CPU_NAME;
+ return "AT91SAM9X25";
case ARCH_EXID_AT91SAM9X35:
- return CONFIG_SYS_AT91_X35_CPU_NAME;
+ return "AT91SAM9X35";
default:
- return CONFIG_SYS_AT91_UNKNOWN_CPU;
+ return "Unknown CPU type";
}
} else {
- return CONFIG_SYS_AT91_UNKNOWN_CPU;
+ return "Unknown CPU type";
}
}
@@ -246,14 +246,14 @@ void at91_macb_hw_init(void)
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
- at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index 47f24f580e..6a3a1bb354 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
-ALL-y += $(OBJTREE)/u-boot.imx
+ALL-y += $(obj)u-boot.imx
endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 00b9aba457..43e766334c 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -289,7 +289,8 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mxs_ssp_regs *ssp_regs;
- const uint32_t sspclk = mxs_get_sspclk(bus);
+ const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
+ const uint32_t sspclk = mxs_get_sspclk(clk);
uint32_t reg;
uint32_t divide, rate, tgtclk;
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
index 2ddc5bc0c6..084def5b12 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
@@ -30,7 +30,7 @@ void early_delay(int delay);
void mxs_power_init(void);
-#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
void mxs_power_wait_pswitch(void);
#else
static inline void mxs_power_wait_pswitch(void) { }
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index f8392f6398..fdac73cfaa 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -27,6 +27,7 @@
#include <config.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
#include <linux/compiler.h>
#include "mxs_init.h"
@@ -119,6 +120,10 @@ static void initialize_dram_values(void)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
#ifdef CONFIG_MX23
+ /*
+ * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
+ * element to be set
+ */
writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
#endif
}
@@ -229,7 +234,7 @@ static void mx23_mem_setup_vddmem(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
- writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+ writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_ILIMIT |
POWER_VDDMEMCTRL_ENABLE_LINREG |
POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
@@ -237,13 +242,20 @@ static void mx23_mem_setup_vddmem(void)
early_delay(10000);
- writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+ writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_LINREG,
&power_regs->hw_power_vddmemctrl);
}
static void mx23_mem_init(void)
{
+ /*
+ * Reset/ungate the EMI block. This is essential, otherwise the system
+ * suffers from memory instability. This thing is mx23 specific and is
+ * no longer present on mx28.
+ */
+ mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
+
mx23_mem_setup_vddmem();
/*
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index e9d6302b7a..287c698ff7 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -921,7 +921,7 @@ void mxs_power_init(void)
early_delay(1000);
}
-#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
void mxs_power_wait_pswitch(void)
{
struct mxs_power_regs *power_regs =
diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index 373841180f..2039106e40 100644
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -32,7 +32,11 @@
#include <asm/arch/sys_proto.h>
/* Maximum fixed count */
-#define TIMER_LOAD_VAL 0xffffffff
+#if defined(CONFIG_MX23)
+#define TIMER_LOAD_VAL 0xffff
+#elif defined(CONFIG_MX28)
+#define TIMER_LOAD_VAL 0xffffffff
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -42,22 +46,22 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* This driver uses 1kHz clock source.
*/
-#define MX28_INCREMENTER_HZ 1000
+#define MXS_INCREMENTER_HZ 1000
static inline unsigned long tick_to_time(unsigned long tick)
{
- return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
+ return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
static inline unsigned long time_to_tick(unsigned long time)
{
- return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
+ return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
/* Calculate how many ticks happen in "us" microseconds */
static inline unsigned long us_to_tick(unsigned long us)
{
- return (us * MX28_INCREMENTER_HZ) / 1000000;
+ return (us * MXS_INCREMENTER_HZ) / 1000000;
}
int timer_init(void)
@@ -69,7 +73,11 @@ int timer_init(void)
mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */
+#if defined(CONFIG_MX23)
+ writel(0, &timrot_regs->hw_timrot_timcount0);
+#elif defined(CONFIG_MX28)
writel(0, &timrot_regs->hw_timrot_fixed_count0);
+#endif
/* Set UPDATE bit and 1Khz frequency */
writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
@@ -77,7 +85,11 @@ int timer_init(void)
&timrot_regs->hw_timrot_timctrl0);
/* Set fixed_count to maximal value */
+#if defined(CONFIG_MX23)
+ writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
+#elif defined(CONFIG_MX28)
writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
+#endif
return 0;
}
@@ -86,9 +98,16 @@ unsigned long long get_ticks(void)
{
struct mxs_timrot_regs *timrot_regs =
(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
+ uint32_t now;
/* Current tick value */
- uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
+#if defined(CONFIG_MX23)
+ /* Upper bits are the valid ones. */
+ now = readl(&timrot_regs->hw_timrot_timcount0) >>
+ TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
+#elif defined(CONFIG_MX28)
+ now = readl(&timrot_regs->hw_timrot_running_count0);
+#endif
if (lastdec >= now) {
/*
@@ -117,17 +136,17 @@ ulong get_timer(ulong base)
}
/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
-#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0
+#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0
void __udelay(unsigned long usec)
{
uint32_t old, new, incr;
uint32_t counter = 0;
- old = readl(MX28_HW_DIGCTL_MICROSECONDS);
+ old = readl(MXS_HW_DIGCTL_MICROSECONDS);
while (counter < usec) {
- new = readl(MX28_HW_DIGCTL_MICROSECONDS);
+ new = readl(MXS_HW_DIGCTL_MICROSECONDS);
/* Check if the timer wrapped. */
if (new < old) {
@@ -152,5 +171,5 @@ void __udelay(unsigned long usec)
ulong get_tbclk(void)
{
- return MX28_INCREMENTER_HZ;
+ return MXS_INCREMENTER_HZ;
}
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index fc0418afd1..67b204e447 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -51,12 +51,6 @@ SECTIONS
. = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- . = ALIGN(4);
-
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index cff660a7d7..7405917595 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -51,12 +51,6 @@ SECTIONS
. = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- . = ALIGN(4);
-
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ee8c2b3fa5..4668b3cf2f 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index ab313265d0..e35a3e3a70 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -56,11 +56,11 @@ int cpu_mmc_init(bd_t *bis)
{
int ret;
- ret = omap_mmc_init(0, 0, 0);
+ ret = omap_mmc_init(0, 0, 0, -1, -1);
if (ret)
return ret;
- return omap_mmc_init(1, 0, 0);
+ return omap_mmc_init(1, 0, 0, -1, -1);
}
#endif
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fd9fc4a720..448cc40157 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -45,13 +45,19 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
*/
void config_sdram(const struct emif_regs *regs)
{
- writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
- if (regs->zq_config){
+ if (regs->zq_config) {
+ /*
+ * A value of 0x2800 for the REF CTRL will give us
+ * about 570us for a delay, which will be long enough
+ * to configure things.
+ */
+ writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
}
writel(regs->sdram_config, &emif_reg->emif_sdram_config);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
}
/**
diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
new file mode 100644
index 0000000000..b6a929ff7e
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } >.sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sdram
+}
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index 350e946392..9c3e2f3ce4 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -40,5 +40,5 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
-ALL-y += $(OBJTREE)/u-boot.imx
+ALL-y += $(obj)u-boot.imx
endif
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index cbce411cca..4f9ca6890c 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o
-SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a8aad5dd0a..193ba1240f 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+#include <stdbool.h>
struct scu_regs {
u32 ctrl;
@@ -121,12 +122,23 @@ void set_vddsoc(u32 mv)
writel(reg, &anatop->reg_core);
}
+static void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+}
+
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
+ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
return 0;
}
@@ -193,3 +205,7 @@ const struct boot_mode soc_boot_modes[] = {
{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
+
+void s_init(void)
+{
+}
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 2b584e0a53..24cbe2da05 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -55,17 +55,20 @@ void spl_board_init(void)
#ifdef CONFIG_SPL_NAND_SUPPORT
gpmc_init();
#endif
+#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
+ arch_misc_init();
+#endif
}
int board_mmc_init(bd_t *bis)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
- omap_mmc_init(0, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
break;
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(1, 0, 0, -1, -1);
break;
}
return 0;
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index b1fd277d6d..9ed18995ea 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -36,6 +36,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
+#include <asm/emif.h>
#ifndef CONFIG_SPL_BUILD
/*
@@ -46,9 +47,20 @@
#define puts(s)
#endif
+const u32 sys_clk_array[8] = {
+ 12000000, /* 12 MHz */
+ 13000000, /* 13 MHz */
+ 16800000, /* 16.8 MHz */
+ 19200000, /* 19.2 MHz */
+ 26000000, /* 26 MHz */
+ 27000000, /* 27 MHz */
+ 38400000, /* 38.4 MHz */
+ 20000000, /* 20 MHz */
+};
+
static inline u32 __get_sys_clk_index(void)
{
- u32 ind;
+ s8 ind;
/*
* For ES1 the ROM code calibration of sys clock is not reliable
* due to hw issue. So, use hard-coded value. If this value is not
@@ -60,8 +72,15 @@ static inline u32 __get_sys_clk_index(void)
ind = OMAP_SYS_CLK_IND_38_4_MHZ;
else {
/* SYS_CLKSEL - 1 to match the dpll param array indices */
- ind = (readl(&prcm->cm_sys_clksel) &
+ ind = (readl((*prcm)->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+ /*
+ * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
+ * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
+ * NUM_SYS_CLK. So considering the last 3 bits as the index
+ * for the dpll param array.
+ */
+ ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
@@ -75,7 +94,34 @@ u32 get_sys_clk_freq(void)
return sys_clk_array[index];
}
-static inline void do_bypass_dpll(u32 *const base)
+void setup_post_dividers(u32 const base, const struct dpll_params *params)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+ if (params->m4_h11 >= 0)
+ writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
+ if (params->m5_h12 >= 0)
+ writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
+ if (params->m6_h13 >= 0)
+ writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
+ if (params->m7_h14 >= 0)
+ writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
+ if (params->h21 >= 0)
+ writel(params->h21, &dpll_regs->cm_div_h21_dpll);
+ if (params->h22 >= 0)
+ writel(params->h22, &dpll_regs->cm_div_h22_dpll);
+ if (params->h23 >= 0)
+ writel(params->h23, &dpll_regs->cm_div_h23_dpll);
+ if (params->h24 >= 0)
+ writel(params->h24, &dpll_regs->cm_div_h24_dpll);
+}
+
+static inline void do_bypass_dpll(u32 const base)
{
struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
@@ -85,17 +131,17 @@ static inline void do_bypass_dpll(u32 *const base)
CM_CLKMODE_DPLL_EN_SHIFT);
}
-static inline void wait_for_bypass(u32 *const base)
+static inline void wait_for_bypass(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
LDELAY)) {
- printf("Bypassing DPLL failed %p\n", base);
+ printf("Bypassing DPLL failed %x\n", base);
}
}
-static inline void do_lock_dpll(u32 *const base)
+static inline void do_lock_dpll(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
@@ -104,18 +150,18 @@ static inline void do_lock_dpll(u32 *const base)
DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
}
-static inline void wait_for_lock(u32 *const base)
+static inline void wait_for_lock(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
&dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("DPLL locking failed for %p\n", base);
+ printf("DPLL locking failed for %x\n", base);
hang();
}
}
-inline u32 check_for_lock(u32 *const base)
+inline u32 check_for_lock(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
@@ -123,12 +169,65 @@ inline u32 check_for_lock(u32 *const base)
return lock;
}
-static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->mpu[sysclk_ind];
+}
+
+const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->core[sysclk_ind];
+}
+
+const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->per[sysclk_ind];
+}
+
+const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->iva[sysclk_ind];
+}
+
+const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->usb[sysclk_ind];
+}
+
+const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
+{
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->abe[sysclk_ind];
+#else
+ return dpll_data->abe;
+#endif
+}
+
+static const struct dpll_params *get_ddr_dpll_params
+ (struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ if (!dpll_data->ddr)
+ return NULL;
+ return &dpll_data->ddr[sysclk_ind];
+}
+
+static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+ if (!params)
+ return;
+
temp = readl(&dpll_regs->cm_clksel_dpll);
if (check_for_lock(base)) {
@@ -183,7 +282,7 @@ u32 omap_ddr_clk(void)
omap_rev = omap_revision();
sys_clk_khz = get_sys_clk_freq() / 1000;
- core_dpll_params = get_core_dpll_params();
+ core_dpll_params = get_core_dpll_params(*dplls_data);
debug("sys_clk %d\n ", sys_clk_khz * 1000);
@@ -235,24 +334,19 @@ void configure_mpu_dpll(void)
*/
if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
mpu_dpll_regs =
- (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
- bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
- clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+ (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
+ bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
+ clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
- setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+ setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
CM_CLKSEL_DCC_EN_MASK);
}
- setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
- setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+ params = get_mpu_dpll_params(*dplls_data);
- params = get_mpu_dpll_params();
-
- do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
debug("MPU DPLL locked\n");
}
@@ -271,17 +365,17 @@ static void setup_usb_dpll(void)
* Use CLKINP in KHz and adjust the denominator accordingly so
* that we have enough accuracy and at the same time no overflow
*/
- params = get_usb_dpll_params();
+ params = get_usb_dpll_params(*dplls_data);
num = params->m * sys_clk_khz;
den = (params->n + 1) * 250 * 1000;
num += den - 1;
sd_div = num / den;
- clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+ clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
/* Now setup the dpll with the regular function */
- do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
}
#endif
@@ -293,28 +387,28 @@ static void setup_dplls(void)
debug("setup_dplls\n");
/* CORE dpll */
- params = get_core_dpll_params(); /* default - safest */
+ params = get_core_dpll_params(*dplls_data); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
- if (omap_revision() != OMAP5432_ES1_0)
- do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else
- do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_LOCK, "core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
- writel(temp, &prcm->cm_clksel_core);
+ writel(temp, (*prcm)->cm_clksel_core);
debug("Core DPLL configured\n");
/* lock PER dpll */
- params = get_per_dpll_params();
- do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+ params = get_per_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
params, DPLL_LOCK, "per");
debug("PER DPLL locked\n");
@@ -324,6 +418,9 @@ static void setup_dplls(void)
#ifdef CONFIG_USB_EHCI_OMAP
setup_usb_dpll();
#endif
+ params = get_ddr_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
+ params, DPLL_LOCK, "ddr");
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
@@ -333,14 +430,14 @@ static void setup_non_essential_dplls(void)
const struct dpll_params *params;
/* IVA */
- clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+ clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
- params = get_iva_dpll_params();
- do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
+ params = get_iva_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
/* Configure ABE dpll */
- params = get_abe_dpll_params();
+ params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#else
@@ -349,64 +446,65 @@ static void setup_non_essential_dplls(void)
* We need to enable some additional options to achieve
* 196.608MHz from 32768 Hz
*/
- setbits_le32(&prcm->cm_clkmode_dpll_abe,
+ setbits_le32((*prcm)->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
CM_CLKMODE_DPLL_LPMODE_EN_MASK|
CM_CLKMODE_DPLL_REGM4XEN_MASK);
/* Spend 4 REFCLK cycles at each stage */
- clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+ clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_RAMP_RATE_MASK,
1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
#endif
/* Select the right reference clk */
- clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+ clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
/* Lock the dpll */
- do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
}
#endif
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
{
- u32 step;
- int ret = 0;
-
- /* See if we can first get the GPIO if needed */
- if (gpio >= 0)
- ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
- if (ret < 0) {
- printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
- gpio = -1;
- }
-
- /* Pull the GPIO low to select SET0 register, while we program SET1 */
- if (gpio >= 0)
- gpio_direction_output(gpio, 0);
+ u32 offset_code;
- step = volt_mv - TPS62361_BASE_VOLT_MV;
- step /= 10;
+ volt_offset -= pmic->base_offset;
- debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
- if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
- puts("Scaling voltage failed for vdd_mpu from TPS\n");
+ offset_code = (volt_offset + pmic->step - 1) / pmic->step;
- /* Pull the GPIO high to select SET1 register */
- if (gpio >= 0)
- gpio_direction_output(gpio, 1);
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ return offset_code + pmic->start_code;
}
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
+ int ret = 0;
+
+ /* See if we can first get the GPIO if needed */
+ if (pmic->gpio_en)
+ ret = gpio_request(pmic->gpio, "PMIC_GPIO");
+
+ if (ret < 0) {
+ printf("%s: gpio %d request failed %d\n", __func__,
+ pmic->gpio, ret);
+ return;
+ }
+
+ /* Pull the GPIO low to select SET0 register, while we program SET1 */
+ if (pmic->gpio_en)
+ gpio_direction_output(pmic->gpio, 0);
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
- offset_code = get_offset_code(offset);
+ offset_code = get_offset_code(offset, pmic);
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
@@ -414,16 +512,46 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+
+ if (pmic->gpio_en)
+ gpio_direction_output(pmic->gpio, 1);
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+void scale_vcores(struct vcores_data const *vcores)
+{
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+
+ do_scale_vcore(vcores->core.addr, vcores->core.value,
+ vcores->core.pmic);
+
+ do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
+ vcores->mpu.pmic);
+
+ do_scale_vcore(vcores->mm.addr, vcores->mm.value,
+ vcores->mm.pmic);
+
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
+ /* Configure LDO SRAM "magic" bits */
+ writel(2, (*prcm)->prm_sldo_core_setup);
+ writel(2, (*prcm)->prm_sldo_mpu_setup);
+ writel(2, (*prcm)->prm_sldo_mm_setup);
+ }
}
-static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - %p\n", clkctrl_reg);
+ debug("Enable clock domain - %x\n", clkctrl_reg);
}
-static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+static inline void wait_for_clk_enable(u32 clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
u32 bound = LDELAY;
@@ -435,19 +563,19 @@ static inline void wait_for_clk_enable(u32 *clkctrl_addr)
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
if (--bound == 0) {
- printf("Clock enable failed for 0x%p idlest 0x%x\n",
+ printf("Clock enable failed for 0x%x idlest 0x%x\n",
clkctrl_addr, clkctrl);
return;
}
}
}
-static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
u32 wait_for_enable)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - %p\n", clkctrl_addr);
+ debug("Enable clock module - %x\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}
@@ -458,12 +586,12 @@ void freq_update_core(void)
const struct dpll_params *core_dpll_params;
u32 omap_rev = omap_revision();
- core_dpll_params = get_core_dpll_params();
+ core_dpll_params = get_core_dpll_params(*dplls_data);
/* Put EMIF clock domain in sw wakeup mode */
- enable_clock_domain(&prcm->cm_memif_clkstctrl,
+ enable_clock_domain((*prcm)->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
@@ -475,9 +603,9 @@ void freq_update_core(void)
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
- writel(freq_config1, &prcm->cm_shadow_freq_config1);
+ writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
- &prcm->cm_shadow_freq_config1, LDELAY)) {
+ (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
puts("FREQ UPDATE procedure failed!!");
hang();
}
@@ -489,20 +617,20 @@ void freq_update_core(void)
*/
if (omap_rev != OMAP5430_ES1_0) {
/* Put EMIF clock domain back in hw auto mode */
- enable_clock_domain(&prcm->cm_memif_clkstctrl,
+ enable_clock_domain((*prcm)->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
}
}
-void bypass_dpll(u32 *const base)
+void bypass_dpll(u32 const base)
{
do_bypass_dpll(base);
wait_for_bypass(base);
}
-void lock_dpll(u32 *const base)
+void lock_dpll(u32 const base)
{
do_lock_dpll(base);
wait_for_lock(base);
@@ -511,39 +639,39 @@ void lock_dpll(u32 *const base)
void setup_clocks_for_console(void)
{
/* Do not add any spl_debug prints in this function */
- clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
/* Enable all UARTs - console will be on one of them */
- clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
}
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_hw_auto,
- u32 *const *clk_modules_explicit_en,
+void do_enable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
u8 wait_for_enable)
{
u32 i, max = 100;
@@ -582,7 +710,7 @@ void prcm_init(void)
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
- scale_vcores();
+ scale_vcores(*omap_vcores);
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
setup_non_essential_dplls();
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 88253cf8ce..9eb1279d41 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -66,6 +66,19 @@ inline u32 emif_num(u32 base)
return 0;
}
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+u32 emif_sdram_type()
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ return (readl(&emif->emif_sdram_config) &
+ EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
@@ -110,11 +123,13 @@ void emif_reset_phy(u32 base)
static void do_lpddr2_init(u32 base, u32 cs)
{
u32 mr_addr;
+ const struct lpddr2_mr_regs *mr_regs;
+ get_lpddr2_mr_regs(&mr_regs);
/* Wait till device auto initialization is complete */
while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
;
- set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+ set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
/*
* tZQINIT = 1 us
* Enough loops assuming a maximum of 2GHz
@@ -122,22 +137,18 @@ static void do_lpddr2_init(u32 base, u32 cs)
sdelay(2000);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
- else
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-
- set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+ set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+ set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
/*
* Enable refresh along with writing MR2
* Encoding of RL in MR2 is (RL - 2)
*/
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, RL_FINAL - 2);
+ set_mr(base, cs, mr_addr, mr_regs->mr2);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR3, 0x1);
+ if (mr_regs->mr3 > 0)
+ set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
}
static void lpddr2_init(u32 base, const struct emif_regs *regs)
@@ -255,9 +266,6 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
@@ -277,27 +285,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- }
+ do_ext_phy_settings(base, regs);
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
@@ -1079,7 +1067,7 @@ static void do_sdram_init(u32 base)
* OPP to another)
*/
if (!(in_sdram || warm_reset())) {
- if (omap_revision() != OMAP5432_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
else
ddr3_init(base, regs);
@@ -1096,9 +1084,6 @@ void emif_post_init_config(u32 base)
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 omap_rev = omap_revision();
- if (omap_rev == OMAP5430_ES1_0)
- return;
-
/* reset phy on ES2.0 */
if (omap_rev == OMAP4430_ES2_0)
emif_reset_phy(base);
@@ -1206,7 +1191,7 @@ void dmm_init(u32 base)
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
- if (omap_revision() >= OMAP4460_ES1_0) {
+ if (lisa_map_regs->is_ma_present) {
hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)MA_BASE;
@@ -1264,7 +1249,7 @@ void dmm_init(u32 base)
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
- u32 omap_rev = omap_revision();
+ u32 sdram_type = emif_sdram_type();
debug(">>sdram_init()\n");
@@ -1275,10 +1260,10 @@ void sdram_init(void)
debug("in_sdram = %d\n", in_sdram);
if (!(in_sdram || warm_reset())) {
- if (omap_rev != OMAP5432_ES1_0)
- bypass_dpll(&prcm->cm_clkmode_dpll_core);
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ bypass_dpll((*prcm)->cm_clkmode_dpll_core);
else
- writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+ writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
if (!in_sdram)
@@ -1298,7 +1283,7 @@ void sdram_init(void)
}
/* for the shadow registers to take effect */
- if (omap_rev != OMAP5432_ES1_0)
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
freq_update_core();
/* Do some testing after the init */
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 9ef10bdf2d..05ff2e868f 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -32,6 +32,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
+#include <asm/omap_common.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -79,12 +81,17 @@ u32 cortex_rev(void)
void omap_rev_string(void)
{
u32 omap_rev = omap_revision();
+ u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
- printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
- minor_rev);
+ if (soc_variant)
+ printf("OMAP");
+ else
+ printf("DRA");
+ printf("%x ES%x.%x\n", omap_variant, major_rev,
+ minor_rev);
}
#ifdef CONFIG_SPL_BUILD
@@ -99,6 +106,10 @@ void spl_display_print(void)
}
#endif
+void __weak srcomp_enable(void)
+{
+}
+
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
@@ -116,6 +127,8 @@ void spl_display_print(void)
void s_init(void)
{
init_omap_revision();
+ hw_data_init();
+
#ifdef CONFIG_SPL_BUILD
if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
force_emif_self_refresh();
@@ -123,6 +136,7 @@ void s_init(void)
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
+ srcomp_enable();
setup_clocks_for_console();
gd = &gdata;
@@ -235,10 +249,7 @@ int checkboard(void)
*/
u32 get_device_type(void)
{
- struct omap_sys_ctrl_regs *ctrl =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- return (readl(&ctrl->control_status) &
+ return (readl((*ctrl)->control_status) &
(DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 40d64af84c..efae381bdb 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -48,10 +48,6 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
. = ALIGN(4);
__image_copy_end = .;
_end = .;
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c
index a045b77180..e6e5f7893c 100644
--- a/arch/arm/cpu/armv7/omap-common/vc.c
+++ b/arch/arm/cpu/armv7/omap-common/vc.c
@@ -81,13 +81,13 @@ void omap_vc_init(u16 speed_khz)
cycles_low -= 7;
val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
- writel(val, &prcm->prm_vc_cfg_i2c_clk);
+ writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
/* No HS mode for now */
val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
- writel(val, &prcm->prm_vc_cfg_i2c_mode);
+ writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
}
/**
@@ -113,14 +113,15 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
- writel(reg_val, &prcm->prm_vc_val_bypass);
+ writel(reg_val, (*prcm)->prm_vc_val_bypass);
/* Signal VC to send data */
- writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass);
+ writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
+ (*prcm)->prm_vc_val_bypass);
/* Wait on VC to complete transmission */
do {
- reg_val = readl(&prcm->prm_vc_val_bypass) &
+ reg_val = readl((*prcm)->prm_vc_val_bypass) &
PRM_VC_VAL_BYPASS_VALID_BIT;
if (!reg_val)
break;
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 89c587e310..c6d9a425a5 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -98,11 +98,11 @@ int board_mmc_init(bd_t *bis)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
- omap_mmc_init(0, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
break;
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(1, 0, 0, -1, -1);
break;
}
return 0;
@@ -110,7 +110,7 @@ int board_mmc_init(bd_t *bis)
void spl_board_init(void)
{
-#ifdef CONFIG_SPL_NAND_SUPPORT
+#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
#ifdef CONFIG_SPL_I2C_SUPPORT
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 83160a28f3..40808d18ff 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -27,8 +27,9 @@ LIB = $(obj)lib$(SOC).o
COBJS += sdram_elpida.o
COBJS += hwinit.o
-COBJS += clocks.o
COBJS += emif.o
+COBJS += prcm-regs.o
+COBJS += hw_data.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
deleted file mode 100644
index 12c58033d2..0000000000
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- *
- * Clock initialization for OMAP4
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * Based on previous work by:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- * Rajendra Nayak <rnayak@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif /* !CONFIG_SPL_BUILD */
-
-struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
-
-const u32 sys_clk_array[8] = {
- 12000000, /* 12 MHz */
- 13000000, /* 13 MHz */
- 16800000, /* 16.8 MHz */
- 19200000, /* 19.2 MHz */
- 26000000, /* 26 MHz */
- 27000000, /* 27 MHz */
- 38400000, /* 38.4 MHz */
-};
-
-/*
- * The M & N values in the following tables are created using the
- * following tool:
- * tools/omap/clocks_get_m_n.c
- * Please use this tool for creating the table for any new frequency.
- */
-
-/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
-static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
- {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
-static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
-static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
- {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
- {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
- {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
- {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
- {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
- {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
- {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
- {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
- {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
- {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
- {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
- {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
- {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
- {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
- {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
- {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
- {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
- {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
- {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
- {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
- {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
- {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
- {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
- {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
- {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
- {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
- {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
- {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
- {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
- {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
- {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
- {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
- {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-void setup_post_dividers(u32 *const base, const struct dpll_params *params)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, &dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, &dpll_regs->cm_div_m3_dpll);
- if (params->m4 >= 0)
- writel(params->m4, &dpll_regs->cm_div_m4_dpll);
- if (params->m5 >= 0)
- writel(params->m5, &dpll_regs->cm_div_m5_dpll);
- if (params->m6 >= 0)
- writel(params->m6, &dpll_regs->cm_div_m6_dpll);
- if (params->m7 >= 0)
- writel(params->m7, &dpll_regs->cm_div_m7_dpll);
-}
-
-/*
- * Lock MPU dpll
- *
- * Resulting MPU frequencies:
- * 4430 ES1.0 : 600 MHz
- * 4430 ES2.x : 792 MHz (OPP Turbo)
- * 4460 : 920 MHz (OPP Turbo) - DCC disabled
- */
-const struct dpll_params *get_mpu_dpll_params(void)
-{
- u32 omap_rev, sysclk_ind;
-
- omap_rev = omap_revision();
- sysclk_ind = get_sys_clk_index();
-
- if (omap_rev == OMAP4430_ES1_0)
- return &mpu_dpll_params_1200mhz[sysclk_ind];
- else if (omap_rev < OMAP4460_ES1_0)
- return &mpu_dpll_params_1600mhz[sysclk_ind];
- else
- return &mpu_dpll_params_1400mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_core_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- switch (omap_revision()) {
- case OMAP4430_ES1_0:
- return &core_dpll_params_es1_1524mhz[sysclk_ind];
- case OMAP4430_ES2_0:
- case OMAP4430_SILICON_ID_INVALID:
- /* safest */
- return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
- default:
- return &core_dpll_params_1600mhz[sysclk_ind];
- }
-}
-
-
-const struct dpll_params *get_per_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &per_dpll_params_1536mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_iva_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &iva_dpll_params_1862mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_usb_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &usb_dpll_params_1920mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_abe_dpll_params(void)
-{
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- u32 sysclk_ind = get_sys_clk_index();
- return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
-#else
- return &abe_dpll_params_32k_196608khz;
-#endif
-}
-
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-void scale_vcores(void)
-{
- u32 volt, omap_rev;
-
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
-
- omap_rev = omap_revision();
-
- /*
- * Scale Voltage rails:
- * 1. VDD_CORE
- * 3. VDD_MPU
- * 3. VDD_IVA
- */
- if (omap_rev < OMAP4460_ES1_0) {
- /*
- * OMAP4430:
- * VDD_CORE = TWL6030 VCORE3
- * VDD_MPU = TWL6030 VCORE1
- * VDD_IVA = TWL6030 VCORE2
- */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
-
- /*
- * note on VDD_MPU:
- * Setting a high voltage for Nitro mode as smart reflex is not
- * enabled. We use the maximum possible value in the AVS range
- * because the next higher voltage in the discrete range
- * (code >= 0b111010) is way too high.
- */
- volt = 1325;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
-
- } else {
- /*
- * OMAP4460:
- * VDD_CORE = TWL6030 VCORE1
- * VDD_MPU = TPS62361
- * VDD_IVA = TWL6030 VCORE2
- */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
- /* TPS62361 */
- volt = 1203;
- do_scale_tps62361(TPS62361_VSEL0_GPIO,
- TPS62361_REG_ADDR_SET1, volt);
- /* VCORE 2 - supplies vdd_iva */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
- }
-}
-
-u32 get_offset_code(u32 offset)
-{
- u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
-
- if (omap_revision() == OMAP4430_ES1_0)
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
- else
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
- offset_code = (offset + step - 1) / step;
-
- /* The code starts at 1 not 0 */
- return ++offset_code;
-}
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- &prcm->cm_l4per_clkstctrl,
- &prcm->cm_l3init_clkstctrl,
- &prcm->cm_memif_clkstctrl,
- &prcm->cm_l4cfg_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- &prcm->cm_l3_2_gpmc_clkctrl,
- &prcm->cm_memif_emif_1_clkctrl,
- &prcm->cm_memif_emif_2_clkctrl,
- &prcm->cm_l4cfg_l4_cfg_clkctrl,
- &prcm->cm_wkup_gpio1_clkctrl,
- &prcm->cm_l4per_gpio2_clkctrl,
- &prcm->cm_l4per_gpio3_clkctrl,
- &prcm->cm_l4per_gpio4_clkctrl,
- &prcm->cm_l4per_gpio5_clkctrl,
- &prcm->cm_l4per_gpio6_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_wkup_gptimer1_clkctrl,
- &prcm->cm_l3init_hsmmc1_clkctrl,
- &prcm->cm_l3init_hsmmc2_clkctrl,
- &prcm->cm_l4per_gptimer2_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_l4per_uart3_clkctrl,
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- /* Enable optional 48M functional clock for USB PHY */
- setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
- USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- &prcm->cm_l3init_hsusbotg_clkctrl,
- &prcm->cm_l3init_usbphy_clkctrl,
- &prcm->cm_l3init_usbphy_clkctrl,
- &prcm->cm_clksel_usb_60mhz,
- &prcm->cm_l3init_hsusbtll_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_l4per_mcspi1_clkctrl,
- &prcm->cm_l4per_i2c1_clkctrl,
- &prcm->cm_l4per_i2c2_clkctrl,
- &prcm->cm_l4per_i2c3_clkctrl,
- &prcm->cm_l4per_i2c4_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
- u32 *const clk_domains_non_essential[] = {
- &prcm->cm_mpu_m3_clkstctrl,
- &prcm->cm_ivahd_clkstctrl,
- &prcm->cm_dsp_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sgx_clkstctrl,
- &prcm->cm1_abe_clkstctrl,
- &prcm->cm_c2c_clkstctrl,
- &prcm->cm_cam_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sdma_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_non_essential[] = {
- &prcm->cm_l3instr_l3_3_clkctrl,
- &prcm->cm_l3instr_l3_instr_clkctrl,
- &prcm->cm_l3instr_intrconn_wp1_clkctrl,
- &prcm->cm_l3init_hsi_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_non_essential[] = {
- &prcm->cm1_abe_aess_clkctrl,
- &prcm->cm1_abe_pdm_clkctrl,
- &prcm->cm1_abe_dmic_clkctrl,
- &prcm->cm1_abe_mcasp_clkctrl,
- &prcm->cm1_abe_mcbsp1_clkctrl,
- &prcm->cm1_abe_mcbsp2_clkctrl,
- &prcm->cm1_abe_mcbsp3_clkctrl,
- &prcm->cm1_abe_slimbus_clkctrl,
- &prcm->cm1_abe_timer5_clkctrl,
- &prcm->cm1_abe_timer6_clkctrl,
- &prcm->cm1_abe_timer7_clkctrl,
- &prcm->cm1_abe_timer8_clkctrl,
- &prcm->cm1_abe_wdt3_clkctrl,
- &prcm->cm_l4per_gptimer9_clkctrl,
- &prcm->cm_l4per_gptimer10_clkctrl,
- &prcm->cm_l4per_gptimer11_clkctrl,
- &prcm->cm_l4per_gptimer3_clkctrl,
- &prcm->cm_l4per_gptimer4_clkctrl,
- &prcm->cm_l4per_hdq1w_clkctrl,
- &prcm->cm_l4per_mcbsp4_clkctrl,
- &prcm->cm_l4per_mcspi2_clkctrl,
- &prcm->cm_l4per_mcspi3_clkctrl,
- &prcm->cm_l4per_mcspi4_clkctrl,
- &prcm->cm_l4per_mmcsd3_clkctrl,
- &prcm->cm_l4per_mmcsd4_clkctrl,
- &prcm->cm_l4per_mmcsd5_clkctrl,
- &prcm->cm_l4per_uart1_clkctrl,
- &prcm->cm_l4per_uart2_clkctrl,
- &prcm->cm_l4per_uart4_clkctrl,
- &prcm->cm_wkup_keyboard_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_cam_iss_clkctrl,
- &prcm->cm_cam_fdif_clkctrl,
- &prcm->cm_dss_dss_clkctrl,
- &prcm->cm_sgx_sgx_clkctrl,
- 0
- };
-
- /* Enable optional functional clock for ISS */
- setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable all optional functional clocks of DSS */
- setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
- do_enable_clocks(clk_domains_non_essential,
- clk_modules_hw_auto_non_essential,
- clk_modules_explicit_en_non_essential,
- 0);
-
- /* Put camera module in no sleep mode */
- clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
- CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
new file mode 100644
index 0000000000..7551b9861e
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -0,0 +1,491 @@
+/*
+ *
+ * HW data initialization for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+
+struct prcm_regs const **prcm =
+ (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+ (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+ (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/*
+ * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
+ * OMAP4460 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
+ {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
+ * OMAP4430 OPP_TURBO frequency
+ */
+static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1200 MHz - MPU clk at 600 MHz
+ * OMAP4430 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+ {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4460 OPP_NOM frequency */
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4430 ES1 OPP_NOM frequency */
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+ {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4430 ES2.X OPP_NOM frequency */
+static const struct dpll_params
+ core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+ {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+ {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+ {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+struct dplls omap4430_dplls_es1 = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_es1_1524mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4430_dplls = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4460_dplls = {
+ .mpu = mpu_dpll_params_1400mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct pmic_data twl6030_4430es1 = {
+ .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
+ .step = 12660, /* 10 mV represented in uV */
+ /* The code starts at 1 not 0 */
+ .start_code = 1,
+};
+
+struct pmic_data twl6030 = {
+ .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
+ .step = 12660, /* 10 mV represented in uV */
+ /* The code starts at 1 not 0 */
+ .start_code = 1,
+};
+
+struct pmic_data tps62361 = {
+ .base_offset = TPS62361_BASE_VOLT_MV,
+ .step = 10000, /* 10 mV represented in uV */
+ .start_code = 0,
+ .gpio = TPS62361_VSEL0_GPIO,
+ .gpio_en = 1
+};
+
+struct vcores_data omap4430_volts_es1 = {
+ .mpu.value = 1325,
+ .mpu.addr = SMPS_REG_ADDR_VCORE1,
+ .mpu.pmic = &twl6030_4430es1,
+
+ .core.value = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE3,
+ .core.pmic = &twl6030_4430es1,
+
+ .mm.value = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &twl6030_4430es1,
+};
+
+struct vcores_data omap4430_volts = {
+ .mpu.value = 1325,
+ .mpu.addr = SMPS_REG_ADDR_VCORE1,
+ .mpu.pmic = &twl6030,
+
+ .core.value = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE3,
+ .core.pmic = &twl6030,
+
+ .mm.value = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &twl6030,
+};
+
+struct vcores_data omap4460_volts = {
+ .mpu.value = 1203,
+ .mpu.addr = TPS62361_REG_ADDR_SET1,
+ .mpu.pmic = &tps62361,
+
+ .core.value = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE1,
+ .core.pmic = &tps62361,
+
+ .mm.value = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &tps62361,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ (*prcm)->cm_l4per_clkstctrl,
+ (*prcm)->cm_l3init_clkstctrl,
+ (*prcm)->cm_memif_clkstctrl,
+ (*prcm)->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3_gpmc_clkctrl,
+ (*prcm)->cm_memif_emif_1_clkctrl,
+ (*prcm)->cm_memif_emif_2_clkctrl,
+ (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+ (*prcm)->cm_wkup_gpio1_clkctrl,
+ (*prcm)->cm_l4per_gpio2_clkctrl,
+ (*prcm)->cm_l4per_gpio3_clkctrl,
+ (*prcm)->cm_l4per_gpio4_clkctrl,
+ (*prcm)->cm_l4per_gpio5_clkctrl,
+ (*prcm)->cm_l4per_gpio6_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_wkup_gptimer1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc2_clkctrl,
+ (*prcm)->cm_l4per_gptimer2_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_l4per_uart3_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ /* Enable optional 48M functional clock for USB PHY */
+ setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
+ USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3init_hsusbotg_clkctrl,
+ (*prcm)->cm_l3init_usbphy_clkctrl,
+ (*prcm)->cm_l3init_usbphy_clkctrl,
+ (*prcm)->cm_clksel_usb_60mhz,
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_mcspi1_clkctrl,
+ (*prcm)->cm_l4per_i2c1_clkctrl,
+ (*prcm)->cm_l4per_i2c2_clkctrl,
+ (*prcm)->cm_l4per_i2c3_clkctrl,
+ (*prcm)->cm_l4per_i2c4_clkctrl,
+ (*prcm)->cm_l3init_hsusbhost_clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_non_essential_clocks(void)
+{
+ u32 const clk_domains_non_essential[] = {
+ (*prcm)->cm_mpu_m3_clkstctrl,
+ (*prcm)->cm_ivahd_clkstctrl,
+ (*prcm)->cm_dsp_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sgx_clkstctrl,
+ (*prcm)->cm1_abe_clkstctrl,
+ (*prcm)->cm_c2c_clkstctrl,
+ (*prcm)->cm_cam_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sdma_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_non_essential[] = {
+ (*prcm)->cm_l3instr_l3_3_clkctrl,
+ (*prcm)->cm_l3instr_l3_instr_clkctrl,
+ (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
+ (*prcm)->cm_l3init_hsi_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_non_essential[] = {
+ (*prcm)->cm1_abe_aess_clkctrl,
+ (*prcm)->cm1_abe_pdm_clkctrl,
+ (*prcm)->cm1_abe_dmic_clkctrl,
+ (*prcm)->cm1_abe_mcasp_clkctrl,
+ (*prcm)->cm1_abe_mcbsp1_clkctrl,
+ (*prcm)->cm1_abe_mcbsp2_clkctrl,
+ (*prcm)->cm1_abe_mcbsp3_clkctrl,
+ (*prcm)->cm1_abe_slimbus_clkctrl,
+ (*prcm)->cm1_abe_timer5_clkctrl,
+ (*prcm)->cm1_abe_timer6_clkctrl,
+ (*prcm)->cm1_abe_timer7_clkctrl,
+ (*prcm)->cm1_abe_timer8_clkctrl,
+ (*prcm)->cm1_abe_wdt3_clkctrl,
+ (*prcm)->cm_l4per_gptimer9_clkctrl,
+ (*prcm)->cm_l4per_gptimer10_clkctrl,
+ (*prcm)->cm_l4per_gptimer11_clkctrl,
+ (*prcm)->cm_l4per_gptimer3_clkctrl,
+ (*prcm)->cm_l4per_gptimer4_clkctrl,
+ (*prcm)->cm_l4per_hdq1w_clkctrl,
+ (*prcm)->cm_l4per_mcbsp4_clkctrl,
+ (*prcm)->cm_l4per_mcspi2_clkctrl,
+ (*prcm)->cm_l4per_mcspi3_clkctrl,
+ (*prcm)->cm_l4per_mcspi4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd3_clkctrl,
+ (*prcm)->cm_l4per_mmcsd4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd5_clkctrl,
+ (*prcm)->cm_l4per_uart1_clkctrl,
+ (*prcm)->cm_l4per_uart2_clkctrl,
+ (*prcm)->cm_l4per_uart4_clkctrl,
+ (*prcm)->cm_wkup_keyboard_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_cam_iss_clkctrl,
+ (*prcm)->cm_cam_fdif_clkctrl,
+ (*prcm)->cm_dss_dss_clkctrl,
+ (*prcm)->cm_sgx_sgx_clkctrl,
+ 0
+ };
+
+ /* Enable optional functional clock for ISS */
+ setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable all optional functional clocks of DSS */
+ setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
+
+ /* Put camera module in no sleep mode */
+ clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void hw_data_init(void)
+{
+ u32 omap_rev = omap_revision();
+
+ (*prcm) = &omap4_prcm;
+
+ switch (omap_rev) {
+
+ case OMAP4430_ES1_0:
+ *dplls_data = &omap4430_dplls_es1;
+ *omap_vcores = &omap4430_volts_es1;
+ break;
+
+ case OMAP4430_ES2_0:
+ case OMAP4430_ES2_1:
+ case OMAP4430_ES2_2:
+ case OMAP4430_ES2_3:
+ *dplls_data = &omap4430_dplls;
+ *omap_vcores = &omap4430_volts;
+ break;
+
+ case OMAP4460_ES1_0:
+ case OMAP4460_ES1_1:
+ *dplls_data = &omap4460_dplls;
+ *omap_vcores = &omap4460_volts;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+
+ *ctrl = &omap4_ctrl;
+}
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index f4123aaffc..2db517b1bf 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -57,10 +57,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
void do_io_settings(void)
{
u32 lpddr2io;
- struct control_lpddr2io_regs *lpddr2io_regs =
- (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- struct omap_sys_ctrl_regs *const ctrl =
- (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
@@ -72,20 +68,20 @@ void do_io_settings(void)
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- &lpddr2io_regs->control_lpddr2io1_2);
- writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
+ (*ctrl)->control_lpddr2io1_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
/* EMIF2 */
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- &lpddr2io_regs->control_lpddr2io2_2);
- writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
+ (*ctrl)->control_lpddr2io2_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
@@ -93,16 +89,16 @@ void do_io_settings(void)
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
- if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+ if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_iva_voltage_ctrl);
+ (*ctrl)->control_ldosram_iva_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_mpu_voltage_ctrl);
+ (*ctrl)->control_ldosram_mpu_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_core_voltage_ctrl);
+ (*ctrl)->control_ldosram_core_voltage_ctrl);
}
/*
@@ -110,11 +106,11 @@ void do_io_settings(void)
* i. unconditionally for all 4430
* ii. only if un-trimmed for 4460
*/
- if (!readl(&ctrl->control_efuse_1))
- writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+ if (!readl((*ctrl)->control_efuse_1))
+ writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
- if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
- writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+ if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
+ writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
}
#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
new file mode 100644
index 0000000000..7225a301b1
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -0,0 +1,315 @@
+/*
+ *
+ * HW regs data for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap4_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a004100,
+ .cm_clksel_abe = 0x4a004108,
+ .cm_dll_ctrl = 0x4a004110,
+ .cm_clkmode_dpll_core = 0x4a004120,
+ .cm_idlest_dpll_core = 0x4a004124,
+ .cm_autoidle_dpll_core = 0x4a004128,
+ .cm_clksel_dpll_core = 0x4a00412c,
+ .cm_div_m2_dpll_core = 0x4a004130,
+ .cm_div_m3_dpll_core = 0x4a004134,
+ .cm_div_m4_dpll_core = 0x4a004138,
+ .cm_div_m5_dpll_core = 0x4a00413c,
+ .cm_div_m6_dpll_core = 0x4a004140,
+ .cm_div_m7_dpll_core = 0x4a004144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a004148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+ .cm_emu_override_dpll_core = 0x4a004150,
+ .cm_clkmode_dpll_mpu = 0x4a004160,
+ .cm_idlest_dpll_mpu = 0x4a004164,
+ .cm_autoidle_dpll_mpu = 0x4a004168,
+ .cm_clksel_dpll_mpu = 0x4a00416c,
+ .cm_div_m2_dpll_mpu = 0x4a004170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+ .cm_bypclk_dpll_mpu = 0x4a00419c,
+ .cm_clkmode_dpll_iva = 0x4a0041a0,
+ .cm_idlest_dpll_iva = 0x4a0041a4,
+ .cm_autoidle_dpll_iva = 0x4a0041a8,
+ .cm_clksel_dpll_iva = 0x4a0041ac,
+ .cm_div_m4_dpll_iva = 0x4a0041b8,
+ .cm_div_m5_dpll_iva = 0x4a0041bc,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+ .cm_bypclk_dpll_iva = 0x4a0041dc,
+ .cm_clkmode_dpll_abe = 0x4a0041e0,
+ .cm_idlest_dpll_abe = 0x4a0041e4,
+ .cm_autoidle_dpll_abe = 0x4a0041e8,
+ .cm_clksel_dpll_abe = 0x4a0041ec,
+ .cm_div_m2_dpll_abe = 0x4a0041f0,
+ .cm_div_m3_dpll_abe = 0x4a0041f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+ .cm_clkmode_dpll_ddrphy = 0x4a004220,
+ .cm_idlest_dpll_ddrphy = 0x4a004224,
+ .cm_autoidle_dpll_ddrphy = 0x4a004228,
+ .cm_clksel_dpll_ddrphy = 0x4a00422c,
+ .cm_div_m2_dpll_ddrphy = 0x4a004230,
+ .cm_div_m4_dpll_ddrphy = 0x4a004238,
+ .cm_div_m5_dpll_ddrphy = 0x4a00423c,
+ .cm_div_m6_dpll_ddrphy = 0x4a004240,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+ .cm_shadow_freq_config1 = 0x4a004260,
+ .cm_mpu_mpu_clkctrl = 0x4a004320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a004400,
+ .cm_dsp_dsp_clkctrl = 0x4a004420,
+
+ /* cm1.abe */
+ .cm1_abe_clkstctrl = 0x4a004500,
+ .cm1_abe_l4abe_clkctrl = 0x4a004520,
+ .cm1_abe_aess_clkctrl = 0x4a004528,
+ .cm1_abe_pdm_clkctrl = 0x4a004530,
+ .cm1_abe_dmic_clkctrl = 0x4a004538,
+ .cm1_abe_mcasp_clkctrl = 0x4a004540,
+ .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+ .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+ .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+ .cm1_abe_slimbus_clkctrl = 0x4a004560,
+ .cm1_abe_timer5_clkctrl = 0x4a004568,
+ .cm1_abe_timer6_clkctrl = 0x4a004570,
+ .cm1_abe_timer7_clkctrl = 0x4a004578,
+ .cm1_abe_timer8_clkctrl = 0x4a004580,
+ .cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+ /* cm2.ckgen */
+ .cm_clksel_mpu_m3_iss_root = 0x4a008100,
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_scale_fclk = 0x4a008108,
+ .cm_core_dvfs_perf1 = 0x4a008110,
+ .cm_core_dvfs_perf2 = 0x4a008114,
+ .cm_core_dvfs_perf3 = 0x4a008118,
+ .cm_core_dvfs_perf4 = 0x4a00811c,
+ .cm_core_dvfs_current = 0x4a008124,
+ .cm_iva_dvfs_perf_tesla = 0x4a008128,
+ .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+ .cm_iva_dvfs_perf_abe = 0x4a008130,
+ .cm_iva_dvfs_current = 0x4a008138,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_m4_dpll_per = 0x4a008158,
+ .cm_div_m5_dpll_per = 0x4a00815c,
+ .cm_div_m6_dpll_per = 0x4a008160,
+ .cm_div_m7_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_emu_override_dpll_per = 0x4a008170,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_unipro = 0x4a0081c0,
+ .cm_idlest_dpll_unipro = 0x4a0081c4,
+ .cm_autoidle_dpll_unipro = 0x4a0081c8,
+ .cm_clksel_dpll_unipro = 0x4a0081cc,
+ .cm_div_m2_dpll_unipro = 0x4a0081d0,
+ .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+ .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+ /* cm2.core */
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_2_clkstctrl = 0x4a008800,
+ .cm_l3_2_dynamicdep = 0x4a008808,
+ .cm_l3_2_l3_2_clkctrl = 0x4a008820,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_memif_emif_h1_clkctrl = 0x4a008b50,
+ .cm_memif_emif_h2_clkctrl = 0x4a008b58,
+ .cm_memif_dll_h_clkctrl = 0x4a008b60,
+ .cm_c2c_clkstctrl = 0x4a008c00,
+ .cm_c2c_staticdep = 0x4a008c04,
+ .cm_c2c_dynamicdep = 0x4a008c08,
+ .cm_c2c_sad2d_clkctrl = 0x4a008c20,
+ .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+ .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
+ .cm_ivahd_clkstctrl = 0x4a008f00,
+
+ /* cm2.ivahd */
+ .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+ .cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009000,
+ .cm_cam_iss_clkctrl = 0x4a009020,
+ .cm_cam_fdif_clkctrl = 0x4a009028,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009100,
+ .cm_dss_dss_clkctrl = 0x4a009120,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009200,
+ .cm_sgx_sgx_clkctrl = 0x4a009220,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009300,
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+ .cm_l3init_hsi_clkctrl = 0x4a009338,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+ .cm_l3init_p1500_clkctrl = 0x4a009378,
+ .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+ .cm_l3init_usbphy_clkctrl = 0x4a0093e0,
+
+ /* cm2.l4per */
+ .cm_l4per_clkstctrl = 0x4a009400,
+ .cm_l4per_dynamicdep = 0x4a009408,
+ .cm_l4per_adc_clkctrl = 0x4a009420,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009428,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009430,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009438,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009440,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009448,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009450,
+ .cm_l4per_elm_clkctrl = 0x4a009458,
+ .cm_l4per_gpio2_clkctrl = 0x4a009460,
+ .cm_l4per_gpio3_clkctrl = 0x4a009468,
+ .cm_l4per_gpio4_clkctrl = 0x4a009470,
+ .cm_l4per_gpio5_clkctrl = 0x4a009478,
+ .cm_l4per_gpio6_clkctrl = 0x4a009480,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009488,
+ .cm_l4per_hecc1_clkctrl = 0x4a009490,
+ .cm_l4per_hecc2_clkctrl = 0x4a009498,
+ .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0094c0,
+ .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+ .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+ .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
+ .cm_l4per_mgate_clkctrl = 0x4a0094e8,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009500,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009508,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+ .cm_l4per_msprohg_clkctrl = 0x4a009530,
+ .cm_l4per_slimbus2_clkctrl = 0x4a009538,
+ .cm_l4per_uart1_clkctrl = 0x4a009540,
+ .cm_l4per_uart2_clkctrl = 0x4a009548,
+ .cm_l4per_uart3_clkctrl = 0x4a009550,
+ .cm_l4per_uart4_clkctrl = 0x4a009558,
+ .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+ .cm_l4per_i2c5_clkctrl = 0x4a009568,
+ .cm_l4sec_clkstctrl = 0x4a009580,
+ .cm_l4sec_staticdep = 0x4a009584,
+ .cm_l4sec_dynamicdep = 0x4a009588,
+ .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+ .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+ .cm_l4sec_rng_clkctrl = 0x4a0095c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4a30610c,
+ .cm_sys_clksel = 0x4a306110,
+ .cm_wkup_clkstctrl = 0x4a307800,
+ .cm_wkup_l4wkup_clkctrl = 0x4a307820,
+ .cm_wkup_wdtimer1_clkctrl = 0x4a307828,
+ .cm_wkup_wdtimer2_clkctrl = 0x4a307830,
+ .cm_wkup_gpio1_clkctrl = 0x4a307838,
+ .cm_wkup_gptimer1_clkctrl = 0x4a307840,
+ .cm_wkup_gptimer12_clkctrl = 0x4a307848,
+ .cm_wkup_synctimer_clkctrl = 0x4a307850,
+ .cm_wkup_usim_clkctrl = 0x4a307858,
+ .cm_wkup_sarram_clkctrl = 0x4a307860,
+ .cm_wkup_keyboard_clkctrl = 0x4a307878,
+ .cm_wkup_rtc_clkctrl = 0x4a307880,
+ .cm_wkup_bandgap_clkctrl = 0x4a307888,
+ .prm_vc_val_bypass = 0x4a307ba0,
+ .prm_vc_cfg_channel = 0x4a307ba4,
+ .prm_vc_cfg_i2c_mode = 0x4a307ba8,
+ .prm_vc_cfg_i2c_clk = 0x4a307bac,
+};
+
+struct omap_sys_ctrl_regs const omap4_ctrl = {
+ .control_id_code = 0x4A002204,
+ .control_std_fuse_opp_bgap = 0x4a002260,
+ .control_status = 0x4a0022c4,
+ .control_ldosram_iva_voltage_ctrl = 0x4A002320,
+ .control_ldosram_mpu_voltage_ctrl = 0x4A002324,
+ .control_ldosram_core_voltage_ctrl = 0x4A002328,
+ .control_pbiaslite = 0x4A100600,
+ .control_lpddr2io1_0 = 0x4A100638,
+ .control_lpddr2io1_1 = 0x4A10063C,
+ .control_lpddr2io1_2 = 0x4A100640,
+ .control_lpddr2io1_3 = 0x4A100644,
+ .control_lpddr2io2_0 = 0x4A100648,
+ .control_lpddr2io2_1 = 0x4A10064C,
+ .control_lpddr2io2_2 = 0x4A100650,
+ .control_lpddr2io2_3 = 0x4A100654,
+ .control_efuse_1 = 0x4A100700,
+ .control_efuse_2 = 0x4A100704,
+};
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index b9128faa56..20fc55216a 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -90,21 +90,28 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
-/* Dummy registers for OMAP44xx */
-const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80540300
+ .dmm_lisa_map_3 = 0x80540300,
+ .is_ma_present = 0x0
};
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80640300
+ .dmm_lisa_map_3 = 0x80640300,
+ .is_ma_present = 0x0
+};
+
+const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
+ .dmm_lisa_map_0 = 0xFF020100,
+ .dmm_lisa_map_1 = 0,
+ .dmm_lisa_map_2 = 0,
+ .dmm_lisa_map_3 = 0x80640300,
+ .is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
@@ -129,8 +136,10 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
if (omap_rev == OMAP4430_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
- else
+ else if (omap_rev < OMAP4460_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+ else
+ *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
@@ -284,3 +293,16 @@ void emif_get_device_timings(u32 emif_nr,
__attribute__((weak, alias("emif_get_device_timings_sdp")));
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
+const struct lpddr2_mr_regs mr_regs = {
+ .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
+ .mr2 = 0x4,
+ .mr3 = -1,
+ .mr10 = MR10_ZQ_ZQINIT,
+ .mr16 = MR16_REF_FULL_ARRAY
+};
+
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
+{
+ *regs = &mr_regs;
+}
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index 9b261c4df2..ce00e2c3c5 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -26,9 +26,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS += hwinit.o
-COBJS += clocks.o
COBJS += emif.o
COBJS += sdram.o
+COBJS += prcm-regs.o
+COBJS += hw_data.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
deleted file mode 100644
index eecfbade35..0000000000
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/*
- *
- * Clock initialization for OMAP5
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- * Sricharan R <r.sricharan@ti.com>
- *
- * Based on previous work by:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- * Rajendra Nayak <rnayak@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif
-
-struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
-
-const u32 sys_clk_array[8] = {
- 12000000, /* 12 MHz */
- 0, /* NA */
- 16800000, /* 16.8 MHz */
- 19200000, /* 19.2 MHz */
- 26000000, /* 26 MHz */
- 0, /* NA */
- 38400000, /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
- {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
- {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
- {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
- {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
- {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
- {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
- {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
- {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
- {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
- {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
- {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
- {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
- {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
- {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-void setup_post_dividers(u32 *const base, const struct dpll_params *params)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, &dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, &dpll_regs->cm_div_m3_dpll);
- if (params->h11 >= 0)
- writel(params->h11, &dpll_regs->cm_div_h11_dpll);
- if (params->h12 >= 0)
- writel(params->h12, &dpll_regs->cm_div_h12_dpll);
- if (params->h13 >= 0)
- writel(params->h13, &dpll_regs->cm_div_h13_dpll);
- if (params->h14 >= 0)
- writel(params->h14, &dpll_regs->cm_div_h14_dpll);
- if (params->h22 >= 0)
- writel(params->h22, &dpll_regs->cm_div_h22_dpll);
- if (params->h23 >= 0)
- writel(params->h23, &dpll_regs->cm_div_h23_dpll);
-}
-
-const struct dpll_params *get_mpu_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &mpu_dpll_params_800mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_core_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- /* Configuring the DDR to be at 532mhz */
- return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
-}
-
-const struct dpll_params *get_per_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &per_dpll_params_768mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_iva_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &iva_dpll_params_2330mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_usb_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &usb_dpll_params_1920mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_abe_dpll_params(void)
-{
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- u32 sysclk_ind = get_sys_clk_index();
- return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
-#else
- return &abe_dpll_params_32k_196608khz;
-#endif
-}
-
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-void scale_vcores(void)
-{
- u32 volt_core, volt_mpu, volt_mm;
-
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
-
- /* Palmas settings */
- if (omap_revision() != OMAP5432_ES1_0) {
- volt_core = VDD_CORE;
- volt_mpu = VDD_MPU;
- volt_mm = VDD_MM;
- } else {
- volt_core = VDD_CORE_5432;
- volt_mpu = VDD_MPU_5432;
- volt_mm = VDD_MM_5432;
- }
-
- do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
- do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
- do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
-
- if (omap_revision() == OMAP5432_ES1_0) {
- /* Configure LDO SRAM "magic" bits */
- writel(2, &prcm->prm_sldo_core_setup);
- writel(2, &prcm->prm_sldo_mpu_setup);
- writel(2, &prcm->prm_sldo_mm_setup);
- }
-}
-
-u32 get_offset_code(u32 volt_offset)
-{
- u32 offset_code, step = 10000; /* 10 mV represented in uV */
-
- volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
-
- offset_code = (volt_offset + step - 1) / step;
-
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- return offset_code + 6;
-}
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- &prcm->cm_l4per_clkstctrl,
- &prcm->cm_l3init_clkstctrl,
- &prcm->cm_memif_clkstctrl,
- &prcm->cm_l4cfg_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- &prcm->cm_l3_2_gpmc_clkctrl,
- &prcm->cm_memif_emif_1_clkctrl,
- &prcm->cm_memif_emif_2_clkctrl,
- &prcm->cm_l4cfg_l4_cfg_clkctrl,
- &prcm->cm_wkup_gpio1_clkctrl,
- &prcm->cm_l4per_gpio2_clkctrl,
- &prcm->cm_l4per_gpio3_clkctrl,
- &prcm->cm_l4per_gpio4_clkctrl,
- &prcm->cm_l4per_gpio5_clkctrl,
- &prcm->cm_l4per_gpio6_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_wkup_gptimer1_clkctrl,
- &prcm->cm_l3init_hsmmc1_clkctrl,
- &prcm->cm_l3init_hsmmc2_clkctrl,
- &prcm->cm_l4per_gptimer2_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_l4per_uart3_clkctrl,
- &prcm->cm_l4per_i2c1_clkctrl,
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Set the correct clock dividers for mmc */
- setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
- setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-
- /* Select 384Mhz for GPU as its the POR for ES1.0 */
- setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_HYD_GCLK_MASK);
- setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_CORE_GCLK_MASK);
-
- /* Enable SCRM OPT clocks for PER and CORE dpll */
- setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_PER_MASK);
- setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_CORE_MASK);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_l4per_mcspi1_clkctrl,
- &prcm->cm_l4per_i2c2_clkctrl,
- &prcm->cm_l4per_i2c3_clkctrl,
- &prcm->cm_l4per_i2c4_clkctrl,
- &prcm->cm_l3init_hsusbtll_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
- &prcm->cm_l3init_fsusb_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
- u32 *const clk_domains_non_essential[] = {
- &prcm->cm_mpu_m3_clkstctrl,
- &prcm->cm_ivahd_clkstctrl,
- &prcm->cm_dsp_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sgx_clkstctrl,
- &prcm->cm1_abe_clkstctrl,
- &prcm->cm_c2c_clkstctrl,
- &prcm->cm_cam_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sdma_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_non_essential[] = {
- &prcm->cm_mpu_m3_mpu_m3_clkctrl,
- &prcm->cm_ivahd_ivahd_clkctrl,
- &prcm->cm_ivahd_sl2_clkctrl,
- &prcm->cm_dsp_dsp_clkctrl,
- &prcm->cm_l3instr_l3_3_clkctrl,
- &prcm->cm_l3instr_l3_instr_clkctrl,
- &prcm->cm_l3instr_intrconn_wp1_clkctrl,
- &prcm->cm_l3init_hsi_clkctrl,
- &prcm->cm_l4per_hdq1w_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_non_essential[] = {
- &prcm->cm1_abe_aess_clkctrl,
- &prcm->cm1_abe_pdm_clkctrl,
- &prcm->cm1_abe_dmic_clkctrl,
- &prcm->cm1_abe_mcasp_clkctrl,
- &prcm->cm1_abe_mcbsp1_clkctrl,
- &prcm->cm1_abe_mcbsp2_clkctrl,
- &prcm->cm1_abe_mcbsp3_clkctrl,
- &prcm->cm1_abe_slimbus_clkctrl,
- &prcm->cm1_abe_timer5_clkctrl,
- &prcm->cm1_abe_timer6_clkctrl,
- &prcm->cm1_abe_timer7_clkctrl,
- &prcm->cm1_abe_timer8_clkctrl,
- &prcm->cm1_abe_wdt3_clkctrl,
- &prcm->cm_l4per_gptimer9_clkctrl,
- &prcm->cm_l4per_gptimer10_clkctrl,
- &prcm->cm_l4per_gptimer11_clkctrl,
- &prcm->cm_l4per_gptimer3_clkctrl,
- &prcm->cm_l4per_gptimer4_clkctrl,
- &prcm->cm_l4per_mcspi2_clkctrl,
- &prcm->cm_l4per_mcspi3_clkctrl,
- &prcm->cm_l4per_mcspi4_clkctrl,
- &prcm->cm_l4per_mmcsd3_clkctrl,
- &prcm->cm_l4per_mmcsd4_clkctrl,
- &prcm->cm_l4per_mmcsd5_clkctrl,
- &prcm->cm_l4per_uart1_clkctrl,
- &prcm->cm_l4per_uart2_clkctrl,
- &prcm->cm_l4per_uart4_clkctrl,
- &prcm->cm_wkup_keyboard_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_cam_iss_clkctrl,
- &prcm->cm_cam_fdif_clkctrl,
- &prcm->cm_dss_dss_clkctrl,
- &prcm->cm_sgx_sgx_clkctrl,
- 0
- };
-
- /* Enable optional functional clock for ISS */
- setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable all optional functional clocks of DSS */
- setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
- do_enable_clocks(clk_domains_non_essential,
- clk_modules_hw_auto_non_essential,
- clk_modules_explicit_en_non_essential,
- 0);
-
- /* Put camera module in no sleep mode */
- clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
- CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
new file mode 100644
index 0000000000..ced274e4db
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -0,0 +1,596 @@
+/*
+ *
+ * HW data initialization for OMAP5
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+struct prcm_regs const **prcm =
+ (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+ (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+ (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
+
+/* OPP HIGH FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
+ {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
+static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
+ {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
+ {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
+ {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
+ {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+ {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
+ {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
+ {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
+ {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
+ {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
+ {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
+ {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
+ {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
+ {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
+ {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
+ {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
+ {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
+ {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
+ {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
+ {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
+ {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
+ {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
+ {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+ {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+};
+
+static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
+ {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+ {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+};
+
+struct dplls omap5_dplls_es1 = {
+ .mpu = mpu_dpll_params_800mhz,
+ .core = core_dpll_params_2128mhz_ddr532,
+ .per = per_dpll_params_768mhz,
+ .iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap5_dplls_es2 = {
+ .mpu = mpu_dpll_params_1100mhz,
+ .core = core_dpll_params_2128mhz_ddr532_es2,
+ .per = per_dpll_params_768mhz_es2,
+ .iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls dra7xx_dplls = {
+ .mpu = mpu_dpll_params_1ghz,
+ .core = core_dpll_params_2128mhz_ddr532_dra7xx,
+ .per = per_dpll_params_768mhz_dra7xx,
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = ddr_dpll_params_1066mhz,
+};
+
+struct pmic_data palmas = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 10000, /* 10 mV represented in uV */
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ .start_code = 6,
+};
+
+struct vcores_data omap5430_volts = {
+ .mpu.value = VDD_MPU,
+ .mpu.addr = SMPS_REG_ADDR_12_MPU,
+ .mpu.pmic = &palmas,
+
+ .core.value = VDD_CORE,
+ .core.addr = SMPS_REG_ADDR_8_CORE,
+ .core.pmic = &palmas,
+
+ .mm.value = VDD_MM,
+ .mm.addr = SMPS_REG_ADDR_45_IVA,
+ .mm.pmic = &palmas,
+};
+
+struct vcores_data omap5430_volts_es2 = {
+ .mpu.value = VDD_MPU_ES2,
+ .mpu.addr = SMPS_REG_ADDR_12_MPU,
+ .mpu.pmic = &palmas,
+
+ .core.value = VDD_CORE_ES2,
+ .core.addr = SMPS_REG_ADDR_8_CORE,
+ .core.pmic = &palmas,
+
+ .mm.value = VDD_MM_ES2,
+ .mm.addr = SMPS_REG_ADDR_45_IVA,
+ .mm.pmic = &palmas,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ (*prcm)->cm_l4per_clkstctrl,
+ (*prcm)->cm_l3init_clkstctrl,
+ (*prcm)->cm_memif_clkstctrl,
+ (*prcm)->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3_gpmc_clkctrl,
+ (*prcm)->cm_memif_emif_1_clkctrl,
+ (*prcm)->cm_memif_emif_2_clkctrl,
+ (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+ (*prcm)->cm_wkup_gpio1_clkctrl,
+ (*prcm)->cm_l4per_gpio2_clkctrl,
+ (*prcm)->cm_l4per_gpio3_clkctrl,
+ (*prcm)->cm_l4per_gpio4_clkctrl,
+ (*prcm)->cm_l4per_gpio5_clkctrl,
+ (*prcm)->cm_l4per_gpio6_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_wkup_gptimer1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc2_clkctrl,
+ (*prcm)->cm_l4per_gptimer2_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_l4per_uart3_clkctrl,
+ (*prcm)->cm_l4per_i2c1_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Set the correct clock dividers for mmc */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+
+ /* Select 384Mhz for GPU as its the POR for ES1.0 */
+ setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
+ CLKSEL_GPU_HYD_GCLK_MASK);
+ setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
+ CLKSEL_GPU_CORE_GCLK_MASK);
+
+ /* Enable SCRM OPT clocks for PER and CORE dpll */
+ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+ OPTFCLKEN_SCRM_PER_MASK);
+ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+ OPTFCLKEN_SCRM_CORE_MASK);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_mcspi1_clkctrl,
+ (*prcm)->cm_l4per_i2c2_clkctrl,
+ (*prcm)->cm_l4per_i2c3_clkctrl,
+ (*prcm)->cm_l4per_i2c4_clkctrl,
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (*prcm)->cm_l3init_hsusbhost_clkctrl,
+ (*prcm)->cm_l3init_fsusb_clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_non_essential_clocks(void)
+{
+ u32 const clk_domains_non_essential[] = {
+ (*prcm)->cm_mpu_m3_clkstctrl,
+ (*prcm)->cm_ivahd_clkstctrl,
+ (*prcm)->cm_dsp_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sgx_clkstctrl,
+ (*prcm)->cm1_abe_clkstctrl,
+ (*prcm)->cm_c2c_clkstctrl,
+ (*prcm)->cm_cam_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sdma_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_non_essential[] = {
+ (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
+ (*prcm)->cm_ivahd_ivahd_clkctrl,
+ (*prcm)->cm_ivahd_sl2_clkctrl,
+ (*prcm)->cm_dsp_dsp_clkctrl,
+ (*prcm)->cm_l3instr_l3_3_clkctrl,
+ (*prcm)->cm_l3instr_l3_instr_clkctrl,
+ (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
+ (*prcm)->cm_l3init_hsi_clkctrl,
+ (*prcm)->cm_l4per_hdq1w_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_non_essential[] = {
+ (*prcm)->cm1_abe_aess_clkctrl,
+ (*prcm)->cm1_abe_pdm_clkctrl,
+ (*prcm)->cm1_abe_dmic_clkctrl,
+ (*prcm)->cm1_abe_mcasp_clkctrl,
+ (*prcm)->cm1_abe_mcbsp1_clkctrl,
+ (*prcm)->cm1_abe_mcbsp2_clkctrl,
+ (*prcm)->cm1_abe_mcbsp3_clkctrl,
+ (*prcm)->cm1_abe_slimbus_clkctrl,
+ (*prcm)->cm1_abe_timer5_clkctrl,
+ (*prcm)->cm1_abe_timer6_clkctrl,
+ (*prcm)->cm1_abe_timer7_clkctrl,
+ (*prcm)->cm1_abe_timer8_clkctrl,
+ (*prcm)->cm1_abe_wdt3_clkctrl,
+ (*prcm)->cm_l4per_gptimer9_clkctrl,
+ (*prcm)->cm_l4per_gptimer10_clkctrl,
+ (*prcm)->cm_l4per_gptimer11_clkctrl,
+ (*prcm)->cm_l4per_gptimer3_clkctrl,
+ (*prcm)->cm_l4per_gptimer4_clkctrl,
+ (*prcm)->cm_l4per_mcspi2_clkctrl,
+ (*prcm)->cm_l4per_mcspi3_clkctrl,
+ (*prcm)->cm_l4per_mcspi4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd3_clkctrl,
+ (*prcm)->cm_l4per_mmcsd4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd5_clkctrl,
+ (*prcm)->cm_l4per_uart1_clkctrl,
+ (*prcm)->cm_l4per_uart2_clkctrl,
+ (*prcm)->cm_l4per_uart4_clkctrl,
+ (*prcm)->cm_wkup_keyboard_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_cam_iss_clkctrl,
+ (*prcm)->cm_cam_fdif_clkctrl,
+ (*prcm)->cm_dss_dss_clkctrl,
+ (*prcm)->cm_sgx_sgx_clkctrl,
+ 0
+ };
+
+ /* Enable optional functional clock for ISS */
+ setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable all optional functional clocks of DSS */
+ setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
+
+ /* Put camera module in no sleep mode */
+ clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+const struct ctrl_ioregs ioregs_omap5430 = {
+ .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es1 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es2 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
+void hw_data_init(void)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+
+ case OMAP5430_ES1_0:
+ case OMAP5432_ES1_0:
+ *prcm = &omap5_es1_prcm;
+ *dplls_data = &omap5_dplls_es1;
+ *omap_vcores = &omap5430_volts;
+ *ctrl = &omap5_ctrl;
+ break;
+
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES2_0:
+ *prcm = &omap5_es2_prcm;
+ *dplls_data = &omap5_dplls_es2;
+ *omap_vcores = &omap5430_volts_es2;
+ *ctrl = &omap5_ctrl;
+ break;
+
+ case DRA752_ES1_0:
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *omap_vcores = &omap5430_volts_es2;
+ *ctrl = &dra7xx_ctrl;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
+
+void get_ioregs(const struct ctrl_ioregs **regs)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ *regs = &ioregs_omap5430;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &ioregs_omap5432_es1;
+ break;
+ case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
+ *regs = &ioregs_omap5432_es2;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index d0c3ff7021..2f4b24752b 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -32,6 +32,7 @@
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/clocks.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
@@ -56,76 +57,58 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_1));
- writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- &(ioregs_base->control_ddrio_0));
- writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- &(ioregs_base->control_ddrio_1));
- writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
- &(ioregs_base->control_ddrio_2));
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddr3ch1_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch1_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch1_1));
-
- writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddr3ch2_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch2_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch2_1));
-
- writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
- &(ioregs_base->control_ddrio_0));
- writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
- &(ioregs_base->control_ddrio_1));
- writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
- &(ioregs_base->control_ddrio_2));
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
/* omap5432 does not use lpddr2 */
- writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
- writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
- writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- &(ioregs_base->control_emif1_sdram_config_ext));
- writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- &(ioregs_base->control_emif2_sdram_config_ext));
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif1_sdram_config_ext);
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif2_sdram_config_ext);
/* Disable DLL select */
- io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+ io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
- &(ioregs_base->control_port_emif1_sdram_config));
+ (*ctrl)->control_port_emif1_sdram_config);
- io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+ io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
- &(ioregs_base->control_port_emif2_sdram_config));
+ (*ctrl)->control_port_emif2_sdram_config);
}
/*
@@ -134,88 +117,198 @@ static void io_settings_ddr3(void)
void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(ds_mask << 16) | (ds_mask << 18);
- io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
+ io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
(~mask);
io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
(ds_45_ohm << 18) | (ds_60_ohm << 2);
- writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
/* Impedance settings Mcspi2 */
mask = (ds_mask << 30);
- io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
+ io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 30);
- writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
/* Impedance settings C2C 3,4 */
mask = (ds_mask << 14) | (ds_mask << 16);
- io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
+ io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
(~mask);
io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
- writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
/* Slew rate settings EMMC, C2C 1,2 */
mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
+ io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
(~mask);
io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
- writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
/* Slew rate settings hsi2, Mcspi2 */
mask = (sc_mask << 24) | (sc_mask << 28);
- io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
+ io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
(~mask);
io_settings |= (sc_fast << 28) | (sc_fast << 24);
- writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
/* Slew rate settings C2C 3,4 */
mask = (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
+ io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
(~mask);
io_settings |= (sc_na << 16) | (sc_na << 18);
- writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
/* impedance and slew rate settings for usb */
mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
- io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
+ io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
(ds_60_ohm << 23) | (sc_fast << 20) |
(sc_fast << 17) | (sc_fast << 14);
- writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
+ writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
- if (omap_revision() <= OMAP5430_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
/* Efuse settings */
- writel(EFUSE_1, &(ioregs_base->control_efuse_1));
- writel(EFUSE_2, &(ioregs_base->control_efuse_2));
- writel(EFUSE_3, &(ioregs_base->control_efuse_3));
- writel(EFUSE_4, &(ioregs_base->control_efuse_4));
+ writel(EFUSE_1, (*ctrl)->control_efuse_1);
+ writel(EFUSE_2, (*ctrl)->control_efuse_2);
+ writel(EFUSE_3, (*ctrl)->control_efuse_3);
+ writel(EFUSE_4, (*ctrl)->control_efuse_4);
+}
+
+static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
+ {0x45, 0x1}, /* 12 MHz */
+ {-1, -1}, /* 13 MHz */
+ {0x63, 0x2}, /* 16.8 MHz */
+ {0x57, 0x2}, /* 19.2 MHz */
+ {0x20, 0x1}, /* 26 MHz */
+ {-1, -1}, /* 27 MHz */
+ {0x41, 0x3} /* 38.4 MHz */
+};
+
+void srcomp_enable(void)
+{
+ u32 srcomp_value, mul_factor, div_factor, clk_val, i;
+ u32 sysclk_ind = get_sys_clk_index();
+ u32 omap_rev = omap_revision();
+
+ mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
+ div_factor = srcomp_parameters[sysclk_ind].divide_factor;
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &=
+ ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor << DIVIDE_FACTOR_XS_SHIFT);
+ writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
+ clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~PWRDWN_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+
+ while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+ & SRCODE_READ_XS_MASK) >>
+ SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+ } else {
+ srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
+ DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor << DIVIDE_FACTOR_XS_SHIFT);
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+ clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+
+ for (i = 0; i < 4; i++) {
+ while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+ & SRCODE_READ_XS_MASK) >>
+ SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
+ SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+ }
}
#endif
void config_data_eye_leveling_samples(u32 emif_base)
{
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
- &(ioregs_base->control_emif1_sdram_config_ext));
+ (*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
- &(ioregs_base->control_emif2_sdram_config_ext));
+ (*ctrl)->control_emif2_sdram_config_ext);
}
void init_omap_revision(void)
@@ -227,17 +320,25 @@ void init_omap_revision(void)
*/
unsigned int rev = cortex_rev();
- switch (rev) {
- case MIDR_CORTEX_A15_R0P0:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP5430_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP5430_ES1_0;
- break;
- case OMAP5432_CONTROL_ID_CODE_ES1_0:
- default:
- *omap_si_rev = OMAP5432_ES1_0;
- break;
- }
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP5430_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5430_ES1_0;
+ if (rev == MIDR_CORTEX_A15_R2P2)
+ *omap_si_rev = OMAP5430_ES2_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5432_ES1_0;
+ if (rev == MIDR_CORTEX_A15_R2P2)
+ *omap_si_rev = OMAP5432_ES2_0;
+ break;
+ case OMAP5430_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5430_ES2_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5432_ES2_0;
+ break;
+ case DRA752_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = DRA752_ES1_0;
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
@@ -253,7 +354,12 @@ void reset_cpu(ulong ignored)
* So use cold reset in case instead.
*/
if (omap_rev == OMAP5430_ES1_0)
- writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
+ writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
else
- writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+ writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
+}
+
+u32 warm_reset(void)
+{
+ return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
new file mode 100644
index 0000000000..b8a61fe881
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -0,0 +1,958 @@
+/*
+ *
+ * HW regs data for OMAP5 Soc
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap5_es1_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a004100,
+ .cm_clksel_abe = 0x4a004108,
+ .cm_dll_ctrl = 0x4a004110,
+ .cm_clkmode_dpll_core = 0x4a004120,
+ .cm_idlest_dpll_core = 0x4a004124,
+ .cm_autoidle_dpll_core = 0x4a004128,
+ .cm_clksel_dpll_core = 0x4a00412c,
+ .cm_div_m2_dpll_core = 0x4a004130,
+ .cm_div_m3_dpll_core = 0x4a004134,
+ .cm_div_h11_dpll_core = 0x4a004138,
+ .cm_div_h12_dpll_core = 0x4a00413c,
+ .cm_div_h13_dpll_core = 0x4a004140,
+ .cm_div_h14_dpll_core = 0x4a004144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a004148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+ .cm_emu_override_dpll_core = 0x4a004150,
+ .cm_div_h22_dpllcore = 0x4a004154,
+ .cm_div_h23_dpll_core = 0x4a004158,
+ .cm_clkmode_dpll_mpu = 0x4a004160,
+ .cm_idlest_dpll_mpu = 0x4a004164,
+ .cm_autoidle_dpll_mpu = 0x4a004168,
+ .cm_clksel_dpll_mpu = 0x4a00416c,
+ .cm_div_m2_dpll_mpu = 0x4a004170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+ .cm_bypclk_dpll_mpu = 0x4a00419c,
+ .cm_clkmode_dpll_iva = 0x4a0041a0,
+ .cm_idlest_dpll_iva = 0x4a0041a4,
+ .cm_autoidle_dpll_iva = 0x4a0041a8,
+ .cm_clksel_dpll_iva = 0x4a0041ac,
+ .cm_div_h11_dpll_iva = 0x4a0041b8,
+ .cm_div_h12_dpll_iva = 0x4a0041bc,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+ .cm_bypclk_dpll_iva = 0x4a0041dc,
+ .cm_clkmode_dpll_abe = 0x4a0041e0,
+ .cm_idlest_dpll_abe = 0x4a0041e4,
+ .cm_autoidle_dpll_abe = 0x4a0041e8,
+ .cm_clksel_dpll_abe = 0x4a0041ec,
+ .cm_div_m2_dpll_abe = 0x4a0041f0,
+ .cm_div_m3_dpll_abe = 0x4a0041f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+ .cm_clkmode_dpll_ddrphy = 0x4a004220,
+ .cm_idlest_dpll_ddrphy = 0x4a004224,
+ .cm_autoidle_dpll_ddrphy = 0x4a004228,
+ .cm_clksel_dpll_ddrphy = 0x4a00422c,
+ .cm_div_m2_dpll_ddrphy = 0x4a004230,
+ .cm_div_h11_dpll_ddrphy = 0x4a004238,
+ .cm_div_h12_dpll_ddrphy = 0x4a00423c,
+ .cm_div_h13_dpll_ddrphy = 0x4a004240,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+ .cm_shadow_freq_config1 = 0x4a004260,
+ .cm_mpu_mpu_clkctrl = 0x4a004320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a004400,
+ .cm_dsp_dsp_clkctrl = 0x4a004420,
+
+ /* cm1.abe */
+ .cm1_abe_clkstctrl = 0x4a004500,
+ .cm1_abe_l4abe_clkctrl = 0x4a004520,
+ .cm1_abe_aess_clkctrl = 0x4a004528,
+ .cm1_abe_pdm_clkctrl = 0x4a004530,
+ .cm1_abe_dmic_clkctrl = 0x4a004538,
+ .cm1_abe_mcasp_clkctrl = 0x4a004540,
+ .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+ .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+ .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+ .cm1_abe_slimbus_clkctrl = 0x4a004560,
+ .cm1_abe_timer5_clkctrl = 0x4a004568,
+ .cm1_abe_timer6_clkctrl = 0x4a004570,
+ .cm1_abe_timer7_clkctrl = 0x4a004578,
+ .cm1_abe_timer8_clkctrl = 0x4a004580,
+ .cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+ /* cm2.ckgen */
+ .cm_clksel_mpu_m3_iss_root = 0x4a008100,
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_scale_fclk = 0x4a008108,
+ .cm_core_dvfs_perf1 = 0x4a008110,
+ .cm_core_dvfs_perf2 = 0x4a008114,
+ .cm_core_dvfs_perf3 = 0x4a008118,
+ .cm_core_dvfs_perf4 = 0x4a00811c,
+ .cm_core_dvfs_current = 0x4a008124,
+ .cm_iva_dvfs_perf_tesla = 0x4a008128,
+ .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+ .cm_iva_dvfs_perf_abe = 0x4a008130,
+ .cm_iva_dvfs_current = 0x4a008138,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_h11_dpll_per = 0x4a008158,
+ .cm_div_h12_dpll_per = 0x4a00815c,
+ .cm_div_h14_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_emu_override_dpll_per = 0x4a008170,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_unipro = 0x4a0081c0,
+ .cm_idlest_dpll_unipro = 0x4a0081c4,
+ .cm_autoidle_dpll_unipro = 0x4a0081c8,
+ .cm_clksel_dpll_unipro = 0x4a0081cc,
+ .cm_div_m2_dpll_unipro = 0x4a0081d0,
+ .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+ .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+ /* cm2.core */
+ .cm_coreaon_bandgap_clkctrl = 0x4a008648,
+ .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_2_clkstctrl = 0x4a008800,
+ .cm_l3_2_dynamicdep = 0x4a008808,
+ .cm_l3_2_l3_2_clkctrl = 0x4a008820,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_memif_emif_h1_clkctrl = 0x4a008b50,
+ .cm_memif_emif_h2_clkctrl = 0x4a008b58,
+ .cm_memif_dll_h_clkctrl = 0x4a008b60,
+ .cm_c2c_clkstctrl = 0x4a008c00,
+ .cm_c2c_staticdep = 0x4a008c04,
+ .cm_c2c_dynamicdep = 0x4a008c08,
+ .cm_c2c_sad2d_clkctrl = 0x4a008c20,
+ .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+ .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+
+ /* cm2.ivahd */
+ .cm_ivahd_clkstctrl = 0x4a008f00,
+ .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+ .cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009000,
+ .cm_cam_iss_clkctrl = 0x4a009020,
+ .cm_cam_fdif_clkctrl = 0x4a009028,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009100,
+ .cm_dss_dss_clkctrl = 0x4a009120,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009200,
+ .cm_sgx_sgx_clkctrl = 0x4a009220,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009300,
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+ .cm_l3init_hsi_clkctrl = 0x4a009338,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+ .cm_l3init_p1500_clkctrl = 0x4a009378,
+ .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+ .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+
+ /* cm2.l4per */
+ .cm_l4per_clkstctrl = 0x4a009400,
+ .cm_l4per_dynamicdep = 0x4a009408,
+ .cm_l4per_adc_clkctrl = 0x4a009420,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009428,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009430,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009438,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009440,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009448,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009450,
+ .cm_l4per_elm_clkctrl = 0x4a009458,
+ .cm_l4per_gpio2_clkctrl = 0x4a009460,
+ .cm_l4per_gpio3_clkctrl = 0x4a009468,
+ .cm_l4per_gpio4_clkctrl = 0x4a009470,
+ .cm_l4per_gpio5_clkctrl = 0x4a009478,
+ .cm_l4per_gpio6_clkctrl = 0x4a009480,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009488,
+ .cm_l4per_hecc1_clkctrl = 0x4a009490,
+ .cm_l4per_hecc2_clkctrl = 0x4a009498,
+ .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0094c0,
+ .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+ .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+ .cm_l4per_mgate_clkctrl = 0x4a0094e8,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009500,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009508,
+ .cm_l4per_gpio7_clkctrl = 0x4a009510,
+ .cm_l4per_gpio8_clkctrl = 0x4a009518,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+ .cm_l4per_msprohg_clkctrl = 0x4a009530,
+ .cm_l4per_slimbus2_clkctrl = 0x4a009538,
+ .cm_l4per_uart1_clkctrl = 0x4a009540,
+ .cm_l4per_uart2_clkctrl = 0x4a009548,
+ .cm_l4per_uart3_clkctrl = 0x4a009550,
+ .cm_l4per_uart4_clkctrl = 0x4a009558,
+ .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+ .cm_l4per_i2c5_clkctrl = 0x4a009568,
+ .cm_l4per_uart5_clkctrl = 0x4a009570,
+ .cm_l4per_uart6_clkctrl = 0x4a009578,
+ .cm_l4sec_clkstctrl = 0x4a009580,
+ .cm_l4sec_staticdep = 0x4a009584,
+ .cm_l4sec_dynamicdep = 0x4a009588,
+ .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+ .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+ .cm_l4sec_rng_clkctrl = 0x4a0095c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4ae0610c,
+ .cm_sys_clksel = 0x4ae06110,
+ .cm_wkup_clkstctrl = 0x4ae07800,
+ .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
+ .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
+ .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
+ .cm_wkup_gpio1_clkctrl = 0x4ae07838,
+ .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
+ .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
+ .cm_wkup_synctimer_clkctrl = 0x4ae07850,
+ .cm_wkup_usim_clkctrl = 0x4ae07858,
+ .cm_wkup_sarram_clkctrl = 0x4ae07860,
+ .cm_wkup_keyboard_clkctrl = 0x4ae07878,
+ .cm_wkup_rtc_clkctrl = 0x4ae07880,
+ .cm_wkup_bandgap_clkctrl = 0x4ae07888,
+ .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
+ .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
+ .prm_rstctrl = 0x4ae07b00,
+ .prm_rstst = 0x4ae07b04,
+ .prm_vc_val_bypass = 0x4ae07ba0,
+ .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
+ .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
+ .prm_sldo_core_setup = 0x4ae07bc4,
+ .prm_sldo_core_ctrl = 0x4ae07bc8,
+ .prm_sldo_mpu_setup = 0x4ae07bcc,
+ .prm_sldo_mpu_ctrl = 0x4ae07bd0,
+ .prm_sldo_mm_setup = 0x4ae07bd4,
+ .prm_sldo_mm_ctrl = 0x4ae07bd8,
+};
+
+struct omap_sys_ctrl_regs const omap5_ctrl = {
+ .control_status = 0x4A002134,
+ .control_paconf_global = 0x4A002DA0,
+ .control_paconf_mode = 0x4A002DA4,
+ .control_smart1io_padconf_0 = 0x4A002DA8,
+ .control_smart1io_padconf_1 = 0x4A002DAC,
+ .control_smart1io_padconf_2 = 0x4A002DB0,
+ .control_smart2io_padconf_0 = 0x4A002DB4,
+ .control_smart2io_padconf_1 = 0x4A002DB8,
+ .control_smart2io_padconf_2 = 0x4A002DBC,
+ .control_smart3io_padconf_0 = 0x4A002DC0,
+ .control_smart3io_padconf_1 = 0x4A002DC4,
+ .control_pbias = 0x4A002E00,
+ .control_i2c_0 = 0x4A002E04,
+ .control_camera_rx = 0x4A002E08,
+ .control_hdmi_tx_phy = 0x4A002E0C,
+ .control_uniportm = 0x4A002E10,
+ .control_dsiphy = 0x4A002E14,
+ .control_mcbsplp = 0x4A002E18,
+ .control_usb2phycore = 0x4A002E1C,
+ .control_hdmi_1 = 0x4A002E20,
+ .control_hsi = 0x4A002E24,
+ .control_ddr3ch1_0 = 0x4A002E30,
+ .control_ddr3ch2_0 = 0x4A002E34,
+ .control_ddrch1_0 = 0x4A002E38,
+ .control_ddrch1_1 = 0x4A002E3C,
+ .control_ddrch2_0 = 0x4A002E40,
+ .control_ddrch2_1 = 0x4A002E44,
+ .control_lpddr2ch1_0 = 0x4A002E48,
+ .control_lpddr2ch1_1 = 0x4A002E4C,
+ .control_ddrio_0 = 0x4A002E50,
+ .control_ddrio_1 = 0x4A002E54,
+ .control_ddrio_2 = 0x4A002E58,
+ .control_hyst_1 = 0x4A002E5C,
+ .control_usbb_hsic_control = 0x4A002E60,
+ .control_c2c = 0x4A002E64,
+ .control_core_control_spare_rw = 0x4A002E68,
+ .control_core_control_spare_r = 0x4A002E6C,
+ .control_core_control_spare_r_c0 = 0x4A002E70,
+ .control_srcomp_north_side = 0x4A002E74,
+ .control_srcomp_south_side = 0x4A002E78,
+ .control_srcomp_east_side = 0x4A002E7C,
+ .control_srcomp_west_side = 0x4A002E80,
+ .control_srcomp_code_latch = 0x4A002E84,
+ .control_port_emif1_sdram_config = 0x4AE0C110,
+ .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
+ .control_port_emif2_sdram_config = 0x4AE0C118,
+ .control_emif1_sdram_config_ext = 0x4AE0C144,
+ .control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
+ .control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
+ .control_padconf_mode = 0x4AE0CDA8,
+ .control_xtal_oscillator = 0x4AE0CDAC,
+ .control_i2c_2 = 0x4AE0CDB0,
+ .control_ckobuffer = 0x4AE0CDB4,
+ .control_wkup_control_spare_rw = 0x4AE0CDB8,
+ .control_wkup_control_spare_r = 0x4AE0CDBC,
+ .control_wkup_control_spare_r_c0 = 0x4AE0CDC0,
+ .control_srcomp_east_side_wkup = 0x4AE0CDC4,
+ .control_efuse_1 = 0x4AE0CDC8,
+ .control_efuse_2 = 0x4AE0CDCC,
+ .control_efuse_3 = 0x4AE0CDD0,
+ .control_efuse_4 = 0x4AE0CDD4,
+ .control_efuse_5 = 0x4AE0CDD8,
+ .control_efuse_6 = 0x4AE0CDDC,
+ .control_efuse_7 = 0x4AE0CDE0,
+ .control_efuse_8 = 0x4AE0CDE4,
+ .control_efuse_9 = 0x4AE0CDE8,
+ .control_efuse_10 = 0x4AE0CDEC,
+ .control_efuse_11 = 0x4AE0CDF0,
+ .control_efuse_12 = 0x4AE0CDF4,
+ .control_efuse_13 = 0x4AE0CDF8,
+};
+
+struct omap_sys_ctrl_regs const dra7xx_ctrl = {
+ .control_status = 0x4A002134,
+ .control_core_mmr_lock1 = 0x4A002540,
+ .control_core_mmr_lock2 = 0x4A002544,
+ .control_core_mmr_lock3 = 0x4A002548,
+ .control_core_mmr_lock4 = 0x4A00254C,
+ .control_core_mmr_lock5 = 0x4A002550,
+ .control_core_control_io1 = 0x4A002554,
+ .control_core_control_io2 = 0x4A002558,
+ .control_paconf_global = 0x4A002DA0,
+ .control_paconf_mode = 0x4A002DA4,
+ .control_smart1io_padconf_0 = 0x4A002DA8,
+ .control_smart1io_padconf_1 = 0x4A002DAC,
+ .control_smart1io_padconf_2 = 0x4A002DB0,
+ .control_smart2io_padconf_0 = 0x4A002DB4,
+ .control_smart2io_padconf_1 = 0x4A002DB8,
+ .control_smart2io_padconf_2 = 0x4A002DBC,
+ .control_smart3io_padconf_0 = 0x4A002DC0,
+ .control_smart3io_padconf_1 = 0x4A002DC4,
+ .control_pbias = 0x4A002E00,
+ .control_i2c_0 = 0x4A002E04,
+ .control_camera_rx = 0x4A002E08,
+ .control_hdmi_tx_phy = 0x4A002E0C,
+ .control_uniportm = 0x4A002E10,
+ .control_dsiphy = 0x4A002E14,
+ .control_mcbsplp = 0x4A002E18,
+ .control_usb2phycore = 0x4A002E1C,
+ .control_hdmi_1 = 0x4A002E20,
+ .control_hsi = 0x4A002E24,
+ .control_ddr3ch1_0 = 0x4A002E30,
+ .control_ddr3ch2_0 = 0x4A002E34,
+ .control_ddrch1_0 = 0x4A002E38,
+ .control_ddrch1_1 = 0x4A002E3C,
+ .control_ddrch2_0 = 0x4A002E40,
+ .control_ddrch2_1 = 0x4A002E44,
+ .control_lpddr2ch1_0 = 0x4A002E48,
+ .control_lpddr2ch1_1 = 0x4A002E4C,
+ .control_ddrio_0 = 0x4A002E50,
+ .control_ddrio_1 = 0x4A002E54,
+ .control_ddrio_2 = 0x4A002E58,
+ .control_hyst_1 = 0x4A002E5C,
+ .control_usbb_hsic_control = 0x4A002E60,
+ .control_c2c = 0x4A002E64,
+ .control_core_control_spare_rw = 0x4A002E68,
+ .control_core_control_spare_r = 0x4A002E6C,
+ .control_core_control_spare_r_c0 = 0x4A002E70,
+ .control_srcomp_north_side = 0x4A002E74,
+ .control_srcomp_south_side = 0x4A002E78,
+ .control_srcomp_east_side = 0x4A002E7C,
+ .control_srcomp_west_side = 0x4A002E80,
+ .control_srcomp_code_latch = 0x4A002E84,
+ .control_padconf_core_base = 0x4A003400,
+ .control_port_emif1_sdram_config = 0x4AE0C110,
+ .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
+ .control_port_emif2_sdram_config = 0x4AE0C118,
+ .control_emif1_sdram_config_ext = 0x4AE0C144,
+ .control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_padconf_mode = 0x4AE0C5A0,
+ .control_xtal_oscillator = 0x4AE0C5A4,
+ .control_i2c_2 = 0x4AE0C5A8,
+ .control_ckobuffer = 0x4AE0C5AC,
+ .control_wkup_control_spare_rw = 0x4AE0C5B0,
+ .control_wkup_control_spare_r = 0x4AE0C5B4,
+ .control_wkup_control_spare_r_c0 = 0x4AE0C5B8,
+ .control_srcomp_east_side_wkup = 0x4AE0C5BC,
+ .control_efuse_1 = 0x4AE0C5C0,
+ .control_efuse_2 = 0x4AE0C5C4,
+ .control_efuse_3 = 0x4AE0C5C8,
+ .control_efuse_4 = 0x4AE0C5CC,
+ .control_efuse_13 = 0x4AE0C5F0,
+};
+
+struct prcm_regs const omap5_es2_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a004100,
+ .cm_clksel_abe = 0x4a004108,
+ .cm_dll_ctrl = 0x4a004110,
+ .cm_clkmode_dpll_core = 0x4a004120,
+ .cm_idlest_dpll_core = 0x4a004124,
+ .cm_autoidle_dpll_core = 0x4a004128,
+ .cm_clksel_dpll_core = 0x4a00412c,
+ .cm_div_m2_dpll_core = 0x4a004130,
+ .cm_div_m3_dpll_core = 0x4a004134,
+ .cm_div_h11_dpll_core = 0x4a004138,
+ .cm_div_h12_dpll_core = 0x4a00413c,
+ .cm_div_h13_dpll_core = 0x4a004140,
+ .cm_div_h14_dpll_core = 0x4a004144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a004148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+ .cm_div_h21_dpll_core = 0x4a004150,
+ .cm_div_h22_dpllcore = 0x4a004154,
+ .cm_div_h23_dpll_core = 0x4a004158,
+ .cm_div_h24_dpll_core = 0x4a00415c,
+ .cm_clkmode_dpll_mpu = 0x4a004160,
+ .cm_idlest_dpll_mpu = 0x4a004164,
+ .cm_autoidle_dpll_mpu = 0x4a004168,
+ .cm_clksel_dpll_mpu = 0x4a00416c,
+ .cm_div_m2_dpll_mpu = 0x4a004170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+ .cm_bypclk_dpll_mpu = 0x4a00419c,
+ .cm_clkmode_dpll_iva = 0x4a0041a0,
+ .cm_idlest_dpll_iva = 0x4a0041a4,
+ .cm_autoidle_dpll_iva = 0x4a0041a8,
+ .cm_clksel_dpll_iva = 0x4a0041ac,
+ .cm_div_h11_dpll_iva = 0x4a0041b8,
+ .cm_div_h12_dpll_iva = 0x4a0041bc,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+ .cm_bypclk_dpll_iva = 0x4a0041dc,
+ .cm_clkmode_dpll_abe = 0x4a0041e0,
+ .cm_idlest_dpll_abe = 0x4a0041e4,
+ .cm_autoidle_dpll_abe = 0x4a0041e8,
+ .cm_clksel_dpll_abe = 0x4a0041ec,
+ .cm_div_m2_dpll_abe = 0x4a0041f0,
+ .cm_div_m3_dpll_abe = 0x4a0041f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+ .cm_clkmode_dpll_ddrphy = 0x4a004220,
+ .cm_idlest_dpll_ddrphy = 0x4a004224,
+ .cm_autoidle_dpll_ddrphy = 0x4a004228,
+ .cm_clksel_dpll_ddrphy = 0x4a00422c,
+ .cm_div_m2_dpll_ddrphy = 0x4a004230,
+ .cm_div_h11_dpll_ddrphy = 0x4a004238,
+ .cm_div_h12_dpll_ddrphy = 0x4a00423c,
+ .cm_div_h13_dpll_ddrphy = 0x4a004240,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+ .cm_shadow_freq_config1 = 0x4a004260,
+ .cm_mpu_mpu_clkctrl = 0x4a004320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a004400,
+ .cm_dsp_dsp_clkctrl = 0x4a004420,
+
+ /* cm1.abe */
+ .cm1_abe_clkstctrl = 0x4a004500,
+ .cm1_abe_l4abe_clkctrl = 0x4a004520,
+ .cm1_abe_aess_clkctrl = 0x4a004528,
+ .cm1_abe_pdm_clkctrl = 0x4a004530,
+ .cm1_abe_dmic_clkctrl = 0x4a004538,
+ .cm1_abe_mcasp_clkctrl = 0x4a004540,
+ .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+ .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+ .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+ .cm1_abe_slimbus_clkctrl = 0x4a004560,
+ .cm1_abe_timer5_clkctrl = 0x4a004568,
+ .cm1_abe_timer6_clkctrl = 0x4a004570,
+ .cm1_abe_timer7_clkctrl = 0x4a004578,
+ .cm1_abe_timer8_clkctrl = 0x4a004580,
+ .cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+
+
+ /* cm2.ckgen */
+ .cm_clksel_mpu_m3_iss_root = 0x4a008100,
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_scale_fclk = 0x4a008108,
+ .cm_core_dvfs_perf1 = 0x4a008110,
+ .cm_core_dvfs_perf2 = 0x4a008114,
+ .cm_core_dvfs_perf3 = 0x4a008118,
+ .cm_core_dvfs_perf4 = 0x4a00811c,
+ .cm_core_dvfs_current = 0x4a008124,
+ .cm_iva_dvfs_perf_tesla = 0x4a008128,
+ .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+ .cm_iva_dvfs_perf_abe = 0x4a008130,
+ .cm_iva_dvfs_current = 0x4a008138,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_h11_dpll_per = 0x4a008158,
+ .cm_div_h12_dpll_per = 0x4a00815c,
+ .cm_div_h13_dpll_per = 0x4a008160,
+ .cm_div_h14_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_emu_override_dpll_per = 0x4a008170,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_unipro = 0x4a0081c0,
+ .cm_idlest_dpll_unipro = 0x4a0081c4,
+ .cm_autoidle_dpll_unipro = 0x4a0081c8,
+ .cm_clksel_dpll_unipro = 0x4a0081cc,
+ .cm_div_m2_dpll_unipro = 0x4a0081d0,
+ .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+ .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+ .cm_coreaon_bandgap_clkctrl = 0x4a008648,
+ .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
+
+ /* cm2.core */
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_2_clkstctrl = 0x4a008800,
+ .cm_l3_2_dynamicdep = 0x4a008808,
+ .cm_l3_2_l3_2_clkctrl = 0x4a008820,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_memif_emif_h1_clkctrl = 0x4a008b50,
+ .cm_memif_emif_h2_clkctrl = 0x4a008b58,
+ .cm_memif_dll_h_clkctrl = 0x4a008b60,
+ .cm_c2c_clkstctrl = 0x4a008c00,
+ .cm_c2c_staticdep = 0x4a008c04,
+ .cm_c2c_dynamicdep = 0x4a008c08,
+ .cm_c2c_sad2d_clkctrl = 0x4a008c20,
+ .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+ .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+ .cm_l4per_clkstctrl = 0x4a009000,
+ .cm_l4per_dynamicdep = 0x4a009008,
+ .cm_l4per_adc_clkctrl = 0x4a009020,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009028,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009030,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009038,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009040,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009048,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009050,
+ .cm_l4per_elm_clkctrl = 0x4a009058,
+ .cm_l4per_gpio2_clkctrl = 0x4a009060,
+ .cm_l4per_gpio3_clkctrl = 0x4a009068,
+ .cm_l4per_gpio4_clkctrl = 0x4a009070,
+ .cm_l4per_gpio5_clkctrl = 0x4a009078,
+ .cm_l4per_gpio6_clkctrl = 0x4a009080,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009088,
+ .cm_l4per_hecc1_clkctrl = 0x4a009090,
+ .cm_l4per_hecc2_clkctrl = 0x4a009098,
+ .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0090c0,
+ .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
+ .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
+ .cm_l4per_mgate_clkctrl = 0x4a0090e8,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009100,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009108,
+ .cm_l4per_gpio7_clkctrl = 0x4a009110,
+ .cm_l4per_gpio8_clkctrl = 0x4a009118,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
+ .cm_l4per_msprohg_clkctrl = 0x4a009130,
+ .cm_l4per_slimbus2_clkctrl = 0x4a009138,
+ .cm_l4per_uart1_clkctrl = 0x4a009140,
+ .cm_l4per_uart2_clkctrl = 0x4a009148,
+ .cm_l4per_uart3_clkctrl = 0x4a009150,
+ .cm_l4per_uart4_clkctrl = 0x4a009158,
+ .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
+ .cm_l4per_i2c5_clkctrl = 0x4a009168,
+ .cm_l4per_uart5_clkctrl = 0x4a009170,
+ .cm_l4per_uart6_clkctrl = 0x4a009178,
+ .cm_l4sec_clkstctrl = 0x4a009180,
+ .cm_l4sec_staticdep = 0x4a009184,
+ .cm_l4sec_dynamicdep = 0x4a009188,
+ .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
+ .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
+ .cm_l4sec_rng_clkctrl = 0x4a0091c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
+
+ /* cm2.ivahd */
+ .cm_ivahd_clkstctrl = 0x4a009200,
+ .cm_ivahd_ivahd_clkctrl = 0x4a009220,
+ .cm_ivahd_sl2_clkctrl = 0x4a009228,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009300,
+ .cm_cam_iss_clkctrl = 0x4a009320,
+ .cm_cam_fdif_clkctrl = 0x4a009328,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009400,
+ .cm_dss_dss_clkctrl = 0x4a009420,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009500,
+ .cm_sgx_sgx_clkctrl = 0x4a009520,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009600,
+
+ /* cm2.l3init */
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
+ .cm_l3init_hsi_clkctrl = 0x4a009638,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
+ .cm_l3init_p1500_clkctrl = 0x4a009678,
+ .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
+ .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4ae0610c,
+ .cm_sys_clksel = 0x4ae06110,
+ .cm_wkup_clkstctrl = 0x4ae07900,
+ .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
+ .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
+ .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
+ .cm_wkup_gpio1_clkctrl = 0x4ae07938,
+ .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
+ .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
+ .cm_wkup_synctimer_clkctrl = 0x4ae07950,
+ .cm_wkup_usim_clkctrl = 0x4ae07958,
+ .cm_wkup_sarram_clkctrl = 0x4ae07960,
+ .cm_wkup_keyboard_clkctrl = 0x4ae07978,
+ .cm_wkup_rtc_clkctrl = 0x4ae07980,
+ .cm_wkup_bandgap_clkctrl = 0x4ae07988,
+ .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
+ .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
+ .prm_rstctrl = 0x4ae07c00,
+ .prm_rstst = 0x4ae07c04,
+ .prm_vc_val_bypass = 0x4ae07ca0,
+ .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
+ .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
+
+ .prm_sldo_core_setup = 0x4ae07cc4,
+ .prm_sldo_core_ctrl = 0x4ae07cc8,
+ .prm_sldo_mpu_setup = 0x4ae07ccc,
+ .prm_sldo_mpu_ctrl = 0x4ae07cd0,
+ .prm_sldo_mm_setup = 0x4ae07cd4,
+ .prm_sldo_mm_ctrl = 0x4ae07cd8,
+};
+
+struct prcm_regs const dra7xx_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a005100,
+ .cm_clksel_abe = 0x4a005108,
+ .cm_dll_ctrl = 0x4a005110,
+ .cm_clkmode_dpll_core = 0x4a005120,
+ .cm_idlest_dpll_core = 0x4a005124,
+ .cm_autoidle_dpll_core = 0x4a005128,
+ .cm_clksel_dpll_core = 0x4a00512c,
+ .cm_div_m2_dpll_core = 0x4a005130,
+ .cm_div_m3_dpll_core = 0x4a005134,
+ .cm_div_h11_dpll_core = 0x4a005138,
+ .cm_div_h12_dpll_core = 0x4a00513c,
+ .cm_div_h13_dpll_core = 0x4a005140,
+ .cm_div_h14_dpll_core = 0x4a005144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a005148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c,
+ .cm_div_h21_dpll_core = 0x4a005150,
+ .cm_div_h22_dpllcore = 0x4a005154,
+ .cm_div_h23_dpll_core = 0x4a005158,
+ .cm_div_h24_dpll_core = 0x4a00515c,
+ .cm_clkmode_dpll_mpu = 0x4a005160,
+ .cm_idlest_dpll_mpu = 0x4a005164,
+ .cm_autoidle_dpll_mpu = 0x4a005168,
+ .cm_clksel_dpll_mpu = 0x4a00516c,
+ .cm_div_m2_dpll_mpu = 0x4a005170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a005188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c,
+ .cm_bypclk_dpll_mpu = 0x4a00519c,
+ .cm_clkmode_dpll_iva = 0x4a0051a0,
+ .cm_idlest_dpll_iva = 0x4a0051a4,
+ .cm_autoidle_dpll_iva = 0x4a0051a8,
+ .cm_clksel_dpll_iva = 0x4a0051ac,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc,
+ .cm_bypclk_dpll_iva = 0x4a0051dc,
+ .cm_clkmode_dpll_abe = 0x4a0051e0,
+ .cm_idlest_dpll_abe = 0x4a0051e4,
+ .cm_autoidle_dpll_abe = 0x4a0051e8,
+ .cm_clksel_dpll_abe = 0x4a0051ec,
+ .cm_div_m2_dpll_abe = 0x4a0051f0,
+ .cm_div_m3_dpll_abe = 0x4a0051f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a005208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c,
+ .cm_clkmode_dpll_ddrphy = 0x4a005210,
+ .cm_idlest_dpll_ddrphy = 0x4a005214,
+ .cm_autoidle_dpll_ddrphy = 0x4a005218,
+ .cm_clksel_dpll_ddrphy = 0x4a00521c,
+ .cm_div_m2_dpll_ddrphy = 0x4a005220,
+ .cm_div_h11_dpll_ddrphy = 0x4a005228,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
+ .cm_clkmode_dpll_dsp = 0x4a005234,
+ .cm_shadow_freq_config1 = 0x4a005260,
+
+ /* cm1.mpu */
+ .cm_mpu_mpu_clkctrl = 0x4a005320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a005400,
+ .cm_dsp_dsp_clkctrl = 0x4a005420,
+
+ /* cm2.ckgen */
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_h11_dpll_per = 0x4a008158,
+ .cm_div_h12_dpll_per = 0x4a00815c,
+ .cm_div_h13_dpll_per = 0x4a008160,
+ .cm_div_h14_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_pcie_ref = 0x4a008200,
+ .cm_clkmode_apll_pcie = 0x4a00821c,
+ .cm_idlest_apll_pcie = 0x4a008220,
+ .cm_div_m2_apll_pcie = 0x4a008224,
+ .cm_clkvcoldo_apll_pcie = 0x4a008228,
+
+ /* cm2.core */
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_gpmc_clkctrl = 0x4a008728,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+
+ /* cm2.ivahd */
+ .cm_ivahd_clkstctrl = 0x4a008f00,
+ .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+ .cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009000,
+ .cm_cam_vip1_clkctrl = 0x4a009020,
+ .cm_cam_vip2_clkctrl = 0x4a009028,
+ .cm_cam_vip3_clkctrl = 0x4a009030,
+ .cm_cam_lvdsrx_clkctrl = 0x4a009038,
+ .cm_cam_csi1_clkctrl = 0x4a009040,
+ .cm_cam_csi2_clkctrl = 0x4a009048,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009100,
+ .cm_dss_dss_clkctrl = 0x4a009120,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009200,
+ .cm_sgx_sgx_clkctrl = 0x4a009220,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009300,
+
+ /* cm2.l3init */
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009340,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009348,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009350,
+ .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+
+ /* cm2.l4per */
+ .cm_l4per_clkstctrl = 0x4a009700,
+ .cm_l4per_dynamicdep = 0x4a009708,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009728,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009730,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009738,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009740,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009748,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009750,
+ .cm_l4per_elm_clkctrl = 0x4a009758,
+ .cm_l4per_gpio2_clkctrl = 0x4a009760,
+ .cm_l4per_gpio3_clkctrl = 0x4a009768,
+ .cm_l4per_gpio4_clkctrl = 0x4a009770,
+ .cm_l4per_gpio5_clkctrl = 0x4a009778,
+ .cm_l4per_gpio6_clkctrl = 0x4a009780,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009788,
+ .cm_l4per_i2c1_clkctrl = 0x4a0097a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0097a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0097b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0097b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0097c0,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0097f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0097f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009800,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009808,
+ .cm_l4per_gpio7_clkctrl = 0x4a009810,
+ .cm_l4per_gpio8_clkctrl = 0x4a009818,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009820,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009828,
+ .cm_l4per_uart1_clkctrl = 0x4a009840,
+ .cm_l4per_uart2_clkctrl = 0x4a009848,
+ .cm_l4per_uart3_clkctrl = 0x4a009850,
+ .cm_l4per_uart4_clkctrl = 0x4a009858,
+ .cm_l4per_uart5_clkctrl = 0x4a009870,
+ .cm_l4sec_clkstctrl = 0x4a009880,
+ .cm_l4sec_staticdep = 0x4a009884,
+ .cm_l4sec_dynamicdep = 0x4a009888,
+ .cm_l4sec_aes1_clkctrl = 0x4a0098a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0098a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0098b0,
+ .cm_l4sec_rng_clkctrl = 0x4a0098c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4ae0610c,
+ .cm_sys_clksel = 0x4ae06110,
+ .cm_wkup_clkstctrl = 0x4ae07800,
+ .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
+ .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
+ .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
+ .cm_wkup_gpio1_clkctrl = 0x4ae07838,
+ .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
+ .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
+ .cm_wkup_sarram_clkctrl = 0x4ae07860,
+ .cm_wkup_keyboard_clkctrl = 0x4ae07878,
+ .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
+ .prm_rstctrl = 0x4ae07d00,
+ .prm_rstst = 0x4ae07d04,
+ .prm_vc_val_bypass = 0x4ae07da0,
+ .prm_vc_cfg_i2c_mode = 0x4ae07db4,
+ .prm_vc_cfg_i2c_clk = 0x4ae07db8,
+};
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 6ebdf5fbfd..6b461e4846 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -67,6 +67,25 @@ const struct emif_regs emif_regs_532_mhz_2cs = {
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
+const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
+ .sdram_config_init = 0x80800EBA,
+ .sdram_config = 0x808022BA,
+ .ref_ctrl = 0x0000081A,
+ .sdram_tim1 = 0x772F6873,
+ .sdram_tim2 = 0x304a129a,
+ .sdram_tim3 = 0x02f7e45f,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x100b3215,
+ .temp_alert_config = 0x08000a05,
+ .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
+ .emif_ddr_phy_ctlr_1 = 0x0E30400d,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
+ .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
+ .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
+ .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
+};
+
const struct emif_regs emif_regs_266_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
@@ -109,13 +128,111 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.emif_rd_wr_exec_thresh = 0x00000305
};
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x1007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0030400A,
+ .emif_ddr_phy_ctlr_1 = 0x0034400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x40000305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
- .dmm_lisa_map_3 = 0xFF020100
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x0,
+ .dmm_lisa_map_3 = 0x80500100,
+ .is_ma_present = 0x1
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ *regs = &emif_regs_532_mhz_2cs;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &emif_regs_ddr3_532_mhz_1cs;
+ break;
+ case OMAP5430_ES2_0:
+ *regs = &emif_regs_532_mhz_2cs_es2;
+ break;
+ case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
+ default:
+ *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+ }
+}
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+ __attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+ **dmm_lisa_regs)
+{
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES1_0:
+ case OMAP5432_ES2_0:
+ *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
+ break;
+ case DRA752_ES1_0:
+ default:
+ *dmm_lisa_regs = &lisa_map_512M_x_1;
+ }
+
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+ __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+#else
+
+static const struct lpddr2_device_details dev_4G_S4_details = {
+ .type = LPDDR2_TYPE_S4,
+ .density = LPDDR2_DENSITY_4Gb,
+ .io_width = LPDDR2_IO_WIDTH_32,
+ .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
};
+static void emif_get_device_details_sdp(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+{
+ /* EMIF1 & EMIF2 have identical configuration */
+ *cs0_device_details = dev_4G_S4_details;
+ *cs1_device_details = dev_4G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+ __attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
@@ -138,7 +255,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000077
};
-const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
@@ -160,54 +277,64 @@ const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000057
};
-static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
-{
- if (omap_revision() == OMAP5432_ES1_0)
- *regs = &emif_regs_ddr3_532_mhz_1cs;
- else
- *regs = &emif_regs_532_mhz_2cs;
-}
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
- __attribute__((weak, alias("emif_get_reg_dump_sdp")));
-
-static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
- **dmm_lisa_regs)
-{
- *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
-}
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
- __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
-
-#else
+const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x50D4350D,
+ 0x00000D43,
+ 0x04010040,
+ 0x01004010,
+ 0x00001004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80080080,
+ 0x00800800,
+ 0x08102040,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000057
+};
-static const struct lpddr2_device_details dev_4G_S4_details = {
- .type = LPDDR2_TYPE_S4,
- .density = LPDDR2_DENSITY_4Gb,
- .io_width = LPDDR2_IO_WIDTH_32,
- .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
+const struct lpddr2_mr_regs mr_regs = {
+ .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
+ .mr2 = 0x6,
+ .mr3 = 0x1,
+ .mr10 = MR10_ZQ_ZQINIT,
+ .mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_device_details_sdp(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
{
- /* EMIF1 & EMIF2 have identical configuration */
- *cs0_device_details = dev_4G_S4_details;
- *cs1_device_details = dev_4G_S4_details;
-}
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ *regs = ext_phy_ctrl_const_base;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = ddr3_ext_phy_ctrl_const_base_es1;
+ break;
+ case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
+ default:
+ *regs = ddr3_ext_phy_ctrl_const_base_es2;
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
- __attribute__((weak, alias("emif_get_device_details_sdp")));
+ }
+}
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
+{
+ *regs = &mr_regs;
+}
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
+ const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -226,12 +353,13 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
* external phy 6-24 registers do not change with
* ddr frequency
*/
+ emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
+ writel(ext_phy_ctrl_const_regs[i],
+ emif_ext_phy_ctrl_base++);
/* Update shadow registers */
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
+ writel(ext_phy_ctrl_const_regs[i],
+ emif_ext_phy_ctrl_base++);
}
}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 141206e739..fa5fad1b0c 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15)
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
#endif
mcr p15, 0, r0, c1, c0, 0
+
+#ifdef CONFIG_ARM_ERRATA_742230
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 4 @ set bit #4
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 6 @ set bit #6
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_751472
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 11 @ set bit #11
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
mov pc, lr @ back to my caller
ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile
index 54ed8c48b4..c8a8504e16 100644
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/armv7/tegra20/Makefile
@@ -27,7 +27,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
COBJS-$(CONFIG_PWM_TEGRA) += pwm.o
COBJS-$(CONFIG_VIDEO_TEGRA) += display.o
diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c
deleted file mode 100644
index 1bccf2b0b2..0000000000
--- a/arch/arm/cpu/armv7/tegra20/usb.c
+++ /dev/null
@@ -1,567 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm-generic/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/usb.h>
-#include <usb/ulpi.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/sys_proto.h>
-#include <asm/arch-tegra/uart.h>
-#include <libfdt.h>
-#include <fdtdec.h>
-
-#ifdef CONFIG_USB_ULPI
- #ifndef CONFIG_USB_ULPI_VIEWPORT
- #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
- define CONFIG_USB_ULPI_VIEWPORT"
- #endif
-#endif
-
-enum {
- USB_PORTS_MAX = 4, /* Maximum ports we allow */
-};
-
-/* Parameters we need for USB */
-enum {
- PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
- PARAM_DIVM, /* PLL INPUT DIVIDER */
- PARAM_DIVP, /* POST DIVIDER (2^N) */
- PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
- PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
- PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
- PARAM_STABLE_COUNT, /* PLL-U STABLE count */
- PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
- PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
- PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
- PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
-
- PARAM_COUNT
-};
-
-/* Possible port types (dual role mode) */
-enum dr_mode {
- DR_MODE_NONE = 0,
- DR_MODE_HOST, /* supports host operation */
- DR_MODE_DEVICE, /* supports device operation */
- DR_MODE_OTG, /* supports both */
-};
-
-/* Information about a USB port */
-struct fdt_usb {
- struct usb_ctlr *reg; /* address of registers in physical memory */
- unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
- unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
- unsigned enabled:1; /* 1 to enable, 0 to disable */
- unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
- enum dr_mode dr_mode; /* dual role mode */
- enum periph_id periph_id;/* peripheral id */
- struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
- struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
-};
-
-static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
-static unsigned port_count; /* Number of available ports */
-
-/*
- * This table has USB timing parameters for each Oscillator frequency we
- * support. There are four sets of values:
- *
- * 1. PLLU configuration information (reference clock is osc/clk_m and
- * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
- *
- * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
- * ----------------------------------------------------------------------
- * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
- * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
- * Filter frequency (MHz) 1 4.8 6 2
- * CPCON 1100b 0011b 1100b 1100b
- * LFCON0 0 0 0 0
- *
- * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
- *
- * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
- * ---------------------------------------------------------------------------
- * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
- * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
- * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
- * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
- *
- * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
- * SessEnd. Each of these signals have their own debouncer and for each of
- * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
- * BIAS_DEBOUNCE_B).
- *
- * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
- * 0xffff -> No debouncing at all
- * <n> ms = <n> *1000 / (1/19.2MHz) / 4
- *
- * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
- * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
- *
- * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
- * values, so we can keep those to default.
- *
- * 4. The 20 microsecond delay after bias cell operation.
- */
-static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
- /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
- { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
- { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
- { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
- { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
-};
-
-/* UTMIP Idle Wait Delay */
-static const u8 utmip_idle_wait_delay = 17;
-
-/* UTMIP Elastic limit */
-static const u8 utmip_elastic_limit = 16;
-
-/* UTMIP High Speed Sync Start Delay */
-static const u8 utmip_hs_sync_start_delay = 9;
-
-/* Put the port into host mode */
-static void set_host_mode(struct fdt_usb *config)
-{
- /*
- * If we are an OTG port, check if remote host is driving VBus and
- * bail out in this case.
- */
- if (config->dr_mode == DR_MODE_OTG &&
- (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
- return;
-
- /*
- * If not driving, we set the GPIO to enable VBUS. We assume
- * that the pinmux is set up correctly for this.
- */
- if (fdt_gpio_isvalid(&config->vbus_gpio)) {
- fdtdec_setup_gpio(&config->vbus_gpio);
- gpio_direction_output(config->vbus_gpio.gpio,
- (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
- 0 : 1);
- debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
- (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
- "low" : "high");
- }
-}
-
-void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
-{
- /* Reset the USB controller with 2us delay */
- reset_periph(config->periph_id, 2);
-
- /*
- * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
- * base address
- */
- if (config->has_legacy_mode)
- setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
-
- /* Put UTMIP1/3 in reset */
- setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
-
- /* Enable the UTMIP PHY */
- if (config->utmi)
- setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
-
- /*
- * TODO: where do we take the USB1 out of reset? The old code would
- * take USB3 out of reset, but not USB1. This code doesn't do either.
- */
-}
-
-/* set up the UTMI USB controller with the parameters provided */
-static int init_utmi_usb_controller(struct fdt_usb *config,
- struct usb_ctlr *usbctlr, const u32 timing[])
-{
- u32 val;
- int loop_count;
-
- clock_enable(config->periph_id);
-
- /* Reset the usb controller */
- usbf_reset_controller(config, usbctlr);
-
- /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
- clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
-
- /* Follow the crystal clock disable by >100ns delay */
- udelay(1);
-
- /*
- * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
- * mux must be switched to actually use a_sess_vld threshold.
- */
- if (fdt_gpio_isvalid(&config->vbus_gpio)) {
- clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
- VBUS_SENSE_CTL_MASK,
- VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
- }
-
- /*
- * PLL Delay CONFIGURATION settings. The following parameters control
- * the bring up of the plls.
- */
- val = readl(&usbctlr->utmip_misc_cfg1);
- clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
- timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
- clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
- timing[PARAM_ACTIVE_DELAY_COUNT] <<
- UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
- writel(val, &usbctlr->utmip_misc_cfg1);
-
- /* Set PLL enable delay count and crystal frequency count */
- val = readl(&usbctlr->utmip_pll_cfg1);
- clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
- timing[PARAM_ENABLE_DELAY_COUNT] <<
- UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
- clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
- timing[PARAM_XTAL_FREQ_COUNT] <<
- UTMIP_XTAL_FREQ_COUNT_SHIFT);
- writel(val, &usbctlr->utmip_pll_cfg1);
-
- /* Setting the tracking length time */
- clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
- UTMIP_BIAS_PDTRK_COUNT_MASK,
- timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
-
- /* Program debounce time for VBUS to become valid */
- clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
- UTMIP_DEBOUNCE_CFG0_MASK,
- timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
-
- setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
-
- /* Disable battery charge enabling bit */
- setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
-
- clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
- setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
-
- /*
- * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
- * Setting these fields, together with default values of the
- * other fields, results in programming the registers below as
- * follows:
- * UTMIP_HSRX_CFG0 = 0x9168c000
- * UTMIP_HSRX_CFG1 = 0x13
- */
-
- /* Set PLL enable delay count and Crystal frequency count */
- val = readl(&usbctlr->utmip_hsrx_cfg0);
- clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
- utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
- clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
- utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
- writel(val, &usbctlr->utmip_hsrx_cfg0);
-
- /* Configure the UTMIP_HS_SYNC_START_DLY */
- clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
- UTMIP_HS_SYNC_START_DLY_MASK,
- utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
-
- /* Preceed the crystal clock disable by >100ns delay. */
- udelay(1);
-
- /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
- setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
-
- /* Finished the per-controller init. */
-
- /* De-assert UTMIP_RESET to bring out of reset. */
- clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
-
- /* Wait for the phy clock to become valid in 100 ms */
- for (loop_count = 100000; loop_count != 0; loop_count--) {
- if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
- break;
- udelay(1);
- }
- if (!loop_count)
- return -1;
-
- /* Disable ICUSB FS/LS transceiver */
- clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
-
- /* Select UTMI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS);
-
- /* Deassert power down state */
- clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
- UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
- clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
- UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
-
- return 0;
-}
-
-#ifdef CONFIG_USB_ULPI
-/* if board file does not set a ULPI reference frequency we default to 24MHz */
-#ifndef CONFIG_ULPI_REF_CLK
-#define CONFIG_ULPI_REF_CLK 24000000
-#endif
-
-/* set up the ULPI USB controller with the parameters provided */
-static int init_ulpi_usb_controller(struct fdt_usb *config,
- struct usb_ctlr *usbctlr)
-{
- u32 val;
- int loop_count;
- struct ulpi_viewport ulpi_vp;
-
- /* set up ULPI reference clock on pllp_out4 */
- clock_enable(PERIPH_ID_DEV2_OUT);
- clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
-
- /* reset ULPI phy */
- if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
- fdtdec_setup_gpio(&config->phy_reset_gpio);
- gpio_direction_output(config->phy_reset_gpio.gpio, 0);
- mdelay(5);
- gpio_set_value(config->phy_reset_gpio.gpio, 1);
- }
-
- /* Reset the usb controller */
- clock_enable(config->periph_id);
- usbf_reset_controller(config, usbctlr);
-
- /* enable pinmux bypass */
- setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
- ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
-
- /* Select ULPI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
-
- /* enable ULPI transceiver */
- setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
-
- /* configure ULPI transceiver timings */
- val = 0;
- writel(val, &usbctlr->ulpi_timing_ctrl_1);
-
- val |= ULPI_DATA_TRIMMER_SEL(4);
- val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
- val |= ULPI_DIR_TRIMMER_SEL(4);
- writel(val, &usbctlr->ulpi_timing_ctrl_1);
- udelay(10);
-
- val |= ULPI_DATA_TRIMMER_LOAD;
- val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
- val |= ULPI_DIR_TRIMMER_LOAD;
- writel(val, &usbctlr->ulpi_timing_ctrl_1);
-
- /* set up phy for host operation with external vbus supply */
- ulpi_vp.port_num = 0;
- ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
-
- if (ulpi_init(&ulpi_vp)) {
- printf("Tegra ULPI viewport init failed\n");
- return -1;
- }
-
- ulpi_set_vbus(&ulpi_vp, 1, 1);
- ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
-
- /* enable wakeup events */
- setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
-
- /* Enable and wait for the phy clock to become valid in 100 ms */
- setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
- for (loop_count = 100000; loop_count != 0; loop_count--) {
- if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
- break;
- udelay(1);
- }
- if (!loop_count)
- return -1;
- clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
-
- return 0;
-}
-#else
-static int init_ulpi_usb_controller(struct fdt_usb *config,
- struct usb_ctlr *usbctlr)
-{
- printf("No code to set up ULPI controller, please enable"
- "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
- return -1;
-}
-#endif
-
-static void config_clock(const u32 timing[])
-{
- clock_start_pll(CLOCK_ID_USB,
- timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
- timing[PARAM_CPCON], timing[PARAM_LFCON]);
-}
-
-/**
- * Add a new USB port to the list of available ports.
- *
- * @param config USB port configuration
- * @return 0 if ok, -1 if error (too many ports)
- */
-static int add_port(struct fdt_usb *config, const u32 timing[])
-{
- struct usb_ctlr *usbctlr = config->reg;
-
- if (port_count == USB_PORTS_MAX) {
- printf("tegrausb: Cannot register more than %d ports\n",
- USB_PORTS_MAX);
- return -1;
- }
-
- if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
- printf("tegrausb: Cannot init port\n");
- return -1;
- }
-
- if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
- printf("tegrausb: Cannot init port\n");
- return -1;
- }
-
- port[port_count++] = *config;
-
- return 0;
-}
-
-int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
-{
- struct usb_ctlr *usbctlr;
-
- if (portnum >= port_count)
- return -1;
- set_host_mode(&port[portnum]);
-
- usbctlr = port[portnum].reg;
- *hccr = (u32)&usbctlr->cap_length;
- *hcor = (u32)&usbctlr->usb_cmd;
- return 0;
-}
-
-int tegrausb_stop_port(int portnum)
-{
- struct usb_ctlr *usbctlr;
-
- usbctlr = port[portnum].reg;
-
- /* Stop controller */
- writel(0, &usbctlr->usb_cmd);
- udelay(1000);
-
- /* Initiate controller reset */
- writel(2, &usbctlr->usb_cmd);
- udelay(1000);
-
- return 0;
-}
-
-int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
- struct fdt_usb *config)
-{
- const char *phy, *mode;
-
- config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode) {
- if (0 == strcmp(mode, "host"))
- config->dr_mode = DR_MODE_HOST;
- else if (0 == strcmp(mode, "peripheral"))
- config->dr_mode = DR_MODE_DEVICE;
- else if (0 == strcmp(mode, "otg"))
- config->dr_mode = DR_MODE_OTG;
- else {
- debug("%s: Cannot decode dr_mode '%s'\n", __func__,
- mode);
- return -FDT_ERR_NOTFOUND;
- }
- } else {
- config->dr_mode = DR_MODE_HOST;
- }
-
- phy = fdt_getprop(blob, node, "phy_type", NULL);
- config->utmi = phy && 0 == strcmp("utmi", phy);
- config->ulpi = phy && 0 == strcmp("ulpi", phy);
- config->enabled = fdtdec_get_is_enabled(blob, node);
- config->has_legacy_mode = fdtdec_get_bool(blob, node,
- "nvidia,has-legacy-mode");
- config->periph_id = clock_decode_periph_id(blob, node);
- if (config->periph_id == PERIPH_ID_NONE) {
- debug("%s: Missing/invalid peripheral ID\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
- fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
- fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
- &config->phy_reset_gpio);
- debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
- "vbus=%d, phy_reset=%d, dr_mode=%d\n",
- config->enabled, config->has_legacy_mode, config->utmi,
- config->ulpi, config->periph_id, config->vbus_gpio.gpio,
- config->phy_reset_gpio.gpio, config->dr_mode);
-
- return 0;
-}
-
-int board_usb_init(const void *blob)
-{
- struct fdt_usb config;
- unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
- enum clock_osc_freq freq;
- int node_list[USB_PORTS_MAX];
- int node, count, i;
-
- /* Set up the USB clocks correctly based on our oscillator frequency */
- freq = clock_get_osc_freq();
- config_clock(usb_pll[freq]);
-
- /* count may return <0 on error */
- count = fdtdec_find_aliases_for_id(blob, "usb",
- COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
- for (i = 0; i < count; i++) {
- debug("USB %d: ", i);
- node = node_list[i];
- if (!node)
- continue;
- if (fdt_decode_usb(blob, node, osc_freq, &config)) {
- debug("Cannot decode USB node %s\n",
- fdt_get_name(blob, node, NULL));
- return -1;
- }
-
- if (add_port(&config, usb_pll[freq]))
- return -1;
- set_host_mode(&config);
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index 499ace4a62..388085dc2a 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-y := timer.o
COBJS-y += cpu.o
+COBJS-y += slcr.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index ab615cc7d4..e8f4c19d49 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,11 +21,37 @@
* MA 02111-1307 USA
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
-inline void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+ zynq_slcr_unlock();
+ /* remap DDR to zero, FILTERSTART */
+ writel(0, &scu_base->filter_start);
+
+ /* Device config APB, unlock the PCAP */
+ writel(0x757BDF0D, &devcfg_base->unlock);
+ writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+ /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+ writel(0x1F, &slcr_base->ocm_cfg);
+ /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+ /* TZ_DDR_RAM, Set DDR trust zone non-secure */
+ writel(0xFFFFFFFF, &slcr_base->trust_zone);
+ /* Set urgent bits with register */
+ writel(0x0, &slcr_base->ddr_urgent_sel);
+ /* Urgent write, ports S2/S3 */
+ writel(0xC, &slcr_base->ddr_urgent);
+
+ zynq_slcr_lock();
+}
void reset_cpu(ulong addr)
{
+ zynq_slcr_cpu_reset();
while (1)
;
}
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
new file mode 100644
index 0000000000..788a8fd14f
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+
+#define SLCR_LOCK_MAGIC 0x767B
+#define SLCR_UNLOCK_MAGIC 0xDF0D
+
+static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
+
+void zynq_slcr_lock(void)
+{
+ if (!slcr_lock)
+ writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+}
+
+void zynq_slcr_unlock(void)
+{
+ if (slcr_lock)
+ writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+}
+
+/* Reset the entire system */
+void zynq_slcr_cpu_reset(void)
+{
+ /*
+ * Unlock the SLCR then reset the system.
+ * Note that this seems to require raw i/o
+ * functions or there's a lockup?
+ */
+ zynq_slcr_unlock();
+
+ /*
+ * Clear 0x0F000000 bits of reboot status register to workaround
+ * the FSBL not loading the bitstream after soft-reboot
+ * This is a temporary solution until we know more.
+ */
+ clrbits_le32(&slcr_base->reboot_status, 0xF000000);
+
+ writel(1, &slcr_base->pss_rst_ctrl);
+}
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 2c823e1065..8345b55032 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -49,7 +49,7 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
@@ -67,11 +67,17 @@ SECTIONS
_end = .;
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- __bss_end = .;
+ __bss_end = .;
+ }
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
index 52b3ec47aa..4983a05090 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -37,6 +37,20 @@ struct tegra_pingroup_desc {
#define PMUX_OD_SHIFT 6
#define PMUX_LOCK_SHIFT 7
#define PMUX_IO_RESET_SHIFT 8
+#define PMUX_RCV_SEL_SHIFT 9
+
+#define PGRP_HSM_SHIFT 2
+#define PGRP_SCHMT_SHIFT 3
+#define PGRP_LPMD_SHIFT 4
+#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT 12
+#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT 20
+#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT 28
+#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT 30
+#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
@@ -58,6 +72,10 @@ struct tegra_pingroup_desc {
#define PINO(pg_name, vdd, f0, f1, f2, f3) \
PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+ PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
@@ -84,71 +102,71 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
- PINI(GPIO_PV2, BB, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(GPIO_PV3, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
+ PIN_RESERVED,
PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
- PINO(LCD_PWR1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_PWR2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_SDIN, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_SDOUT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_WR_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_CS0_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_DC0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_SCK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_PWR0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_PCLK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_DE, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D3, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D4, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D5, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D6, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D7, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D8, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D9, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D10, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D11, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D12, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D13, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D14, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D15, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D16, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D17, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D18, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D19, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D20, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D21, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D22, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_D23, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_CS1_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_M1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINO(LCD_DC1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
- PINI(CRT_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(CRT_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D0, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D1, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D2, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D3, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D4, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D5, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D6, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D7, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D8, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D9, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D10, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_D11, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_PCLK, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_MCLK, VI, RSVD1, RSVD3, RSVD3, RSVD4),
- PINI(VI_VSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(VI_HSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
@@ -220,8 +238,8 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
- PINI(SDMMC4_RST_N, SDMMC4, RSVD1, RSVD2, RSVD3, SDMMC4),
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x3280 */
+ PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
@@ -246,11 +264,11 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
- PINI(KB_ROW11, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW12, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW13, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW14, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(KB_ROW15, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
@@ -278,36 +296,46 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
- PINI(SPI2_MOSI, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(SPI2_MISO, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
- PINI(SPI2_CS0_N, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
- PINI(SPI2_SCK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
- PINI(SPI1_MOSI, AUDIO, RSVD1, SPI1, SPI2, DAP2),
- PINI(SPI1_SCK, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PINI(SPI1_CS0_N, AUDIO, SPI6, SPI1, SPI2, RSVD4),
- PINI(SPI1_MISO, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
- PINI(SPI2_CS1_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SPI2_CS2_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
+ PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
+ PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
+ PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
+ PIN_RESERVED,
PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
- PINI(SDMMC3_DAT4, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_DAT5, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_DAT6, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
- PINI(SDMMC3_DAT7, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
- PINI(SDMMC3_CD_N, SDMMC3, SDMMC3, OWR, RSVD3, RSVD4),
- PINI(SPI1_CS1_N, AUDIO, SPI6, RSVD2, SPI2, I2C1),
- PINI(SPI1_CS2_N, AUDIO, SPI6, SPI1, SPI2, I2C1),
- PINI(USB_VBUS_EN0, SYS, USB, RSVD2, RSVD3, RSVD4),
- PINI(USB_VBUS_EN1, SYS, USB, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
+ PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
+ PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
+ PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
+ PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PINO(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
- PINO(NAND_GMI_CLK_LB, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved by t114: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
@@ -484,6 +512,30 @@ static int pinmux_set_ioreset(enum pmux_pingrp pin,
return 0;
}
+static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
+ enum pmux_pin_rcv_sel rcv_sel)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and rcv_sel */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+ if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+ return 0;
+
+ reg = readl(pin_rcv_sel);
+ reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
+ if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+ reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
+ writel(reg, pin_rcv_sel);
+
+ return 0;
+}
+
void pinmux_config_pingroup(struct pingroup_config *config)
{
enum pmux_pingrp pin = config->pingroup;
@@ -495,6 +547,7 @@ void pinmux_config_pingroup(struct pingroup_config *config)
pinmux_set_lock(pin, config->lock);
pinmux_set_od(pin, config->od);
pinmux_set_ioreset(pin, config->ioreset);
+ pinmux_set_rcv_sel(pin, config->rcv_sel);
}
void pinmux_config_table(struct pingroup_config *config, int len)
@@ -504,3 +557,184 @@ void pinmux_config_table(struct pingroup_config *config, int len)
for (i = 0; i < len; i++)
pinmux_config_pingroup(&config[i]);
}
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwf = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwf */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwf));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwf == PGRP_SLWF_NONE)
+ return 0;
+
+ reg = readl(pad_slwf);
+ reg &= ~PGRP_SLWF_MASK;
+ reg |= (slwf << PGRP_SLWF_SHIFT);
+ writel(reg, pad_slwf);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwr = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwr */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwr));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwr == PGRP_SLWR_NONE)
+ return 0;
+
+ reg = readl(pad_slwr);
+ reg &= ~PGRP_SLWR_MASK;
+ reg |= (slwr << PGRP_SLWR_SHIFT);
+ writel(reg, pad_slwr);
+
+ return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvup = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvup */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvup));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvup == PGRP_DRVUP_NONE)
+ return 0;
+
+ reg = readl(pad_drvup);
+ reg &= ~PGRP_DRVUP_MASK;
+ reg |= (drvup << PGRP_DRVUP_SHIFT);
+ writel(reg, pad_drvup);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvdn = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvdn */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvdn));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvdn == PGRP_DRVDN_NONE)
+ return 0;
+
+ reg = readl(pad_drvdn);
+ reg &= ~PGRP_DRVDN_MASK;
+ reg |= (drvdn << PGRP_DRVDN_SHIFT);
+ writel(reg, pad_drvdn);
+
+ return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_lpmd = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad and lpmd value */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_lpmd_isvalid(lpmd));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (lpmd == PGRP_LPMD_NONE)
+ return 0;
+
+ reg = readl(pad_lpmd);
+ reg &= ~PGRP_LPMD_MASK;
+ reg |= (lpmd << PGRP_LPMD_SHIFT);
+ writel(reg, pad_lpmd);
+
+ return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_schmt = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (schmt == PGRP_SCHMT_NONE)
+ return 0;
+
+ reg = readl(pad_schmt);
+ reg &= ~(1 << PGRP_SCHMT_SHIFT);
+ if (schmt == PGRP_SCHMT_ENABLE)
+ reg |= (0x1 << PGRP_SCHMT_SHIFT);
+ writel(reg, pad_schmt);
+
+ return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_hsm = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (hsm == PGRP_HSM_NONE)
+ return 0;
+
+ reg = readl(pad_hsm);
+ reg &= ~(1 << PGRP_HSM_SHIFT);
+ if (hsm == PGRP_HSM_ENABLE)
+ reg |= (0x1 << PGRP_HSM_SHIFT);
+ writel(reg, pad_hsm);
+
+ return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+ enum pdrive_pingrp pad = config->padgrp;
+
+ padgrp_set_drvup_slwf(pad, config->slwf);
+ padgrp_set_drvdn_slwr(pad, config->slwr);
+ padgrp_set_drvup(pad, config->drvup);
+ padgrp_set_drvdn(pad, config->drvdn);
+ padgrp_set_lpmd(pad, config->lpmd);
+ padgrp_set_schmt(pad, config->schmt);
+ padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ padctrl_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index 122665fd3c..eecf0580bc 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -38,6 +38,19 @@ struct tegra_pingroup_desc {
#define PMUX_LOCK_SHIFT 7
#define PMUX_IO_RESET_SHIFT 8
+#define PGRP_HSM_SHIFT 2
+#define PGRP_SCHMT_SHIFT 3
+#define PGRP_LPMD_SHIFT 4
+#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT 12
+#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT 20
+#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT 28
+#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT 30
+#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
+
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
@@ -504,3 +517,178 @@ void pinmux_config_table(struct pingroup_config *config, int len)
for (i = 0; i < len; i++)
pinmux_config_pingroup(&config[i]);
}
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
+ int slwf)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwf = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwf */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwf));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwf == PGRP_SLWF_NONE)
+ return 0;
+
+ reg = readl(pad_slwf);
+ reg &= ~PGRP_SLWF_MASK;
+ reg |= (slwf << PGRP_SLWF_SHIFT);
+ writel(reg, pad_slwf);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwr = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwr */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwr));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwr == PGRP_SLWR_NONE)
+ return 0;
+
+ reg = readl(pad_slwr);
+ reg &= ~PGRP_SLWR_MASK;
+ reg |= (slwr << PGRP_SLWR_SHIFT);
+ writel(reg, pad_slwr);
+
+ return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvup = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvup */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvup));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvup == PGRP_DRVUP_NONE)
+ return 0;
+
+ reg = readl(pad_drvup);
+ reg &= ~PGRP_DRVUP_MASK;
+ reg |= (drvup << PGRP_DRVUP_SHIFT);
+ writel(reg, pad_drvup);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvdn = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvdn */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvdn));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvdn == PGRP_DRVDN_NONE)
+ return 0;
+
+ reg = readl(pad_drvdn);
+ reg &= ~PGRP_DRVDN_MASK;
+ reg |= (drvdn << PGRP_DRVDN_SHIFT);
+ writel(reg, pad_drvdn);
+
+ return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_lpmd = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad and lpmd value */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_lpmd_isvalid(lpmd));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (lpmd == PGRP_LPMD_NONE)
+ return 0;
+
+ reg = readl(pad_lpmd);
+ reg &= ~PGRP_LPMD_MASK;
+ reg |= (lpmd << PGRP_LPMD_SHIFT);
+ writel(reg, pad_lpmd);
+
+ return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_schmt = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ reg = readl(pad_schmt);
+ reg &= ~(1 << PGRP_SCHMT_SHIFT);
+ if (schmt == PGRP_SCHMT_ENABLE)
+ reg |= (0x1 << PGRP_SCHMT_SHIFT);
+ writel(reg, pad_schmt);
+
+ return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad,
+ enum pgrp_hsm hsm)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_hsm = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ reg = readl(pad_hsm);
+ reg &= ~(1 << PGRP_HSM_SHIFT);
+ if (hsm == PGRP_HSM_ENABLE)
+ reg |= (0x1 << PGRP_HSM_SHIFT);
+ writel(reg, pad_hsm);
+
+ return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+ enum pdrive_pingrp pad = config->padgrp;
+
+ padgrp_set_drvup_slwf(pad, config->slwf);
+ padgrp_set_drvdn_slwr(pad, config->slwr);
+ padgrp_set_drvup(pad, config->drvup);
+ padgrp_set_drvdn(pad, config->drvdn);
+ padgrp_set_lpmd(pad, config->lpmd);
+ padgrp_set_schmt(pad, config->schmt);
+ padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ padctrl_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
new file mode 100644
index 0000000000..3c0d99ca36
--- /dev/null
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
+
+#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
+ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
+#endif
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index b337e7bf51..3a1083d9a9 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -52,7 +52,7 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
@@ -81,11 +81,18 @@ SECTIONS
*(.mmutable)
}
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- __bss_end = .;
+ __bss_end = .;
+ }
+
+ .bss_end __bss_end (OVERLAY) : {
+ KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index d06cd126dd..701c0f9aff 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -1,5 +1,78 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra114";
+
+ tegra_car: clock {
+ compatible = "nvidia,tegra114-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gpio: gpio {
+ compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04
+ 0 125 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <0 38 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 12>;
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <0 84 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 54>;
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <0 92 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 67>;
+ status = "disabled";
+ };
+
+ i2c@7000c700 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000c700 0x100>;
+ interrupts = <0 120 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 103>;
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra114-i2c";
+ reg = <0x7000d000 0x100>;
+ interrupts = <0 53 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 47>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 9a8968522e..3805750581 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra20";
@@ -318,24 +318,32 @@
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
- interrupts = < 46 >;
+ interrupts = <0 14 0x04>;
+ clocks = <&tegra_car 14>;
+ status = "disabled";
};
sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
- interrupts = < 47 >;
+ interrupts = <0 15 0x04>;
+ clocks = <&tegra_car 9>;
+ status = "disabled";
};
sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
- interrupts = < 51 >;
+ interrupts = <0 19 0x04>;
+ clocks = <&tegra_car 69>;
+ status = "disabled";
};
sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
- interrupts = < 63 >;
+ interrupts = <0 31 0x04>;
+ clocks = <&tegra_car 15>;
+ status = "disabled";
};
};
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 7b8126f7cc..ccf154f1e7 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -1,10 +1,10 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
- tegra_car: clock@60006000 {
- compatible = "nvidia,tegra30-car", "nvidia,tegra20-car";
+ tegra_car: clock {
+ compatible = "nvidia,tegra30-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
};
@@ -44,51 +44,79 @@
0 141 0x04
0 142 0x04
0 143 0x04>;
+ clocks = <&tegra_car 34>;
+ };
+
+ gpio: gpio {
+ compatible = "nvidia,tegra30-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04
+ 0 125 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
};
i2c@7000c000 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000C000 0x100>;
- /* PERIPH_ID_I2C1, CLK_M */
- clocks = <&tegra_car 12>;
+ clocks = <&tegra_car 12>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
};
i2c@7000c400 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000C400 0x100>;
- /* PERIPH_ID_I2C2, CLK_M */
- clocks = <&tegra_car 54>;
+ clocks = <&tegra_car 54>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
};
i2c@7000c500 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000C500 0x100>;
- /* PERIPH_ID_I2C3, CLK_M */
- clocks = <&tegra_car 67>;
+ clocks = <&tegra_car 67>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
};
i2c@7000c700 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000c700 0x100>;
+ interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000C700 0x100>;
- /* PERIPH_ID_I2C4, CLK_M */
- clocks = <&tegra_car 103>;
+ clocks = <&tegra_car 103>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
};
i2c@7000d000 {
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000d000 0x100>;
+ interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
- reg = <0x7000D000 0x100>;
- /* PERIPH_ID_I2C_DVC, CLK_M */
- clocks = <&tegra_car 47>;
+ clocks = <&tegra_car 47>, <&tegra_car 182>;
+ clock-names = "div-clk", "fast-clk";
+ status = "disabled";
};
spi@7000d400 {
@@ -98,9 +126,8 @@
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
- /* PERIPH_ID_SBC1, PLLP_OUT0 */
clocks = <&tegra_car 41>;
+ status = "disabled";
};
spi@7000d600 {
@@ -110,9 +137,8 @@
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
- /* PERIPH_ID_SBC2, PLLP_OUT0 */
clocks = <&tegra_car 44>;
+ status = "disabled";
};
spi@7000d800 {
@@ -122,9 +148,8 @@
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
- /* PERIPH_ID_SBC3, PLLP_OUT0 */
clocks = <&tegra_car 46>;
+ status = "disabled";
};
spi@7000da00 {
@@ -134,9 +159,8 @@
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
- /* PERIPH_ID_SBC4, PLLP_OUT0 */
clocks = <&tegra_car 68>;
+ status = "disabled";
};
spi@7000dc00 {
@@ -146,9 +170,8 @@
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
- /* PERIPH_ID_SBC5, PLLP_OUT0 */
clocks = <&tegra_car 104>;
+ status = "disabled";
};
spi@7000de00 {
@@ -158,8 +181,39 @@
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
- /* PERIPH_ID_SBC6, PLLP_OUT0 */
clocks = <&tegra_car 105>;
+ status = "disabled";
+ };
+
+ sdhci@78000000 {
+ compatible = "nvidia,tegra30-sdhci";
+ reg = <0x78000000 0x200>;
+ interrupts = <0 14 0x04>;
+ clocks = <&tegra_car 14>;
+ status = "disabled";
+ };
+
+ sdhci@78000200 {
+ compatible = "nvidia,tegra30-sdhci";
+ reg = <0x78000200 0x200>;
+ interrupts = <0 15 0x04>;
+ clocks = <&tegra_car 9>;
+ status = "disabled";
+ };
+
+ sdhci@78000400 {
+ compatible = "nvidia,tegra30-sdhci";
+ reg = <0x78000400 0x200>;
+ interrupts = <0 19 0x04>;
+ clocks = <&tegra_car 69>;
+ status = "disabled";
+ };
+
+ sdhci@78000600 {
+ compatible = "nvidia,tegra30-sdhci";
+ reg = <0x78000600 0x200>;
+ interrupts = <0 31 0x04>;
+ clocks = <&tegra_car 15>;
+ status = "disabled";
};
};
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 1f597c0eec..33c9c83892 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -16,148 +16,12 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x48060100
#define OMAP_HSMMC2_BASE 0x481D8100
-typedef struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-} hsmmc_t;
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 644ff353fe..e961ce0578 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -29,6 +29,7 @@
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
+#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 588d8de82f..97ab60d1b2 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -35,5 +35,7 @@ void ddr_pll_config(unsigned int ddrpll_M);
void sdelay(unsigned long);
void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size);
void omap_nand_switch_ecc(int);
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h
index de0f1b1923..b7d1932f42 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h
@@ -140,12 +140,6 @@
/*
* Cpu Name
*/
-#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15"
-#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25"
-#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35"
-#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25"
-#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35"
-#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type"
#define ATMEL_CPU_NAME get_cpu_name()
/*
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/include/asm/arch-davinci/gpio.h
index 5206b12211..06390c85e1 100644
--- a/arch/arm/include/asm/arch-davinci/gpio.h
+++ b/arch/arm/include/asm/arch-davinci/gpio.h
@@ -65,15 +65,16 @@ struct davinci_gpio_bank {
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
+#define gpio_status() gpio_info()
+#define GPIO_NAME_SIZE 20
#if defined(CONFIG_SOC_DM644X)
/* GPIO0 to GPIO53, omit the V3.3 volts one */
#define MAX_NUM_GPIOS 70
+#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#define MAX_NUM_GPIOS 128
#else
#define MAX_NUM_GPIOS 144
#endif
-
-#define gpio_status() gpio_info()
-#define GPIO_NAME_SIZE 20
#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
#define GPIO_BIT(gp) ((gp) & 0x1F)
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
index 91d11ae847..3ca4c94680 100644
--- a/arch/arm/include/asm/arch-mx35/spl.h
+++ b/arch/arm/include/asm/arch-mx35/spl.h
@@ -27,7 +27,7 @@
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index d670f30c02..76764571a7 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,6 +20,17 @@
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define CCM_CCGR0 0x020C4068
+#define CCM_CCGR1 0x020C406c
+#define CCM_CCGR2 0x020C4070
+#define CCM_CCGR3 0x020C4074
+#define CCM_CCGR4 0x020C4078
+#define CCM_CCGR5 0x020C407c
+#define CCM_CCGR6 0x020C4080
+
+#define PMU_MISC2 0x020C8170
+
+#ifndef __ASSEMBLY__
struct mxc_ccm_reg {
u32 ccr; /* 0x0000 */
u32 ccdr;
@@ -105,6 +116,7 @@ struct mxc_ccm_reg {
u32 analog_pfd_528_clr;
u32 analog_pfd_528_tog;
};
+#endif
/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN (1 << 27)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3eb0081ca8..eaa7439486 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -601,5 +601,13 @@ struct iomuxc_base_regs {
u32 daisy[104]; /* 0x7b0..94c */
};
+struct wdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Miscellaneous Control */
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index d23abd764a..d67f600068 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -16,6 +16,11 @@
#ifndef __ASM_ARCH_IOMUX_H__
#define __ASM_ARCH_IOMUX_H__
+
+#define MX6_IOMUXC_GPR4 0x020e0010
+#define MX6_IOMUXC_GPR6 0x020e0018
+#define MX6_IOMUXC_GPR7 0x020e001c
+
/*
* IOMUXC_GPR13 bit fields
*/
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
new file mode 100644
index 0000000000..1fdc1d48b3
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6_DDR_H__
+#define __ASM_ARCH_MX6_DDR_H__
+
+#ifdef CONFIG_MX6Q
+#include "mx6q-ddr.h"
+#else
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#include "mx6dl-ddr.h"
+#else
+#error "Please select cpu"
+#endif /* CONFIG_MX6DL or CONFIG_MX6S */
+#endif /* CONFIG_MX6Q */
+
+#define MX6_MMDC_P0_MDCTL 0x021b0000
+#define MX6_MMDC_P0_MDPDC 0x021b0004
+#define MX6_MMDC_P0_MDOTC 0x021b0008
+#define MX6_MMDC_P0_MDCFG0 0x021b000c
+#define MX6_MMDC_P0_MDCFG1 0x021b0010
+#define MX6_MMDC_P0_MDCFG2 0x021b0014
+#define MX6_MMDC_P0_MDMISC 0x021b0018
+#define MX6_MMDC_P0_MDSCR 0x021b001c
+#define MX6_MMDC_P0_MDREF 0x021b0020
+#define MX6_MMDC_P0_MDRWD 0x021b002c
+#define MX6_MMDC_P0_MDOR 0x021b0030
+#define MX6_MMDC_P0_MDASP 0x021b0040
+#define MX6_MMDC_P0_MAPSR 0x021b0404
+#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
+#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
+#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
+#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
+#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
+#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
+#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
+#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
+#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
+#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
+#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
+#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
+#define MX6_MMDC_P0_MPMUR0 0x021b08b8
+
+#define MX6_MMDC_P1_MDCTL 0x021b4000
+#define MX6_MMDC_P1_MDPDC 0x021b4004
+#define MX6_MMDC_P1_MDOTC 0x021b4008
+#define MX6_MMDC_P1_MDCFG0 0x021b400c
+#define MX6_MMDC_P1_MDCFG1 0x021b4010
+#define MX6_MMDC_P1_MDCFG2 0x021b4014
+#define MX6_MMDC_P1_MDMISC 0x021b4018
+#define MX6_MMDC_P1_MDSCR 0x021b401c
+#define MX6_MMDC_P1_MDREF 0x021b4020
+#define MX6_MMDC_P1_MDRWD 0x021b402c
+#define MX6_MMDC_P1_MDOR 0x021b4030
+#define MX6_MMDC_P1_MDASP 0x021b4040
+#define MX6_MMDC_P1_MAPSR 0x021b4404
+#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
+#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
+#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
+#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
+#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
+#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
+#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
+#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
+#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
+#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
+#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
+#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
+#define MX6_MMDC_P1_MPMUR0 0x021b48b8
+
+#endif /*__ASM_ARCH_MX6_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
new file mode 100644
index 0000000000..63f485666a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6_PINS_H__
+#define __ASM_ARCH_MX6_PINS_H__
+
+#ifdef CONFIG_MX6Q
+#include "mx6q_pins.h"
+#else
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#include "mx6dl_pins.h"
+#else
+#error "Please select cpu"
+#endif /* CONFIG_MX6DL or CONFIG_MX6S */
+#endif /* CONFIG_MX6Q */
+
+#endif /*__ASM_ARCH_MX6_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
new file mode 100644
index 0000000000..325da3314a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6DLS_DDR_H__
+#define __ASM_ARCH_MX6DLS_DDR_H__
+
+#ifndef CONFIG_MX6DL
+#ifndef CONFIG_MX6S
+#error "wrong CPU"
+#endif
+#endif
+
+#define MX6_IOM_DRAM_DQM0 0x020e0470
+#define MX6_IOM_DRAM_DQM1 0x020e0474
+#define MX6_IOM_DRAM_DQM2 0x020e0478
+#define MX6_IOM_DRAM_DQM3 0x020e047c
+#define MX6_IOM_DRAM_DQM4 0x020e0480
+#define MX6_IOM_DRAM_DQM5 0x020e0484
+#define MX6_IOM_DRAM_DQM6 0x020e0488
+#define MX6_IOM_DRAM_DQM7 0x020e048c
+
+#define MX6_IOM_DRAM_CAS 0x020e0464
+#define MX6_IOM_DRAM_RAS 0x020e0490
+#define MX6_IOM_DRAM_RESET 0x020e0494
+#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
+#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
+#define MX6_IOM_DRAM_SDBA2 0x020e04a0
+#define MX6_IOM_DRAM_SDCKE0 0x020e04a4
+#define MX6_IOM_DRAM_SDCKE1 0x020e04a8
+#define MX6_IOM_DRAM_SDODT0 0x020e04b4
+#define MX6_IOM_DRAM_SDODT1 0x020e04b8
+
+#define MX6_IOM_DRAM_SDQS0 0x020e04bc
+#define MX6_IOM_DRAM_SDQS1 0x020e04c0
+#define MX6_IOM_DRAM_SDQS2 0x020e04c4
+#define MX6_IOM_DRAM_SDQS3 0x020e04c8
+#define MX6_IOM_DRAM_SDQS4 0x020e04cc
+#define MX6_IOM_DRAM_SDQS5 0x020e04d0
+#define MX6_IOM_DRAM_SDQS6 0x020e04d4
+#define MX6_IOM_DRAM_SDQS7 0x020e04d8
+
+#define MX6_IOM_GRP_B0DS 0x020e0764
+#define MX6_IOM_GRP_B1DS 0x020e0770
+#define MX6_IOM_GRP_B2DS 0x020e0778
+#define MX6_IOM_GRP_B3DS 0x020e077c
+#define MX6_IOM_GRP_B4DS 0x020e0780
+#define MX6_IOM_GRP_B5DS 0x020e0784
+#define MX6_IOM_GRP_B6DS 0x020e078c
+#define MX6_IOM_GRP_B7DS 0x020e0748
+#define MX6_IOM_GRP_ADDDS 0x020e074c
+#define MX6_IOM_DDRMODE_CTL 0x020e0750
+#define MX6_IOM_GRP_DDRPKE 0x020e0754
+#define MX6_IOM_GRP_DDRMODE 0x020e0760
+#define MX6_IOM_GRP_CTLDS 0x020e076c
+#define MX6_IOM_GRP_DDR_TYPE 0x020e0774
+
+#endif /*__ASM_ARCH_MX6S_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 79e2c4f5a4..9494e4126a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -50,100 +50,103 @@
#define NO_MUX_I 0
#define NO_PAD_I 0
enum {
- MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
- MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
- MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
- MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
- MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
- MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
- MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
- MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
- MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
- MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
- MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
- MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
- MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
- MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
- MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
- MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
- MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
- MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
- MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
- MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
- MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
- MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
- MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
- MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
- MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
- MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
- MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
- MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
- MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
- MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
- MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+ MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+ MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+ MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+ MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+ MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+ MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+ MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
+ MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
+ MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+ MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
+ MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
+ MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
+ MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
+ MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+ MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+ MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
new file mode 100644
index 0000000000..e51727c389
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MX6Q_DDR_H__
+#define __ASM_ARCH_MX6Q_DDR_H__
+
+#ifndef CONFIG_MX6Q
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0 0x020e05ac
+#define MX6_IOM_DRAM_DQM1 0x020e05b4
+#define MX6_IOM_DRAM_DQM2 0x020e0528
+#define MX6_IOM_DRAM_DQM3 0x020e0520
+#define MX6_IOM_DRAM_DQM4 0x020e0514
+#define MX6_IOM_DRAM_DQM5 0x020e0510
+#define MX6_IOM_DRAM_DQM6 0x020e05bc
+#define MX6_IOM_DRAM_DQM7 0x020e05c4
+
+#define MX6_IOM_DRAM_CAS 0x020e056c
+#define MX6_IOM_DRAM_RAS 0x020e0578
+#define MX6_IOM_DRAM_RESET 0x020e057c
+#define MX6_IOM_DRAM_SDCLK_0 0x020e0588
+#define MX6_IOM_DRAM_SDCLK_1 0x020e0594
+#define MX6_IOM_DRAM_SDBA2 0x020e058c
+#define MX6_IOM_DRAM_SDCKE0 0x020e0590
+#define MX6_IOM_DRAM_SDCKE1 0x020e0598
+#define MX6_IOM_DRAM_SDODT0 0x020e059c
+#define MX6_IOM_DRAM_SDODT1 0x020e05a0
+
+#define MX6_IOM_DRAM_SDQS0 0x020e05a8
+#define MX6_IOM_DRAM_SDQS1 0x020e05b0
+#define MX6_IOM_DRAM_SDQS2 0x020e0524
+#define MX6_IOM_DRAM_SDQS3 0x020e051c
+#define MX6_IOM_DRAM_SDQS4 0x020e0518
+#define MX6_IOM_DRAM_SDQS5 0x020e050c
+#define MX6_IOM_DRAM_SDQS6 0x020e05b8
+#define MX6_IOM_DRAM_SDQS7 0x020e05c0
+
+#define MX6_IOM_GRP_B0DS 0x020e0784
+#define MX6_IOM_GRP_B1DS 0x020e0788
+#define MX6_IOM_GRP_B2DS 0x020e0794
+#define MX6_IOM_GRP_B3DS 0x020e079c
+#define MX6_IOM_GRP_B4DS 0x020e07a0
+#define MX6_IOM_GRP_B5DS 0x020e07a4
+#define MX6_IOM_GRP_B6DS 0x020e07a8
+#define MX6_IOM_GRP_B7DS 0x020e0748
+#define MX6_IOM_GRP_ADDDS 0x020e074c
+#define MX6_IOM_DDRMODE_CTL 0x020e0750
+#define MX6_IOM_GRP_DDRPKE 0x020e0758
+#define MX6_IOM_GRP_DDRMODE 0x020e0774
+#define MX6_IOM_GRP_CTLDS 0x020e078c
+#define MX6_IOM_GRP_DDR_TYPE 0x020e0798
+
+#endif /*__ASM_ARCH_MX6Q_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
new file mode 100644
index 0000000000..1c1c00855f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -0,0 +1,1671 @@
+/*
+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__
+#define __ASM_ARCH_MX6_MX6Q_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS (1 << 16)
+#define PAD_CTL_PUS_100K_DOWN (0 << 14)
+#define PAD_CTL_PUS_47K_UP (1 << 14)
+#define PAD_CTL_PUS_100K_UP (2 << 14)
+#define PAD_CTL_PUS_22K_UP (3 << 14)
+
+#define PAD_CTL_PUE (1 << 13)
+#define PAD_CTL_PKE (1 << 12)
+#define PAD_CTL_ODE (1 << 11)
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
+enum {
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
+ MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0),
+ MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0),
+ MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0),
+ MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0),
+ MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0),
+ MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0),
+ MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0),
+ MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0),
+ MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
+ MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
+ MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
+ MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
+ MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
+ MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
+ MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0),
+ MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
+ MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0),
+ MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0),
+ MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0),
+ MX6_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0),
+ MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0),
+ MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0),
+ MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0),
+ MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0),
+ MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0),
+ MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0),
+ MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0),
+ MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0),
+ MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0),
+ MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0),
+ MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0),
+ MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0),
+ MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0),
+ MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0),
+ MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
+ MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0),
+ MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0),
+ MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0),
+ MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0),
+ MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0),
+ MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0),
+ MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0),
+ MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0),
+ MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0),
+ MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0),
+ MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0),
+ MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0),
+ MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
+ MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
+ MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0),
+ MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
+ MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
+ MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0),
+ MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
+ MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
+ MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
+ MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
+ MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0),
+ MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0),
+ MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0),
+ MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0),
+ MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0),
+ MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0),
+ MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0),
+ MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0),
+ MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0),
+ MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0),
+ MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0),
+ MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0),
+ MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0),
+ MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0),
+ MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0),
+ MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0),
+ MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0),
+ MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0),
+ MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0),
+ MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0),
+ MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0),
+ MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0),
+ MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0),
+ MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0),
+ MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0),
+ MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0),
+ MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0),
+ MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
+ MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
+ MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
+ MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
+ MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
+ MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
+ MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
+ MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
+ MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
+ MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
+ MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
+ MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
+ MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
+ MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
+ MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
+ MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
+ MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0),
+ MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
+ MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
+ MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0),
+ MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
+ MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
+ MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
+ MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
+ MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
+ MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
+ MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
+ MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
+ MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
+ MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
+ MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0),
+ MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0),
+ MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0),
+ MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0),
+ MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0),
+ MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
+ MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0),
+ MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0),
+ MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0),
+ MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0),
+ MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0),
+ MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0),
+ MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0),
+ MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0),
+ MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0),
+ MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0),
+ MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0),
+ MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0),
+ MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0),
+ MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0),
+ MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
+ MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
+ MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0),
+ MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
+ MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
+ MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0),
+ MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0),
+ MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
+ MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
+ MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0),
+ MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
+ MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
+ MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0),
+ MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0),
+ MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0),
+ MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0),
+ MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0),
+ MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0),
+ MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0),
+ MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0),
+ MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0),
+ MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0),
+ MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0),
+ MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0),
+ MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0),
+ MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0),
+ MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0),
+ MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
+ MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
+ MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0),
+ MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
+ MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
+ MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0),
+ MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0),
+ MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0),
+ MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
+ MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
+ MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
+ MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0),
+ MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0),
+ MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0),
+ MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0),
+ MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0),
+ MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0),
+ MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0),
+ MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0),
+ MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0),
+ MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
+ MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
+ MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0),
+ MX6_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0),
+ MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
+ MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0),
+ MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
+ MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
+ MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
+ MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
+ MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0),
+ MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0),
+ MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0),
+ MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0),
+ MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0),
+ MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0),
+ MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0),
+ MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0),
+ MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0),
+ MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0),
+ MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0),
+ MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0),
+ MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0),
+ MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0),
+ MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0),
+ MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0),
+ MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0),
+ MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0),
+ MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0),
+ MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0),
+ MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0),
+ MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0),
+ MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0),
+ MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0),
+ MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0),
+ MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
+ MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
+ MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
+ MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
+ MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
+ MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
+ MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
+ MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
+ MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0),
+ MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0),
+ MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0),
+ MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0),
+ MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
+ MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
+ MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
+ MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
+ MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
+ MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0),
+ MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0),
+ MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
+ MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0),
+ MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0),
+ MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
+ MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
+ MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
+ MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0),
+ MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0),
+ MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
+ MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
+ MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
+ MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
+ MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0),
+ MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0),
+ MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
+ MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0),
+ MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0),
+ MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
+ MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0),
+ MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0),
+ MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0),
+ MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0),
+ MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0),
+ MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0),
+ MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0),
+ MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0),
+ MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0),
+ MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0),
+ MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0),
+ MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
+};
+
+#endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
deleted file mode 100644
index 3ade8dc433..0000000000
--- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h
+++ /dev/null
@@ -1,1671 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Auto Generate file, please don't edit it
- *
- */
-
-#ifndef __ASM_ARCH_MX6_MX6X_PINS_H__
-#define __ASM_ARCH_MX6_MX6X_PINS_H__
-
-#include <asm/imx-common/iomux-v3.h>
-
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-
-enum {
- MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
- MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0),
- MX6Q_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0),
- MX6Q_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0),
- MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0),
- MX6Q_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0),
- MX6Q_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0),
- MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0),
- MX6Q_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0),
- MX6Q_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
- MX6Q_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
- MX6Q_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
- MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
- MX6Q_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
- MX6Q_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
- MX6Q_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0),
- MX6Q_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0),
- MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0),
- MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0),
- MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0),
- MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0),
- MX6Q_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0),
- MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0),
- MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0),
- MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0),
- MX6Q_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0),
- MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0),
- MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0),
- MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0),
- MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0),
- MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0),
- MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0),
- MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0),
- MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0),
- MX6Q_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
- MX6Q_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0),
- MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0),
- MX6Q_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0),
- MX6Q_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0),
- MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0),
- MX6Q_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0),
- MX6Q_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0),
- MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0),
- MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0),
- MX6Q_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0),
- MX6Q_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0),
- MX6Q_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0),
- MX6Q_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0),
- MX6Q_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
- MX6Q_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
- MX6Q_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0),
- MX6Q_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
- MX6Q_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
- MX6Q_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
- MX6Q_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
- MX6Q_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0),
- MX6Q_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0),
- MX6Q_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0),
- MX6Q_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0),
- MX6Q_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0),
- MX6Q_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0),
- MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0),
- MX6Q_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0),
- MX6Q_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0),
- MX6Q_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0),
- MX6Q_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0),
- MX6Q_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0),
- MX6Q_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0),
- MX6Q_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0),
- MX6Q_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0),
- MX6Q_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0),
- MX6Q_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0),
- MX6Q_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0),
- MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0),
- MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0),
- MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0),
- MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0),
- MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0),
- MX6Q_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0),
- MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0),
- MX6Q_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0),
- MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0),
- MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
- MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
- MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
- MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
- MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
- MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
- MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
- MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
- MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
- MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
- MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
- MX6Q_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
- MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
- MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
- MX6Q_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0),
- MX6Q_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0),
- MX6Q_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
- MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
- MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
- MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
- MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
- MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
- MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
- MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
- MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
- MX6Q_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
- MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0),
- MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0),
- MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0),
- MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
- MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0),
- MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0),
- MX6Q_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0),
- MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0),
- MX6Q_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0),
- MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0),
- MX6Q_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0),
- MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0),
- MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0),
- MX6Q_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0),
- MX6Q_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0),
- MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0),
- MX6Q_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0),
- MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
- MX6Q_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
- MX6Q_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0),
- MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
- MX6Q_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
- MX6Q_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0),
- MX6Q_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0),
- MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
- MX6Q_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
- MX6Q_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0),
- MX6Q_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
- MX6Q_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
- MX6Q_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0),
- MX6Q_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0),
- MX6Q_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0),
- MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0),
- MX6Q_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0),
- MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0),
- MX6Q_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0),
- MX6Q_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0),
- MX6Q_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0),
- MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0),
- MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0),
- MX6Q_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0),
- MX6Q_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0),
- MX6Q_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0),
- MX6Q_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0),
- MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
- MX6Q_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
- MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0),
- MX6Q_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
- MX6Q_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
- MX6Q_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0),
- MX6Q_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0),
- MX6Q_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0),
- MX6Q_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
- MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
- MX6Q_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
- MX6Q_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0),
- MX6Q_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0),
- MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0),
- MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0),
- MX6Q_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0),
- MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0),
- MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0),
- MX6Q_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0),
- MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0),
- MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
- MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
- MX6Q_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0),
- MX6Q_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0),
- MX6Q_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
- MX6Q_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0),
- MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
- MX6Q_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
- MX6Q_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
- MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
- MX6Q_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0),
- MX6Q_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0),
- MX6Q_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0),
- MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0),
- MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0),
- MX6Q_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0),
- MX6Q_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0),
- MX6Q_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0),
- MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0),
- MX6Q_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0),
- MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0),
- MX6Q_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0),
- MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0),
- MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0),
- MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0),
- MX6Q_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0),
- MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0),
- MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0),
- MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0),
- MX6Q_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0),
- MX6Q_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0),
- MX6Q_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0),
- MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0),
- MX6Q_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0),
- MX6Q_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
- MX6Q_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
- MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
- MX6Q_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
- MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
- MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
- MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
- MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
- MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0),
- MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0),
- MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0),
- MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0),
- MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
- MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
- MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
- MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
- MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
- MX6Q_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0),
- MX6Q_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0),
- MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
- MX6Q_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0),
- MX6Q_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0),
- MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
- MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
- MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__PL301_P