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-rw-r--r--arch/arm/cpu/armv7/cache_v7.c3
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c35
2 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 5f6d0396f3..8748c145c4 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -340,6 +340,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
}
+void arm_init_domains(void)
+{
+}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#ifndef CONFIG_SYS_ICACHE_OFF
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 05ff2e868f..70d16a8160 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -34,6 +34,12 @@
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>
+#include <asm/cache.h>
+#include <asm/system.h>
+
+#define ARMV7_DCACHE_WRITEBACK 0xe
+#define ARMV7_DOMAIN_CLIENT 1
+#define ARMV7_DOMAIN_MASK (0x3 << 0)
DECLARE_GLOBAL_DATA_PTR;
@@ -269,4 +275,33 @@ void enable_caches(void)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
+
+void dram_bank_mmu_setup(int bank)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ u32 start = bd->bi_dram[bank].start >> 20;
+ u32 size = bd->bi_dram[bank].size >> 20;
+ u32 end = start + size;
+
+ debug("%s: bank: %d\n", __func__, bank);
+ for (i = start; i < end; i++)
+ set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+
+}
+
+void arm_init_domains(void)
+{
+ u32 reg;
+
+ reg = get_dacr();
+ /*
+ * Set DOMAIN to client access so that all permissions
+ * set in pagetables are validated by the mmu.
+ */
+ reg &= ~ARMV7_DOMAIN_MASK;
+ reg |= ARMV7_DOMAIN_CLIENT;
+ set_dacr(reg);
+}
#endif
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