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-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/cpu/arm1136/mx35/Makefile1
-rw-r--r--arch/arm/cpu/arm1136/mx35/mx35_sdram.c137
-rw-r--r--arch/arm/include/asm/arch-mx35/sys_proto.h2
-rw-r--r--board/woodburn/Makefile43
-rw-r--r--board/woodburn/imximage.cfg4
-rw-r--r--board/woodburn/lowlevel_init.S38
-rw-r--r--board/woodburn/woodburn.c261
-rw-r--r--boards.cfg2
-rw-r--r--include/configs/woodburn.h34
-rw-r--r--include/configs/woodburn_common.h313
-rw-r--r--include/configs/woodburn_sd.h60
12 files changed, 896 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 971235bbca..311c0e7fb6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -584,6 +584,7 @@ Stefano Babic <sbabic@denx.de>
trizepsiv xscale/pxa
twister omap3
vision2 i.MX51
+ woodburn i.MX35
Jason Liu <r64343@freescale.com>
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index 469397ca43..f4ababbe5b 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).o
COBJS += generic.o
COBJS += timer.o
COBJS += iomux.o
+COBJS += mx35_sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
new file mode 100644
index 0000000000..f7e682c8c5
--- /dev/null
+++ b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+enum {
+ SMODE_NORMAL = 0,
+ SMODE_PRECHARGE,
+ SMODE_AUTO_REFRESH,
+ SMODE_LOAD_REG,
+ SMODE_MANUAL_REFRESH
+};
+
+#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
+
+static inline void dram_wait(unsigned int count)
+{
+ volatile unsigned int wait = count;
+
+ while (wait--)
+ ;
+
+}
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+ u32 row, u32 col, u32 dsize, u32 refresh)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+ u32 *cfg_reg, *ctl_reg;
+ u32 val;
+ u32 ctlval;
+
+ switch (start_address) {
+ case CSD0_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg0;
+ ctl_reg = &esdc->esdctl0;
+ break;
+ case CSD1_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg1;
+ ctl_reg = &esdc->esdctl1;
+ break;
+ default:
+ return;
+ }
+
+ /* The MX35 supports 11 up to 14 rows */
+ if (row < 11 || row > 14 || col < 8 || col > 10)
+ return;
+ ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ dram_wait(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ddr2_config, cfg_reg);
+
+ /* Precharge ALL */
+ writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
+ ctl_reg);
+ writel(0xda, start_address);
+ writel(0xda, start_address);
+
+ writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_MR);
+ writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
+ ctl_reg);
+
+ dram_wait(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h
index 9c0d51321d..aa3549cb0d 100644
--- a/arch/arm/include/asm/arch-mx35/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx35/sys_proto.h
@@ -25,6 +25,8 @@
#define _SYS_PROTO_H_
u32 get_cpu_rev(void);
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+ u32 row, u32 col, u32 dsize, u32 refresh);
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
#endif
diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile
new file mode 100644
index 0000000000..b60163f9fd
--- /dev/null
+++ b/board/woodburn/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := woodburn.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/woodburn/imximage.cfg b/board/woodburn/imximage.cfg
new file mode 100644
index 0000000000..b4cc8ecf63
--- /dev/null
+++ b/board/woodburn/imximage.cfg
@@ -0,0 +1,4 @@
+BOOT_FROM sd
+
+# DDR2 init
+DATA 4 0xB8001010 0x00000304
diff --git a/board/woodburn/lowlevel_init.S b/board/woodburn/lowlevel_init.S
new file mode 100644
index 0000000000..57fb1b139e
--- /dev/null
+++ b/board/woodburn/lowlevel_init.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
new file mode 100644
index 0000000000..286749f3c9
--- /dev/null
+++ b/board/woodburn/woodburn.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Based on flea3.c and mx35pdk.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <spl.h>
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+
+/* For MMC */
+#define GPIO_MMC_CD 7
+#define GPIO_MMC_WP 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void board_setup_sdram(void)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+ 13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+}
+
+int woodburn_init(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_fec();
+
+ /* setup GPIO1_4 FEC_ENABLE signal */
+ mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+ gpio_direction_output(4, 1);
+ mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+ gpio_direction_output(9, 0);
+ gpio_set_value(9, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void board_init_f(ulong dummy)
+{
+ /* Set the stack pointer. */
+ asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+ /* Initialize MUX and SDRAM */
+ woodburn_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end__ - __bss_start);
+
+ /* Set global data pointer. */
+ gd = &gdata;
+
+ preloader_console_init();
+ timer_init();
+
+ board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+}
+
+#endif
+
+
+/* Booting from NOR in external mode */
+int board_early_init_f(void)
+{
+ return woodburn_init();
+}
+
+
+int board_init(void)
+{
+ struct pmic *p;
+ u32 val;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ pmic_init();
+ p = get_pmic();
+
+ /*
+ * Set switchers in Auto in NORMAL mode & STANDBY mode
+ * Setup the switcher mode for SW1 & SW2
+ */
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ /* Set SWILIMB */
+ val |= (1 << 22);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+ (SWMODE_MASK << SWMODE3_SHIFT));
+ val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VGEN1 to 3.15V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VGEN1_MASK);
+ val |= VGEN1_3_15;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= VGEN1EN;
+ pmic_reg_write(p, REG_MODE_0, val);
+ udelay(2000);
+
+ return 0;
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+ /* configure pins for SDHC1 only */
+ mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+ /* MMC Card Detect on GPIO1_7 */
+ mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+ gpio_direction_input(GPIO_MMC_CD);
+
+ mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+ gpio_direction_output(GPIO_MMC_WP, 0);
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(GPIO_MMC_CD);
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/boards.cfg b/boards.cfg
index 4b17289722..04ecdeb4df 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -50,6 +50,8 @@ tt01 arm arm1136 - hale
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
+woodburn arm arm1136 - - mx35
+woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
rpi_b arm arm1176 rpi_b raspberrypi bcm2835
diff --git a/include/configs/woodburn.h b/include/configs/woodburn.h
new file mode 100644
index 0000000000..95a71c45b2
--- /dev/null
+++ b/include/configs/woodburn.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
new file mode 100644
index 0000000000..58a96cffce
--- /dev/null
+++ b/include/configs/woodburn_common.h
@@ -0,0 +1,313 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __WOODBURN_COMMON_CONFIG_H
+#define __WOODBURN_COMMON_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3 3668
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* This is required to setup the ESDC controller */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* PMIC Controller */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_PMIC_FSL
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
+#define CONFIG_RTC_MC13XXX
+
+
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_CMD_GPIO
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "woodburn U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
+ IRAM_BASE_ADDR - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
+ "32m(rootfb)," \
+ "64m(pcache)," \
+ "64m(app1)," \
+ "10m(app2),-(spool);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 7
+#endif
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME woodburn
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=80800000\0" \
+ "kernel_addr_r=80800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +80000;" \
+ "erase ${uboot_addr} +80000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h
new file mode 100644
index 0000000000..63185c5432
--- /dev/null
+++ b/include/configs/woodburn_sd.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT in RAM */
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+
+#define CONFIG_BOOT_INTERNAL
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x100 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x10002300
+#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+
+#endif /* __CONFIG_H */
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