diff options
99 files changed, 3161 insertions, 1198 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 48db504dad..3879fde425 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -943,6 +943,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF518F-EZBRD BF518 BF526-EZBRD BF526 BF527-EZKIT BF527 + BF527-EZKIT-V2 BF527 BF533-EZKIT BF533 BF533-STAMP BF533 BF537-PNAV BF537 @@ -960,6 +961,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> CM-BF537U BF537 CM-BF548 BF548 CM-BF561 BF561 + TCM-BF518 BF518 TCM-BF537 BF537 Martin Strubel <strubel@section5.ch> @@ -978,6 +980,11 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> IBF-DSP561 BF561 +Valentin Yakovenkov <yakovenkov@niistt.ru> +Anton Shurpin <shurpin.aa@niistt.ru> + + BF561-ACVILON BF561 + ######################################################################### # End of MAINTAINERS list # ######################################################################### @@ -871,6 +871,7 @@ LIST_blackfin=" \ bf518f-ezbrd \ bf526-ezbrd \ bf527-ezkit \ + bf527-ezkit-v2 \ bf533-ezkit \ bf533-stamp \ bf537-minotaur \ @@ -879,6 +880,7 @@ LIST_blackfin=" \ bf537-stamp \ bf538f-ezkit \ bf548-ezkit \ + bf561-acvilon \ bf561-ezkit \ blackstamp \ cm-bf527 \ @@ -888,6 +890,7 @@ LIST_blackfin=" \ cm-bf548 \ cm-bf561 \ ibf-dsp561 \ + tcm-bf518 \ tcm-bf537 \ " @@ -308,7 +308,7 @@ $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(obj)u-boot.ldr: $(obj)u-boot - $(obj)tools/envcrc --binary > $(obj)env-ldr.o + $(CREATE_LDR_ENV) $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) $(obj)u-boot.ldr.hex: $(obj)u-boot.ldr @@ -3528,10 +3528,11 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \ bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit # Bluetechnix tinyboards -BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 tcm-bf537 +BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 \ + tcm-bf518 tcm-bf537 # Misc third party boards -BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp +BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp # I-SYST Micromodule BFIN_BOARDS += ibf-dsp561 @@ -3539,6 +3540,10 @@ BFIN_BOARDS += ibf-dsp561 $(BFIN_BOARDS:%=%_config) : unconfig @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=) +bf527-ezkit-v2_config : unconfig + @$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \ + bf527-ezkit blackfin blackfin bf527-ezkit + #======================================================================== # AVR32 #======================================================================== diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 63be7cf06c..85b350f3ec 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -15,6 +15,7 @@ #include <asm/blackfin.h> #include <asm/net.h> #include <asm/mach-common/bits/otp.h> +#include <asm/sdh.h> DECLARE_GLOBAL_DATA_PTR; @@ -25,13 +26,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #if defined(CONFIG_BFIN_MAC) static void board_init_enetaddr(uchar *mac_addr) { @@ -162,3 +156,10 @@ int board_early_init_f(void) #endif return 0; } + +#ifdef CONFIG_BFIN_SDH +int board_mmc_init(bd_t *bis) +{ + return bfin_mmc_init(bis); +} +#endif diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c index 1666bf6614..52d82cd87e 100644 --- a/board/bf526-ezbrd/bf526-ezbrd.c +++ b/board/bf526-ezbrd/bf526-ezbrd.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index 2cbfa8d03a..a911880ee3 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { @@ -75,3 +68,16 @@ int misc_init_r(void) return 0; } + +#ifdef CONFIG_USB_BLACKFIN +void board_musb_init(void) +{ + /* + * BF527 EZ-KITs require PG13 to be high for HOST mode + */ + bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13); + bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13); + bfin_write_PORTGIO_SET(PG13); + SSYNC(); +} +#endif diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 57652be293..8f6ea2308f 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -12,40 +12,111 @@ #include <malloc.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/dma.h> -#include <i2c.h> +#include <spi.h> #include <linux/types.h> #include <stdio_dev.h> -#define DMA_SIZE16 2 - #include <asm/mach-common/bits/ppi.h> #include <asm/mach-common/bits/timer.h> -#include <asm/bfin_logo_230x230.h> - #define LCD_X_RES 320 /* Horizontal Resolution */ #define LCD_Y_RES 240 /* Vertical Resolution */ -#define LCD_BPP 24 /* Bit Per Pixel */ -#define LCD_PIXEL_SIZE (LCD_BPP / 8) +#define DMA_BUS_SIZE 16 + +#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 /* lq035q1 */ + +#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \ + !defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI) +# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI +#endif + +/* Interface 16/18-bit TFT over an 8-bit wide PPI using a + * small Programmable Logic Device (CPLD) + * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165 + */ + +#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI +#include <asm/bfin_logo_rgb565_230x230.h> +#define LCD_BPP 16 /* Bit Per Pixel */ +#define CLOCKS_PPIX 2 /* Clocks per pixel */ +#define CPLD_DELAY 3 /* RGB565 pipeline delay */ +#endif + +#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI +#include <asm/bfin_logo_230x230.h> +#define LCD_BPP 24 /* Bit Per Pixel */ +#define CLOCKS_PPIX 3 /* Clocks per pixel */ +#define CPLD_DELAY 5 /* RGB888 pipeline delay */ +#endif + +/* + * HS and VS timing parameters (all in number of PPI clk ticks) + */ + +#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */ +#define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */ +#define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */ +#define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */ + +#define U_LINE 4 /* Blanking Lines */ + +#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */ +#define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */ +#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */ + +#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8)) + +/* + * LCD Modes + */ +#define LQ035_RL (0 << 8) /* Right -> Left Scan */ +#define LQ035_LR (1 << 8) /* Left -> Right Scan */ +#define LQ035_TB (1 << 9) /* Top -> Botton Scan */ +#define LQ035_BT (0 << 9) /* Botton -> Top Scan */ +#define LQ035_BGR (1 << 11) /* Use BGR format */ +#define LQ035_RGB (0 << 11) /* Use RGB format */ +#define LQ035_NORM (1 << 13) /* Reversal */ +#define LQ035_REV (0 << 13) /* Reversal */ + +#define LQ035_INDEX 0x74 +#define LQ035_DATA 0x76 -#define DMA_BUS_SIZE 16 -#define LCD_CLK (12*1000*1000) /* 12MHz */ +#define LQ035_DRIVER_OUTPUT_CTL 0x1 +#define LQ035_SHUT_CTL 0x11 -#define CLOCKS_PER_PIX 3 +#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV) +#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK) + +#define LQ035_SHUT (1 << 0) /* Shutdown */ +#define LQ035_ON (0 << 0) /* Shutdown */ + +#ifndef CONFIG_LQ035Q1_LCD_MODE +#define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR) +#endif + +#else /* t350mcqb */ +#include <asm/bfin_logo_230x230.h> + +#define LCD_BPP 24 /* Bit Per Pixel */ +#define CLOCKS_PPIX 3 /* Clocks per pixel */ /* HS and VS timing parameters (all in number of PPI clk ticks) */ -#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */ -#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */ +#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */ +#define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */ #define H_PULSE 90 /* HS pulse width */ #define H_START 204 /* first valid pixel */ #define U_LINE 1 /* Blanking Lines */ -#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */ +#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */ #define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */ #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */ #define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX) +#endif + +#define LCD_PIXEL_SIZE (LCD_BPP / 8) +#define DMA_SIZE16 2 #define PPI_TX_MODE 0x2 #define PPI_XFER_TYPE_11 0xC @@ -53,6 +124,40 @@ #define PPI_PACK_EN 0x80 #define PPI_POLS_1 0x8000 +#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 +static struct spi_slave *slave; +static int lq035q1_control(unsigned char reg, unsigned short value) +{ + int ret; + u8 regs[3] = {LQ035_INDEX, 0, 0}; + u8 data[3] = {LQ035_DATA, 0, 0}; + u8 dummy[3]; + + regs[2] = reg; + data[1] = value >> 8; + data[2] = value & 0xFF; + + if (!slave) { + /* FIXME: Verify the max SCK rate */ + slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS, + CONFIG_LQ035Q1_SPI_CS, 20000000, + SPI_MODE_3); + if (!slave) + return -1; + } + + if (spi_claim_bus(slave)) + return -1; + + ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + + spi_release_bus(slave); + + return ret; +} +#endif + /* enable and disable PPI functions */ void EnablePPI(void) { @@ -80,7 +185,7 @@ void Init_PPI(void) *pPPI_DELAY = H_START; *pPPI_COUNT = (H_ACTPIX-1); - *pPPI_FRAME = 0; + *pPPI_FRAME = V_LINES; /* PPI control, to be replaced with definitions */ *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */ @@ -188,9 +293,20 @@ void DisableTIMER1(void) SSYNC(); } +void EnableTIMER12(void) +{ + *pTIMER_ENABLE |= TIMEN1 | TIMEN0; + SSYNC(); +} + int video_init(void *dst) { +#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 + lq035q1_control(LQ035_SHUT_CTL, LQ035_ON); + lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE & + LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT); +#endif Init_Ports(); Init_DMA(dst); EnableDMA(); @@ -199,6 +315,9 @@ int video_init(void *dst) Init_PPI(); EnablePPI(); +#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 + EnableTIMER12(); +#else /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */ EnableTIMER1(); /* Add Some Delay ... */ @@ -209,6 +328,7 @@ int video_init(void *dst) /* now start frame sync 1 */ EnableTIMER0(); +#endif return 0; } diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 8727dee6d9..b1aa7b7cee 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -39,13 +39,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - /* miscellaneous platform dependent initialisations */ int misc_init_r(void) { diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index dbba12b848..832037b17c 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -30,6 +30,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y := $(BOARD).o +COBJS-$(CONFIG_STAMP_CF) += ide-cf.o COBJS-$(CONFIG_VIDEO) += video.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index a2269105be..4abad08cd9 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -39,13 +39,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - /* PF0 and PF1 are used to switch between the ethernet and flash: * PF0 PF1 * flash: 0 0 @@ -69,118 +62,11 @@ void swap_to(int device_id) /* miscellaneous platform dependent initialisations */ int misc_init_r(void) { - int i; - int cf_stat = 0; - - /* Check whether CF card is inserted */ - *pFIO_EDGE = FIO_EDGE_CF_BITS; - *pFIO_POLAR = FIO_POLAR_CF_BITS; - for (i = 0; i < 0x300; i++) - asm("nop;"); - - if ((*pFIO_FLAG_S) & CF_STAT_BITS) { - cf_stat = 0; - } else { - cf_stat = 1; - } - - *pFIO_EDGE = FIO_EDGE_BITS; - *pFIO_POLAR = FIO_POLAR_BITS; - - if (cf_stat) { - printf("Booting from COMPACT flash\n"); - - for (i = 0; i < 0x1000; i++) - asm("nop;"); - for (i = 0; i < 0x1000; i++) - asm("nop;"); - for (i = 0; i < 0x1000; i++) - asm("nop;"); - - serial_setbrg(); - ide_init(); - - setenv("bootargs", ""); - setenv("bootcmd", - "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000"); - } else { - printf("Booting from FLASH\n"); - } - - return 0; -} -#endif - #ifdef CONFIG_STAMP_CF + cf_ide_init(); +#endif -void cf_outb(unsigned char val, volatile unsigned char *addr) -{ - /* - * Set PF1 PF0 respectively to 0 1 to divert address - * to the expansion memory banks - */ - *pFIO_FLAG_S = CF_PF0; - *pFIO_FLAG_C = CF_PF1; - SSYNC(); - - *(addr) = val; - SSYNC(); - - /* Setback PF1 PF0 to 0 0 to address external - * memory banks */ - *(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0; - SSYNC(); -} - -unsigned char cf_inb(volatile unsigned char *addr) -{ - volatile unsigned char c; - - *pFIO_FLAG_S = CF_PF0; - *pFIO_FLAG_C = CF_PF1; - SSYNC(); - - c = *(addr); - SSYNC(); - - *pFIO_FLAG_C = CF_PF1_PF0; - SSYNC(); - - return c; -} - -void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) -{ - int i; - - *pFIO_FLAG_S = CF_PF0; - *pFIO_FLAG_C = CF_PF1; - SSYNC(); - - for (i = 0; i < words; i++) { - *(sect_buf + i) = *(addr); - SSYNC(); - } - - *pFIO_FLAG_C = CF_PF1_PF0; - SSYNC(); -} - -void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) -{ - int i; - - *pFIO_FLAG_S = CF_PF0; - *pFIO_FLAG_C = CF_PF1; - SSYNC(); - - for (i = 0; i < words; i++) { - *(addr) = *(sect_buf + i); - SSYNC(); - } - - *pFIO_FLAG_C = CF_PF1_PF0; - SSYNC(); + return 0; } #endif diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c new file mode 100644 index 0000000000..23e786b5b8 --- /dev/null +++ b/board/bf533-stamp/ide-cf.c @@ -0,0 +1,90 @@ +/* + * CF IDE addon card code + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <asm/blackfin.h> +#include "bf533-stamp.h" + +void cf_outb(unsigned char val, volatile unsigned char *addr) +{ + /* "ETHERNET" means the expansion memory banks */ + swap_to(ETHERNET); + + *addr = val; + SSYNC(); + + swap_to(FLASH); +} + +unsigned char cf_inb(volatile unsigned char *addr) +{ + unsigned char c; + + swap_to(ETHERNET); + + c = *addr; + SSYNC(); + + swap_to(FLASH); + + return c; +} + +void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) +{ + int i; + + swap_to(ETHERNET); + + for (i = 0; i < words; i++) { + *(sect_buf + i) = *addr; + SSYNC(); + } + + swap_to(FLASH); +} + +void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) +{ + int i; + + swap_to(ETHERNET); + + for (i = 0; i < words; i++) { + *addr = *(sect_buf + i); + SSYNC(); + } + + swap_to(FLASH); +} + +void cf_ide_init(void) +{ + int i, cf_stat; + + /* Check whether CF card is inserted */ + bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS); + bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS); + for (i = 0; i < 0x300; i++) + asm volatile("nop;"); + + cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS; + + bfin_write_FIO_EDGE(FIO_EDGE_BITS); + bfin_write_FIO_POLAR(FIO_POLAR_BITS); + + if (!cf_stat) { + for (i = 0; i < 0x3000; i++) + asm volatile("nop;"); + + ide_init(); + } +} diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c index 71b452a4f8..920429c12e 100644 --- a/board/bf537-minotaur/bf537-minotaur.c +++ b/board/bf537-minotaur/bf537-minotaur.c @@ -23,13 +23,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c index 12cfefa8ff..c5125288cb 100644 --- a/board/bf537-pnav/bf537-pnav.c +++ b/board/bf537-pnav/bf537-pnav.c @@ -23,13 +23,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c index 5ad39cc935..04d38910b3 100644 --- a/board/bf537-srv1/bf537-srv1.c +++ b/board/bf537-srv1/bf537-srv1.c @@ -23,13 +23,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 28597c9e69..3911be671b 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -43,13 +43,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - void board_reset(void) { /* workaround for weak pull ups on ssel */ diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c index 15916fad64..49d30e75d0 100644 --- a/board/bf538f-ezkit/bf538f-ezkit.c +++ b/board/bf538f-ezkit/bf538f-ezkit.c @@ -20,13 +20,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index 88a0cd4d61..65fb81a9c5 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -11,6 +11,7 @@ #include <config.h> #include <command.h> #include <asm/blackfin.h> +#include <asm/sdh.h> DECLARE_GLOBAL_DATA_PTR; @@ -21,13 +22,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - int board_early_init_f(void) { /* Port H: PH8 - PH13 == A4 - A9 @@ -85,3 +79,26 @@ int board_eth_init(bd_t *bis) return smc911x_initialize(0, CONFIG_SMC911X_BASE); } #endif + +#ifdef CONFIG_BFIN_SDH +int board_mmc_init(bd_t *bis) +{ + return bfin_mmc_init(bis); +} +#endif + +#ifdef CONFIG_USB_BLACKFIN +void board_musb_init(void) +{ + /* + * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device + * and OTG host modes, while rev 1.1 and greater require PE7 to + * be low for device mode and high for host mode. We set it high + * here because we are in host mode. + */ + bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7); + bfin_write_PORTE_DIR_SET(PE7); + bfin_write_PORTE_SET(PE7); + SSYNC(); +} +#endif diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile new file mode 100644 index 0000000000..cc039a05e9 --- /dev/null +++ b/board/bf561-acvilon/Makefile @@ -0,0 +1,56 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2007 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf561-acvilon/bf561-acvilon.c b/board/bf561-acvilon/bf561-acvilon.c new file mode 100644 index 0000000000..483758ef99 --- /dev/null +++ b/board/bf561-acvilon/bf561-acvilon.c @@ -0,0 +1,51 @@ +/* + * File: board/bf561-acvilon/bf561-acvilon.c + * Based on: board/bf561-ezkit/bf561-ezkit.c + * Author: + * + * Created: 2009-06-23 + * Description: Acvilon System On Module board file + * + * Modified: + * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Bugs: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <common.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n"); + printf(" Support: http://www.niistt.ru/\n"); + return 0; +} + +#ifdef CONFIG_SMC911X +int board_eth_init(bd_t *bis) +{ + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +} +#endif diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk new file mode 100644 index 0000000000..cfad21a2a4 --- /dev/null +++ b/board/bf561-acvilon/config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index e5d7eb3388..b2411b65bf 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -38,13 +38,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c index f55ab975e4..6355c10959 100644 --- a/board/blackstamp/blackstamp.c +++ b/board/blackstamp/blackstamp.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef SHARED_RESOURCES void swap_to(int device_id) { diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c index db1cf9028c..b6815b1ccd 100644 --- a/board/cm-bf527/cm-bf527.c +++ b/board/cm-bf527/cm-bf527.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c index ab0bf3bf65..a863195057 100644 --- a/board/cm-bf533/cm-bf533.c +++ b/board/cm-bf533/cm-bf533.c @@ -18,13 +18,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c index d1ca0a420f..1e350dc064 100644 --- a/board/cm-bf537e/cm-bf537e.c +++ b/board/cm-bf537e/cm-bf537e.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index 9628e0f949..92fa5a0993 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c index 796263d62b..3627586b69 100644 --- a/board/cm-bf548/cm-bf548.c +++ b/board/cm-bf548/cm-bf548.c @@ -21,13 +21,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - int board_early_init_f(void) { /* Port H: PH8 - PH13 == A4 - A9 diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c index f21a015e42..80cfff7242 100644 --- a/board/cm-bf561/cm-bf561.c +++ b/board/cm-bf561/cm-bf561.c @@ -18,13 +18,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c index 551fc291a0..b5bebd4a90 100644 --- a/board/ibf-dsp561/ibf-dsp561.c +++ b/board/ibf-dsp561/ibf-dsp561.c @@ -16,10 +16,3 @@ int checkboard(void) printf(" Support: http://www.i-syst.com/\n"); return 0; } - -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile new file mode 100644 index 0000000000..f2bd2c247d --- /dev/null +++ b/board/tcm-bf518/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk new file mode 100644 index 0000000000..f85bef5e2a --- /dev/null +++ b/board/tcm-bf518/config.mk @@ -0,0 +1,33 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c new file mode 100644 index 0000000000..5964059dd1 --- /dev/null +++ b/board/tcm-bf518/tcm-bf518.c @@ -0,0 +1,78 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2008-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <net.h> +#include <netdev.h> +#include <asm/blackfin.h> +#include <asm/net.h> +#include <asm/mach-common/bits/otp.h> +#include <asm/sdh.h> + +int checkboard(void) +{ + printf("Board: Bluetechnix TCM-BF518 board\n"); + printf(" Support: http://www.bluetechnix.com/\n"); + printf(" http://blackfin.uclinux.org/\n"); + return 0; +} + +#if defined(CONFIG_BFIN_MAC) +static void board_init_enetaddr(uchar *mac_addr) +{ + bool valid_mac = false; + +#if 0 + /* the MAC is stored in OTP memory page 0xDF */ + uint32_t ret; + uint64_t otp_mac; + + ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac); + if (!(ret & OTP_MASTER_ERROR)) { + uchar *otp_mac_p = (uchar *)&otp_mac; + + for (ret = 0; ret < 6; ++ret) + mac_addr[ret] = otp_mac_p[5 - ret]; + + if (is_valid_ether_addr(mac_addr)) + valid_mac = true; + } +#endif + + if (!valid_mac) { + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + } + + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + return 0; +} + +#ifdef CONFIG_BFIN_SDH +int board_mmc_init(bd_t *bis) +{ + return bfin_mmc_init(bis); +} +#endif diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 573387d4f6..60742dfea5 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/cpu/blackfin/Makefile b/cpu/blackfin/Makefile index 5eef6a3063..211b8d5450 100644 --- a/cpu/blackfin/Makefile +++ b/cpu/blackfin/Makefile @@ -24,7 +24,7 @@ COBJS-y += os_log.o COBJS-y += reset.o COBJS-y += serial.o COBJS-y += traps.o -COBJS-y += watchdog.o +COBJS-$(CONFIG_HW_WATCHDOG) += watchdog.o ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) COBJS-y += initcode.o diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c index 9bb6407fc6..2c8fd86b86 100644 --- a/cpu/blackfin/cpu.c +++ b/cpu/blackfin/cpu.c @@ -25,13 +25,12 @@ ulong bfin_poweron_retx; __attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { - extern char _stext_l1; #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1 /* Build a NOP slide over the LDR jump block. Whee! */ char nops[0xC]; serial_early_puts("NOP Slide\n"); memset(nops, 0x00, sizeof(nops)); - memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops)); + memcpy((void *)L1_INST_SRAM, nops, sizeof(nops)); #endif if (!loaded_from_ldr) { @@ -40,10 +39,10 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) * checking at build time. */ serial_early_puts("L1 Relocate\n"); - extern char _stext_l1, _etext_l1, _stext_l1_lma; - memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1)); - extern char _sdata_l1, _edata_l1, _sdata_l1_lma; - memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1)); + extern char _stext_l1[], _text_l1_lma[], _text_l1_len[]; + memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len); + extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[]; + memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len); } #if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) /* The BF537 bootrom will reset the EBIU_AMGCTL register on us diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index a039cbbbce..5f80ad615e 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -9,6 +9,8 @@ * Licensed under the GPL-2 or later. */ +#define BFIN_IN_INITCODE + #include <config.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/bootrom.h> @@ -17,7 +19,6 @@ #include <asm/mach-common/bits/pll.h> #include <asm/mach-common/bits/uart.h> -#define BFIN_IN_INITCODE #include "serial.h" __attribute__((always_inline)) @@ -33,7 +34,7 @@ static inline void serial_init(void) size_t i; /* force RTS rather than relying on auto RTS */ - bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL); + bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL); /* Wait for the line to clear up. We cannot rely on UART * registers as none of them reflect the status of the RSR. @@ -63,7 +64,7 @@ static inline void serial_init(void) #endif if (BFIN_DEBUG_EARLY_SERIAL) { - int ucen = *pUART_GCTL & UCEN; + int ucen = bfin_read16(&pUART->gctl) & UCEN; serial_early_init(); /* If the UART is off, that means we need to program @@ -80,7 +81,7 @@ static inline void serial_deinit(void) #ifdef __ADSPBF54x__ if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { /* clear forced RTS rather than relying on auto RTS */ - bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL); + bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL); } #endif } @@ -94,9 +95,9 @@ static inline void serial_putc(char c) if (c == '\n') serial_putc('\r'); - *pUART_THR = c; + bfin_write16(&pUART->thr, c); - while (!(*pUART_LSR & TEMT)) + while (!(bfin_read16(&pUART->lsr) & TEMT)) continue; } @@ -213,6 +214,7 @@ static inline void serial_putc(char c) # define CONFIG_HAS_VR 1 #endif +#if CONFIG_MEM_SIZE #ifndef EBIU_RSTCTL /* Blackfin with SDRAM */ #ifndef CONFIG_EBIU_SDBCTL_VAL @@ -245,6 +247,7 @@ static inline void serial_putc(char c) # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE) #endif #endif +#endif /* Conflicting Column Address Widths Causes SDRAM Errors: * EB2CAW and EB3CAW must be the same @@ -255,28 +258,21 @@ static inline void serial_putc(char c) # endif #endif -BOOTROM_CALLED_FUNC_ATTR -void initcode(ADI_BOOT_DATA *bootstruct) +__attribute__((always_inline)) static inline void +program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) { - ADI_BOOT_DATA bootstruct_scratch; + serial_putc('a'); /* Save the clock pieces that are used in baud rate calculation */ - unsigned int sdivB, divB, vcoB; - serial_init(); if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { - sdivB = bfin_read_PLL_DIV() & 0xf; - vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f; - divB = serial_early_get_div(); + serial_putc('b'); + *sdivB = bfin_read_PLL_DIV() & 0xf; + *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f; + *divB = serial_early_get_div(); + serial_putc('c'); } - serial_putc('A'); - - /* If the bootstruct is NULL, then it's because we're loading - * dynamically and not via LDR (bootrom). So set the struct to - * some scratch space. - */ - if (!bootstruct) - bootstruct = &bootstruct_scratch; + serial_putc('d'); #ifdef CONFIG_HW_WATCHDOG # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE @@ -289,41 +285,69 @@ void initcode(ADI_BOOT_DATA *bootstruct) * timeout, so don't clobber that. */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { + serial_putc('e'); bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); bfin_write_WDOG_CTL(0); + serial_putc('f'); } #endif - serial_putc('B'); + serial_putc('g'); + + /* Blackfin bootroms use the SPI slow read opcode instead of the SPI + * fast read, so we need to slow down the SPI clock a lot more during + * boot. Once we switch over to u-boot's SPI flash driver, we'll + * increase the speed appropriately. + */ + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { + serial_putc('h'); + if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4) + bs->dFlags |= BFLAG_FASTREAD; + bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); + serial_putc('i'); + } + + serial_putc('j'); +} + +__attribute__((always_inline)) static inline bool +maybe_self_refresh(ADI_BOOT_DATA *bs) +{ + serial_putc('a'); + + if (!CONFIG_MEM_SIZE) + return false; /* If external memory is enabled, put it into self refresh first. */ - bool put_into_srfs = false; #ifdef EBIU_RSTCTL if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { + serial_putc('b'); bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ); - put_into_srfs = true; + return true; } #else if (bfin_read_EBIU_SDBCTL() & EBE) { + serial_putc('b'); bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); - put_into_srfs = true; + return true; } #endif - serial_putc('C'); + serial_putc('c'); - /* Blackfin bootroms use the SPI slow read opcode instead of the SPI - * fast read, so we need to slow down the SPI clock a lot more during - * boot. Once we switch over to u-boot's SPI flash driver, we'll - * increase the speed appropriately. - */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { - if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4) - bootstruct->dFlags |= BFLAG_FASTREAD; - bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); - } + return false; +} - serial_putc('D'); +__attribute__((always_inline)) static inline u16 +program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) +{ + u16 vr_ctl; + + serial_putc('a'); + + vr_ctl = bfin_read_VR_CTL(); + + serial_putc('b'); /* If we're entering self refresh, make sure it has happened. */ if (put_into_srfs) @@ -334,15 +358,14 @@ void initcode(ADI_BOOT_DATA *bootstruct) #endif continue; - serial_putc('E'); + serial_putc('c'); /* With newer bootroms, we use the helper function to set up * the memory controller. Older bootroms lacks such helpers * so we do it ourselves. */ - uint16_t vr_ctl = bfin_read_VR_CTL(); if (!ANOMALY_05000386) { - serial_putc('F'); + serial_putc('d'); /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ ADI_SYSCTRL_VALUES memory_settings; @@ -362,7 +385,9 @@ void initcode(ADI_BOOT_DATA *bootstruct) #if ANOMALY_05000432 bfin_write_SIC_IWR1(0); #endif + serial_putc('e'); bfrom_SysControl(actions, &memory_settings, NULL); + serial_putc('f'); #if ANOMALY_05000432 bfin_write_SIC_IWR1(-1); #endif @@ -370,8 +395,9 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_SICA_IWR0(-1); bfin_write_SICA_IWR1(-1); #endif + serial_putc('g'); } else { - serial_putc('G'); + serial_putc('h'); /* Disable all peripheral wakeups except for the PLL event. */ #ifdef SIC_IWR0 @@ -387,38 +413,40 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_SIC_IWR(1); #endif - serial_putc('H'); + serial_putc('i'); /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); - serial_putc('I'); + serial_putc('j'); /* Only reprogram when needed to avoid triggering unnecessary * PLL relock sequences. */ if (vr_ctl != CONFIG_VR_CTL_VAL) { - serial_putc('!'); + serial_putc('?'); bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); asm("idle;"); + serial_putc('!'); } - serial_putc('J'); + serial_putc('k'); bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); - serial_putc('K'); + serial_putc('l'); /* Only reprogram when needed to avoid triggering unnecessary * PLL relock sequences. */ if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { - serial_putc('!'); + serial_putc('?'); bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); asm("idle;"); + serial_putc('!'); } - serial_putc('L'); + serial_putc('m'); /* Restore all peripheral wakeups. */ #ifdef SIC_IWR0 @@ -433,9 +461,19 @@ void initcode(ADI_BOOT_DATA *bootstruct) #else bfin_write_SIC_IWR(-1); #endif + + serial_putc('n'); } - serial_putc('M'); + serial_putc('o'); + + return vr_ctl; +} + +__attribute__((always_inline)) static inline void +update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) +{ + serial_putc('a'); /* Since we've changed the SCLK above, we may need to update * the UART divisors (UART baud rates are based on SCLK). @@ -443,6 +481,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) * for dividing which means we'd generate a libgcc reference. */ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { + serial_putc('b'); unsigned int sdivR, vcoR; sdivR = bfin_read_PLL_DIV() & 0xf; vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; @@ -452,20 +491,38 @@ void initcode(ADI_BOOT_DATA *bootstruct) for (quotient = 0; dividend > 0; ++quotient) dividend -= divisor; serial_early_put_div(quotient - ANOMALY_05000230); + serial_putc('c'); } - serial_putc('N'); + serial_putc('d'); +} + +__attribute__((always_inline)) static inline void +program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) +{ + serial_putc('a'); + + if (!CONFIG_MEM_SIZE) + return; + + serial_putc('b'); /* Program the external memory controller before we come out of * self-refresh. This only works with our SDRAM controller. */ #ifndef EBIU_RSTCTL +# ifdef CONFIG_EBIU_SDRRC_VAL bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); +# endif +# ifdef CONFIG_EBIU_SDBCTL_VAL bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL); +# endif +# ifdef CONFIG_EBIU_SDGCTL_VAL bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL); +# endif #endif - serial_putc('O'); + serial_putc('c'); /* Now that we've reprogrammed, take things out of self refresh. */ if (put_into_srfs) @@ -475,16 +532,24 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS)); #endif - serial_putc('P'); + serial_putc('d'); /* Our DDR controller sucks and cannot be programmed while in * self-refresh. So we have to pull it out before programming. */ #ifdef EBIU_RSTCTL +# ifdef CONFIG_EBIU_RSTCTL_VAL bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL); +# endif +# ifdef CONFIG_EBIU_DDRCTL0_VAL bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL); +# endif +# ifdef CONFIG_EBIU_DDRCTL1_VAL bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL); +# endif +# ifdef CONFIG_EBIU_DDRCTL2_VAL bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL); +# endif # ifdef CONFIG_EBIU_DDRCTL3_VAL /* default is disable, so don't need to force this */ bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL); @@ -494,7 +559,18 @@ void initcode(ADI_BOOT_DATA *bootstruct) # endif #endif - serial_putc('Q'); + serial_putc('e'); +} + +__attribute__((always_inline)) static inline void +check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) +{ + serial_putc('a'); + + if (!CONFIG_MEM_SIZE) + return; + + serial_putc('b'); /* Are we coming out of hibernate (suspend to memory) ? * The memory layout is: @@ -508,7 +584,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) uint32_t *hibernate_magic = 0; __builtin_bfin_ssync(); /* make sure memory controller is done */ if (hibernate_magic[0] == 0xDEADBEEF) { - serial_putc('R'); + serial_putc('c'); bfin_write_EVT15(hibernate_magic[1]); bfin_write_IMASK(EVT_IVG15); __asm__ __volatile__ ( @@ -525,25 +601,80 @@ void initcode(ADI_BOOT_DATA *bootstruct) : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */) ); } + serial_putc('d'); } - serial_putc('S'); + serial_putc('e'); +} + +__attribute__((always_inline)) static inline void +program_async_controller(ADI_BOOT_DATA *bs) +{ + serial_putc('a'); /* Program the async banks controller. */ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); -#ifdef EBIU_MODE + serial_putc('b'); + /* Not all parts have these additional MMRs. */ +#ifdef EBIU_MODE +# ifdef CONFIG_EBIU_MBSCTL_VAL bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); +# endif +# ifdef CONFIG_EBIU_MODE_VAL bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); +# endif +# ifdef CONFIG_EBIU_FCTL_VAL bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); +# endif #endif - serial_putc('T'); + serial_putc('c'); +} + +BOOTROM_CALLED_FUNC_ATTR +void initcode(ADI_BOOT_DATA *bs) +{ + ADI_BOOT_DATA bootstruct_scratch; + + serial_init(); + + serial_putc('A'); + + /* If the bootstruct is NULL, then it's because we're loading + * dynamically and not via LDR (bootrom). So set the struct to + * some scratch space. + */ + if (!bs) + bs = &bootstruct_scratch; + + serial_putc('B'); + bool put_into_srfs = maybe_self_refresh(bs); + + serial_putc('C'); + uint sdivB, divB, vcoB; + program_early_devices(bs, &sdivB, &divB, &vcoB); + + serial_putc('D'); + u16 vr_ctl = program_clocks(bs, put_into_srfs); + + serial_putc('E'); + update_serial_clocks(bs, sdivB, divB, vcoB); + + serial_putc('F'); + program_memory_controller(bs, put_into_srfs); + + serial_putc('G'); + check_hibernation(bs, vr_ctl, put_into_srfs); + + serial_putc('H'); + program_async_controller(bs); #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 + serial_putc('I'); /* tell the bootrom where our entry point is */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE); diff --git a/cpu/blackfin/interrupt.S b/cpu/blackfin/interrupt.S index 71e0fc6708..8c7a262892 100644 --- a/cpu/blackfin/interrupt.S +++ b/cpu/blackfin/interrupt.S @@ -1,7 +1,7 @@ /* * interrupt.S - trampoline default exceptions/interrupts to C handlers * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2009 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -17,10 +17,19 @@ ENTRY(_trap) sp.l = LO(L1_SRAM_SCRATCH_END - 20); sp.h = HI(L1_SRAM_SCRATCH_END - 20); SAVE_ALL_SYS + r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ sp += -12; call _trap_c; sp += 12; + +#if ANOMALY_05000257 + R7 = LC0; + LC0 = R7; + R7 = LC1; + LC1 = R7; +#endif + RESTORE_ALL_SYS sp = CONFIG_BFIN_SCRATCH_REG; rtx; diff --git a/cpu/blackfin/interrupts.c b/cpu/blackfin/interrupts.c index 921bfe0c0f..54a67b4971 100644 --- a/cpu/blackfin/interrupts.c +++ b/cpu/blackfin/interrupts.c @@ -97,12 +97,12 @@ void __udelay(unsigned long usec) #define MAX_TIM_LOAD 0xFFFFFFFF int timer_init(void) { - *pTCNTL = 0x1; + bfin_write_TCNTL(0x1); CSYNC(); - *pTSCALE = 0x0; - *pTCOUNT = MAX_TIM_LOAD; - *pTPERIOD = MAX_TIM_LOAD; - *pTCNTL = 0x7; + bfin_write_TSCALE(0x0); + bfin_write_TCOUNT(MAX_TIM_LOAD); + bfin_write_TPERIOD(MAX_TIM_LOAD); + bfin_write_TCNTL(0x7); CSYNC(); timestamp = 0; @@ -130,7 +130,7 @@ ulong get_timer(ulong base) ulong milisec; /* Number of clocks elapsed */ - ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT)); + ulong clocks = (MAX_TIM_LOAD - bfin_read_TCOUNT()); /* * Find if the TCOUNT is reset diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 2abda186ec..901cb97a1c 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -44,10 +44,6 @@ #ifdef CONFIG_UART_CONSOLE -#if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0) -# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART -#endif - #include "serial.h" #ifdef CONFIG_DEBUG_SERIAL @@ -63,7 +59,7 @@ size_t cache_count; static uint16_t uart_lsr_save; static uint16_t uart_lsr_read(void) { - uint16_t lsr = *pUART_LSR; + uint16_t lsr = bfin_read16(&pUART->lsr); uart_lsr_save |= (lsr & (OE|PE|FE|BI)); return lsr | uart_lsr_save; } @@ -71,15 +67,21 @@ static uint16_t uart_lsr_read(void) static void uart_lsr_clear(void) { uart_lsr_save = 0; - *pUART_LSR |= -1; + bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); } #else /* When debugging is disabled, we only care about the DR bit, so if other * bits get set/cleared, we don't really care since we don't read them * anyways (and thus anomaly 05000099 is irrelevant). */ -static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; } -static inline void uart_lsr_clear(void) { *pUART_LSR = -1; } +static uint16_t uart_lsr_read(void) +{ + return bfin_read16(&pUART->lsr); +} +static void uart_lsr_clear(void) +{ + bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); +} #endif /* Symbol for our assembly to call. */ @@ -130,7 +132,7 @@ void serial_putc(const char c) continue; /* queue the character for transmission */ - *pUART_THR = c; + bfin_write16(&pUART->thr, c); SSYNC(); WATCHDOG_RESET(); @@ -151,7 +153,7 @@ int serial_getc(void) continue; /* grab the new byte */ - uart_rbr_val = *pUART_RBR; + uart_rbr_val = bfin_read16(&pUART->rbr); #ifdef CONFIG_DEBUG_SERIAL /* grab & clear the LSR */ @@ -165,8 +167,8 @@ int serial_getc(void) uint16_t dll, dlh; printf("\n[SERIAL ERROR]\n"); ACCESS_LATCH(); - dll = *pUART_DLL; - dlh = *pUART_DLH; + dll = bfin_read16(&pUART->dll); + dlh = bfin_read16(&pUART->dlh); ACCESS_PORT_IER(); printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh); do { diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index 6cbc564b53..5f9be8622d 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -24,71 +24,80 @@ # define BFIN_DEBUG_EARLY_SERIAL 0 #endif +#ifndef __ASSEMBLY__ + #define LOB(x) ((x) & 0xFF) #define HIB(x) (((x) >> 8) & 0xFF) +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m +struct bfin_mmr_serial { +#ifdef __ADSPBF54x__ + __BFP(dll); + __BFP(dlh); + __BFP(gctl); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + __BFP(ier_set); + __BFP(ier_clear); + __BFP(thr); + __BFP(rbr); +#else + union { + u16 dll; + u16 thr; + const u16 rbr; + }; + const u16 __spad0; + union { + u16 dlh; + u16 ier; + }; + const u16 __spad1; + const __BFP(iir); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + const u32 __spad2; + __BFP(gctl); +#endif +}; +#undef __BFP + #ifndef UART_LSR # if (CONFIG_UART_CONSOLE == 3) -# define pUART_DLH pUART3_DLH -# define pUART_DLL pUART3_DLL -# define pUART_GCTL pUART3_GCTL -# define pUART_IER pUART3_IER -# define pUART_IERC pUART3_IER_CLEAR -# define pUART_LCR pUART3_LCR -# define pUART_LSR pUART3_LSR -# define pUART_RBR pUART3_RBR -# define pUART_THR pUART3_THR -# define UART_THR UART3_THR -# define UART_LSR UART3_LSR +# define UART_BASE UART3_DLL # elif (CONFIG_UART_CONSOLE == 2) -# define pUART_DLH pUART2_DLH -# define pUART_DLL pUART2_DLL -# define pUART_GCTL pUART2_GCTL -# define pUART_IER pUART2_IER -# define pUART_IERC pUART2_IER_CLEAR -# define pUART_LCR pUART2_LCR -# define pUART_LSR pUART2_LSR -# define pUART_RBR pUART2_RBR -# define pUART_THR pUART2_THR -# define UART_THR UART2_THR -# define UART_LSR UART2_LSR +# define UART_BASE UART2_DLL # elif (CONFIG_UART_CONSOLE == 1) -# define pUART_DLH pUART1_DLH -# define pUART_DLL pUART1_DLL -# define pUART_GCTL pUART1_GCTL -# define pUART_IER pUART1_IER -# define pUART_IERC pUART1_IER_CLEAR -# define pUART_LCR pUART1_LCR -# define pUART_LSR pUART1_LSR -# define pUART_RBR pUART1_RBR -# define pUART_THR pUART1_THR -# define UART_THR UART1_THR -# define UART_LSR UART1_LSR +# define UART_BASE UART1_DLL # elif (CONFIG_UART_CONSOLE == 0) -# define pUART_DLH pUART0_DLH -# define pUART_DLL pUART0_DLL -# define pUART_GCTL pUART0_GCTL -# define pUART_IER pUART0_IER -# define pUART_IERC pUART0_IER_CLEAR -# define pUART_LCR pUART0_LCR -# define pUART_LSR pUART0_LSR -# define pUART_RBR pUART0_RBR -# define pUART_THR pUART0_THR -# define UART_THR UART0_THR -# define UART_LSR UART0_LSR +# define UART_BASE UART0_DLL +# endif +#else +# if CONFIG_UART_CONSOLE != 0 +# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART # endif +# define UART_BASE UART_DLL #endif - -#ifndef __ASSEMBLY__ +#define pUART ((volatile struct bfin_mmr_serial *)UART_BASE) #ifdef __ADSPBF54x__ # define ACCESS_LATCH() # define ACCESS_PORT_IER() -# define CLEAR_IER() (*pUART_IERC = 0) #else -# define ACCESS_LATCH() (*pUART_LCR |= DLAB) -# define ACCESS_PORT_IER() (*pUART_LCR &= ~DLAB) -# define CLEAR_IER() (*pUART_IER = 0) +# define ACCESS_LATCH() \ + bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB) +# define ACCESS_PORT_IER() \ + bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB) #endif __attribute__((always_inline)) @@ -142,10 +151,10 @@ static inline void serial_early_init(void) serial_do_portmux(); /* always enable UART -- avoids anomalies 05000309 and 05000350 */ - *pUART_GCTL = UCEN; + bfin_write16(&pUART->gctl, UCEN); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = WLS_8; + bfin_write16(&pUART->lcr, WLS_8); SSYNC(); } @@ -158,8 +167,8 @@ static inline void serial_early_put_div(uint16_t divisor) SSYNC(); /* Program the divisor to get the baud rate we want */ - *pUART_DLL = LOB(divisor); - *pUART_DLH = HIB(divisor); + bfin_write16(&pUART->dll, LOB(divisor)); + bfin_write16(&pUART->dlh, HIB(divisor)); SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ @@ -174,8 +183,8 @@ static inline uint16_t serial_early_get_div(void) ACCESS_LATCH(); SSYNC(); - uint8_t dll = *pUART_DLL; - uint8_t dlh = *pUART_DLH; + uint8_t dll = bfin_read16(&pUART->dll); + uint8_t dlh = bfin_read16(&pUART->dlh); uint16_t divisor = (dlh << 8) | dll; /* Clear DLAB in LCR to Access THR RBR IER */ diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S index 7cbd632205..7a3abba21c 100644 --- a/cpu/blackfin/start.S +++ b/cpu/blackfin/start.S @@ -95,6 +95,7 @@ ENTRY(_start) /* Save RETX so we can pass it while booting Linux */ r7 = RETX; +#if CONFIG_MEM_SIZE /* Figure out where we are currently executing so that we can decide * how to best reprogram and relocate things. We'll pass below: * R4: load address of _start @@ -131,6 +132,9 @@ ENTRY(_start) r3.h = 0x2000; cc = r5 < r3 (iu); if cc jump .Ldma_and_reprogram; +#else + r6 = 1 (x); /* fake loaded_from_ldr = 1 */ +#endif r0 = 0 (x); /* set bootstruct to NULL */ call _initcode; jump .Lprogrammed; @@ -139,11 +143,10 @@ ENTRY(_start) .Ldma_and_reprogram: r0.l = LO(L1_INST_SRAM); r0.h = HI(L1_INST_SRAM); - r1.l = __initcode_start; - r1.h = __initcode_start; - r2.l = __initcode_end; - r2.h = __initcode_end; - r2 = r2 - r1; /* convert r2 into length of initcode */ + r1.l = __initcode_lma; + r1.h = __initcode_lma; + r2.l = __initcode_len; + r2.h = __initcode_len; r1 = r1 - r4; /* convert r1 from load address of initcode ... */ r1 = r1 + r5; /* ... to current (not load) address of initcode */ p3 = r0; @@ -155,6 +158,7 @@ ENTRY(_start) .Lprogrammed: serial_early_set_baud +#if CONFIG_MEM_SIZE /* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded * monitor location in the end of RAM. We know that memcpy() only * uses registers, so it is safe to call here. Note that this only @@ -167,18 +171,18 @@ ENTRY(_start) r2.l = LO(CONFIG_SYS_MONITOR_LEN); r2.h = HI(CONFIG_SYS_MONITOR_LEN); call _memcpy_ASM; +#endif /* Initialize BSS section ... we know that memset() does not * use the BSS, so it is safe to call here. The bootrom LDR * takes care of clearing things for us. */ serial_early_puts("Zero BSS"); - r0.l = __bss_start; - r0.h = __bss_start; + r0.l = __bss_vma; + r0.h = __bss_vma; r1 = 0 (x); - r2.l = __bss_end; - r2.h = __bss_end; - r2 = r2 - r0; + r2.l = __bss_len; + r2.h = __bss_len; call _memset; .Lnorelocate: diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c index 7e7c74ce47..becc36e6a9 100644 --- a/cpu/blackfin/traps.c +++ b/cpu/blackfin/traps.c @@ -100,6 +100,14 @@ void trap_c(struct pt_regs *regs) uint32_t new_cplb_addr = 0, new_cplb_data = 0; static size_t last_evicted; size_t i; + unsigned long tflags; + + /* + * Keep the trace buffer so that a miss here points people + * to the right place (their code). Crashes here rarely + * happen. If they do, only the Blackfin maintainer cares. + */ + trace_buffer_save(tflags); new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1); @@ -156,6 +164,7 @@ void trap_c(struct pt_regs *regs) for (i = 0; i < 16; ++i) debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++); + trace_buffer_restore(tflags); break; } diff --git a/cpu/blackfin/watchdog.c b/cpu/blackfin/watchdog.c index b47c6b688d..1886bda0ae 100644 --- a/cpu/blackfin/watchdog.c +++ b/cpu/blackfin/watchdog.c @@ -1,7 +1,7 @@ /* * watchdog.c - driver for Blackfin on-chip watchdog * - * Copyright (c) 2007-2008 Analog Devices Inc. + * Copyright (c) 2007-2009 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -10,7 +10,6 @@ #include <watchdog.h> #include <asm/blackfin.h> -#ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void) { bfin_write_WDOG_STAT(0); @@ -22,4 +21,3 @@ void hw_watchdog_init(void) hw_watchdog_reset(); bfin_write_WDOG_CTL(0x0); } -#endif diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 16c9695ba8..f9d560a71b 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -1,7 +1,7 @@ /* * Driver for Blackfin on-chip SDH controller * - * Copyright (c) 2008 Analog Devices Inc. + * Copyright (c) 2008-2009 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -18,20 +18,6 @@ #include <asm/mach-common/bits/sdh.h> #include <asm/mach-common/bits/dma.h> -#include "bfin_sdh.h" - -/* SD_CLK frequency must be less than 400k in identification mode */ -#ifndef CONFIG_SYS_MMC_CLK_ID -#define CONFIG_SYS_MMC_CLK_ID 200000 -#endif -/* SD_CLK for normal working */ -#ifndef CONFIG_SYS_MMC_CLK_OP -#define CONFIG_SYS_MMC_CLK_OP 25000000 -#endif -/* support 3.2-3.3V and 3.3-3.4V */ -#define CONFIG_SYS_MMC_OP_COND 0x00300000 -#define MMC_DEFAULT_RCA 1 - #if defined(__ADSPBF51x__) # define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL # define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL @@ -64,61 +50,17 @@ # error no support for this proc yet #endif -static unsigned int mmc_rca; -static int mmc_card_is_sd; -static block_dev_desc_t mmc_blkdev; -struct mmc_cid cid; -static __u32 csd[4]; - -#define get_bits(resp, start, size) \ - ({ \ - const int __size = size; \ - const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \ - const int32_t __off = 3 - ((start) / 32); \ - const int32_t __shft = (start) & 31; \ - uint32_t __res; \ - \ - __res = resp[__off] >> __shft; \ - if (__size + __shft > 32) \ - __res |= resp[__off-1] << ((32 - __shft) % 32); \ - __res & __mask; \ - }) - - -block_dev_desc_t *mmc_get_dev(int dev) -{ - return &mmc_blkdev; -} - -static void mci_set_clk(unsigned long clk) -{ - unsigned long sys_clk; - unsigned long clk_div; - __u16 clk_ctl = 0; - - /* setting SD_CLK */ - sys_clk = get_sclk(); - bfin_write_SDH_CLK_CTL(0); - if (sys_clk % (2 * clk) == 0) - clk_div = sys_clk / (2 * clk) - 1; - else - clk_div = sys_clk / (2 * clk); - - if (clk_div > 0xff) - clk_div = 0xff; - clk_ctl |= (clk_div & 0xff); - clk_ctl |= CLK_E; - bfin_write_SDH_CLK_CTL(clk_ctl); -} - static int -mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) +sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) { unsigned int sdh_cmd; unsigned int status; + int cmd = mmc_cmd->cmdidx; + int flags = mmc_cmd->resp_type; + int arg = mmc_cmd->cmdarg; int ret = 0; sdh_cmd = 0; - unsigned long *response = resp; + sdh_cmd |= cmd; if (flags & MMC_RSP_PRESENT) @@ -138,336 +80,137 @@ mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) CMD_CRC_FAIL))); if (flags & MMC_RSP_PRESENT) { - response[0] = bfin_read_SDH_RESPONSE0(); + mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0(); if (flags & MMC_RSP_136) { - response[1] = bfin_read_SDH_RESPONSE1(); - response[2] = bfin_read_SDH_RESPONSE2(); - response[3] = bfin_read_SDH_RESPONSE3(); + mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1(); + mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2(); + mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3(); } } - if (status & CMD_TIME_OUT) { - printf("CMD%d timeout\n", (int)cmd); - ret |= -ETIMEDOUT; - } else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) { - printf("CMD%d CRC failure\n", (int)cmd); - ret |= -EILSEQ; - } + if (status & CMD_TIME_OUT) + ret |= TIMEOUT; + else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) + ret |= COMM_ERR; + bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT); return ret; } -static int -mmc_acmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) +/* set data for single block transfer */ +static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) { - unsigned long aresp[4]; + u16 data_ctl = 0; + u16 dma_cfg = 0; int ret = 0; - ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, - MMC_RSP_PRESENT); - if (ret) - return ret; - - if ((aresp[0] & (ILLEGAL_COMMAND | APP_CMD)) != APP_CMD) - return -ENODEV; - ret = mmc_cmd(cmd, arg, resp, flags); - return ret; -} - -static unsigned long -mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, void *buffer) -{ - int ret, i; - unsigned long resp[4]; - unsigned long card_status; - __u8 *buf = buffer; - __u32 status; - __u16 data_ctl = 0; - __u16 dma_cfg = 0; - - if (blkcnt == 0) - return 0; - debug("mmc_bread: dev %d, start %d, blkcnt %d\n", dev, start, blkcnt); - /* Force to use 512-byte block,because a lot of code depends on this */ - data_ctl |= 9 << 4; + /* Don't support write yet. */ + if (data->flags & MMC_DATA_WRITE) + return UNUSABLE_ERR; + data_ctl |= ((ffs(data->blocksize) - 1) << 4); data_ctl |= DTX_DIR; bfin_write_SDH_DATA_CTL(data_ctl); - dma_cfg |= WDSIZE_32 | RESTART | WNR | DMAEN; - - /* FIXME later */ - bfin_write_SDH_DATA_TIMER(0xFFFFFFFF); - for (i = 0; i < blkcnt; ++i, ++start) { - blackfin_dcache_flush_invalidate_range(buf + i * mmc_blkdev.blksz, - buf + (i + 1) * mmc_blkdev.blksz); - bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz); - bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4); - bfin_write_DMA_X_MODIFY(4); - bfin_write_DMA_CONFIG(dma_cfg); - bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz); - /* Put the device into Transfer state */ - ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SELECT_CARD failed\n"); - goto out; - } - /* Set block length */ - ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SET_BLOCKLEN failed\n"); - goto out; - } - ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, - start * mmc_blkdev.blksz, resp, - MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_READ_SINGLE_BLOCK failed\n"); - goto out; - } - bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); + dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN; - do { - udelay(1); - status = bfin_read_SDH_STATUS(); - } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN))); - - if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)) { - bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT | \ - DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT); - goto read_error; - } else { - bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT); - mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0); - } - } - out: + bfin_write_SDH_DATA_TIMER(0xFFFF); - return i; + blackfin_dcache_flush_invalidate_range(data->dest, + data->dest + data->blocksize); + /* configure DMA */ + bfin_write_DMA_START_ADDR(data->dest); + bfin_write_DMA_X_COUNT(data->blocksize / 4); + bfin_write_DMA_X_MODIFY(4); + bfin_write_DMA_CONFIG(dma_cfg); + bfin_write_SDH_DATA_LGTH(data->blocksize); + /* kick off transfer */ + bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); - read_error: - mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1); - printf("mmc: bread failed, status = %08x, card status = %08lx\n", - status, card_status); - goto out; + return ret; } -static unsigned long -mmc_bwrite(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer) + +static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) { - int ret, i = 0; - unsigned long resp[4]; - unsigned long card_status; - const __u8 *buf = buffer; - __u32 status; - __u16 data_ctl = 0; - __u16 dma_cfg = 0; - - if (blkcnt == 0) - return 0; - - debug("mmc_bwrite: dev %d, start %lx, blkcnt %lx\n", - dev, start, blkcnt); - /* Force to use 512-byte block,because a lot of code depends on this */ - data_ctl |= 9 << 4; - data_ctl &= ~DTX_DIR; - bfin_write_SDH_DATA_CTL(data_ctl); - dma_cfg |= WDSIZE_32 | RESTART | DMAEN; - /* FIXME later */ - bfin_write_SDH_DATA_TIMER(0xFFFFFFFF); - for (i = 0; i < blkcnt; ++i, ++start) { - bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz); - bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4); - bfin_write_DMA_X_MODIFY(4); - bfin_write_DMA_CONFIG(dma_cfg); - bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz); - - /* Put the device into Transfer state */ - ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SELECT_CARD failed\n"); - goto out; - } - /* Set block length */ - ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SET_BLOCKLEN failed\n"); - goto out; - } - ret = mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, - start * mmc_blkdev.blksz, resp, - MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_WRITE_SINGLE_BLOCK failed\n"); - goto out; - } - bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); + u32 status; + int ret = 0; + ret = sdh_send_cmd(mmc, cmd); + if (ret) { + printf("sending CMD%d failed\n", cmd->cmdidx); + return ret; + } + if (data) { + ret = sdh_setup_data(mmc, data); do { udelay(1); status = bfin_read_SDH_STATUS(); - } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN))); + } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN))); - if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN)) { - bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT | - DAT_CRC_FAIL_STAT | TX_UNDERRUN_STAT); - goto write_error; - } else { + if (status & DAT_TIME_OUT) { + bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT); + ret |= TIMEOUT; + } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) { + bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT); + ret |= COMM_ERR; + } else bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT); - mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0); + + if (ret) { + printf("tranfering data failed\n"); + return ret; } } - out: - return i; - - write_error: - mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1); - printf("mmc: bwrite failed, status = %08x, card status = %08lx\n", - status, card_status); - goto out; -} - -static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) -{ - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = resp[2] >> 24; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 16; - cid->psn = (resp[2] << 16) | (resp[3] >> 16); - cid->mdt = resp[3] >> 8; -} - -static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) -{ - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = 0; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 24; - cid->psn = (resp[2] << 8) | (resp[3] >> 24); - cid->mdt = (resp[3] >> 8) & 0x0fff; -} - -static void mmc_dump_cid(const struct mmc_cid *cid) -{ - printf("CID information:\n"); - printf("Manufacturer ID: %02X\n", cid->mid); - printf("OEM/Application ID: %04X\n", cid->oid); - printf("Product name: %s\n", cid->pnm); - printf("Product Revision: %u.%u\n", - cid->prv >> 4, cid->prv & 0x0f); - printf("Product Serial Number: %lu\n", cid->psn); - printf("Manufacturing Date: %02u/%02u\n", - cid->mdt >> 4, cid->mdt & 0x0f); -} - -static void mmc_dump_csd(__u32 *csd) -{ - printf("CSD information:\n"); - printf("CSD structure version: 1.%u\n", get_bits(csd, 126, 2)); - printf("Card command classes: %03x\n", get_bits(csd, 84, 12)); - printf("Max trans speed: %s\n", (get_bits(csd, 96, 8) == 0x32) ? "25MHz" : "50MHz"); - printf("Read block length: %d\n", 1 << get_bits(csd, 80, 4)); - printf("Write block length: %u\n", 1 << get_bits(csd, 22, 4)); - printf("Card capacity: %u bytes\n", - (get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2)) * - (1 << get_bits(csd, 80, 4))); - putc('\n'); + return 0; } -static int mmc_idle_cards(void) +static void sdh_set_clk(unsigned long clk) { - int ret = 0; - - /* Reset all cards */ - ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); - if (ret) - return ret; - udelay(500); - return mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); + unsigned long sys_clk; + unsigned long clk_div; + u16 clk_ctl = 0; + + clk_ctl = bfin_read_SDH_CLK_CTL(); + if (clk) { + /* setting SD_CLK */ + sys_clk = get_sclk(); + bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); + if (sys_clk % (2 * clk) == 0) + clk_div = sys_clk / (2 * clk) - 1; + else + clk_div = sys_clk / (2 * clk); + + if (clk_div > 0xff) + clk_div = 0xff; + clk_ctl |= (clk_div & 0xff); + clk_ctl |= CLK_E; + bfin_write_SDH_CLK_CTL(clk_ctl); + } else + bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); } -static int sd_init_card(struct mmc_cid *cid, int verbose) +static void bfin_sdh_set_ios(struct mmc *mmc) { - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; ++i) { - ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, - resp, MMC_RSP_R3); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; + u16 cfg = 0; + u16 clk_ctl = 0; + + if (mmc->bus_width == 4) { + cfg = bfin_read_SDH_CFG(); + cfg &= ~0x80; + cfg |= 0x40; + bfin_write_SDH_CFG(cfg); + clk_ctl |= WIDE_BUS; } - if (ret) - return ret; - - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2); - if (ret) - return ret; - sd_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); - - /* Get RCA of the card that responded */ - ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, MMC_RSP_R6); - if (ret) - return ret; - - mmc_rca = (resp[0] >> 16) & 0xffff; - if (verbose) - printf("SD Card detected (RCA %u)\n", mmc_rca); - mmc_card_is_sd = 1; - return 0; + bfin_write_SDH_CLK_CTL(clk_ctl); + sdh_set_clk(mmc->clock); } -static int mmc_init_card(struct mmc_cid *cid, int verbose) +static int bfin_sdh_init(struct mmc *mmc) { - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; ++i) { - ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp, - MMC_RSP_R3); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; - } - if (ret) - return ret; - /* Get CID of all cards. FIXME: Support more than one card */ - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2); - if (ret) - return ret; - mmc_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); - - /* Set Relative Address of the card that responded */ - ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, - MMC_RSP_R1); - return ret; -} - -int mmc_legacy_init(int verbose) -{ - __u16 pwr_ctl = 0; - int ret; - unsigned int max_blksz; - /* Initialize sdh controller */ + u16 pwr_ctl = 0; +/* Initialize sdh controller */ #if defined(__ADSPBF54x__) bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1); bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00); @@ -481,56 +224,34 @@ int mmc_legacy_init(int verbose) bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN); /* Disable card detect pin */ bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60); - mci_set_clk(CONFIG_SYS_MMC_CLK_ID); - /* setting power control */ + pwr_ctl |= ROD_CTL; pwr_ctl |= PWR_ON; bfin_write_SDH_PWR_CTL(pwr_ctl); - mmc_card_is_sd = 0; - ret = sd_init_card(&cid, verbose); - if (ret) { - mmc_rca = MMC_DEFAULT_RCA; - ret = mmc_init_card(&cid, verbose); - } - if (ret) - return ret; - /* Get CSD from the card */ - ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, csd, MMC_RSP_R2); - if (ret) - return ret; - if (verbose) - mmc_dump_csd(csd); - /* Initialize the blockdev structure */ - mmc_blkdev.if_type = IF_TYPE_MMC; - mmc_blkdev.part_type = PART_TYPE_DOS; - mmc_blkdev.block_read = mmc_bread; - mmc_blkdev.block_write = mmc_bwrite; - sprintf(mmc_blkdev.vendor, - "Man %02x%04x Snr %08lx", - cid.mid, cid.oid, cid.psn); - strncpy(mmc_blkdev.product, cid.pnm, - sizeof(mmc_blkdev.product)); - sprintf(mmc_blkdev.revision, "%x %x", - cid.prv >> 4, cid.prv & 0x0f); - - max_blksz = 1 << get_bits(csd, 80, 4); - /* - * If we can't use 512 byte blocks, refuse to deal with the - * card. Tons of code elsewhere seems to depend on this. - */ - if (max_blksz < 512 || (max_blksz > 512 && !get_bits(csd, 79, 1))) { - printf("Card does not support 512 byte reads, aborting.\n"); - return -ENODEV; - } - - mmc_blkdev.blksz = 512; - mmc_blkdev.lba = (get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2)); - mci_set_clk(CONFIG_SYS_MMC_CLK_OP); - init_part(&mmc_blkdev); return 0; } -int mmc2info(ulong addr) + +int bfin_mmc_init(bd_t *bis) { + struct mmc *mmc = NULL; + + mmc = malloc(sizeof(struct mmc)); + + if (!mmc) + return -ENOMEM; + sprintf(mmc->name, "Blackfin SDH"); + mmc->send_cmd = bfin_sdh_request; + mmc->set_ios = bfin_sdh_set_ios; + mmc->init = bfin_sdh_init; + mmc->host_caps = MMC_MODE_4BIT; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->f_max = get_sclk(); + mmc->f_min = mmc->f_max >> 9; + mmc->block_dev.part_type = PART_TYPE_DOS; + + mmc_register(mmc); + return 0; } diff --git a/drivers/mmc/bfin_sdh.h b/drivers/mmc/bfin_sdh.h deleted file mode 100644 index 793ec3061b..0000000000 --- a/drivers/mmc/bfin_sdh.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2008 Analog Device Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __BLACKFIN_SDH_H__ -#define __BLACKFIN_SDH_H__ - -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ - -#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ -#define MMC_CMD_AC (0 << 5) -#define MMC_CMD_ADTC (1 << 5) -#define MMC_CMD_BC (2 << 5) -#define MMC_CMD_BCR (3 << 5) - -#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ -#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ -#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ -#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ - -/* - * These are the native response types, and correspond to valid bit - * patterns of the above flags. One additional valid pattern - * is all zeros, which means we don't expect a response. - */ -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R4 (MMC_RSP_PRESENT) -#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define ILLEGAL_COMMAND (1 << 22) -#define APP_CMD (1 << 5) - -#endif diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index 2a72f99b24..f28d42b489 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -85,6 +85,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct bfin_spi_slave *bss; + ulong sclk; u32 mmr_base; u32 baud; @@ -105,7 +106,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, default: return NULL; } - baud = get_sclk() / (2 * max_hz); + sclk = get_sclk(); + baud = sclk / (2 * max_hz); + /* baud should be rounded up */ + if (sclk % (2 * max_hz)) + baud += 1; if (baud < 2) baud = 2; else if (baud > (u16)-1) @@ -314,6 +319,10 @@ void spi_release_bus(struct spi_slave *slave) SSYNC(); } +#ifndef CONFIG_BFIN_SPI_IDLE_VAL +# define CONFIG_BFIN_SPI_IDLE_VAL 0xff +#endif + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -340,7 +349,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* todo: take advantage of hardware fifos and setup RX dma */ while (bytes--) { - u8 value = (tx ? *tx++ : 0); + u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL); debug("%s: tx:%x ", __func__, value); write_SPI_TDBR(bss, value); SSYNC(); diff --git a/include/asm-blackfin/bfin_logo_rgb565_230x230.h b/include/asm-blackfin/bfin_logo_rgb565_230x230.h new file mode 100644 index 0000000000..c5b0be96f1 --- /dev/null +++ b/include/asm-blackfin/bfin_logo_rgb565_230x230.h @@ -0,0 +1,1242 @@ +/* + * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi + * + * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y) + * + * Where: 'screen' is the pointer to the frame buffer + * 'width' is the screen width + * 'x' is the horizontal position + * 'y' is the vertical position + */ + +#define EASYLOGO_ENABLE_GZIP 19303 + +static unsigned char EASYLOGO_DECOMP_BUFFER[105800]; + +#include <video_easylogo.h> + +#define DEF_BFIN_LOGO_WIDTH 230 +#define DEF_BFIN_LOGO_HEIGHT 230 +#define DEF_BFIN_LOGO_PIXELS 52900 +#define DEF_BFIN_LOGO_BPP 16 +#define DEF_BFIN_LOGO_PIXEL_SIZE 2 +#define DEF_BFIN_LOGO_SIZE 105800 + +unsigned char DEF_BFIN_LOGO_DATA[] = { + 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 0x7f, 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0x08, + 0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2, + 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8, + 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c, + 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00 +}; + +fastimage_t bfin_logo = { + DEF_BFIN_LOGO_DATA, + DEF_BFIN_LOGO_WIDTH, + DEF_BFIN_LOGO_HEIGHT, + DEF_BFIN_LOGO_BPP, + DEF_BFIN_LOGO_PIXEL_SIZE, + DEF_BFIN_LOGO_SIZE +}; diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h index 8ec7928945..3fd34b33fe 100644 --- a/include/asm-blackfin/blackfin_local.h +++ b/include/asm-blackfin/blackfin_local.h @@ -25,6 +25,8 @@ #ifndef __BLACKFIN_LOCAL_H__ #define __BLACKFIN_LOCAL_H__ +#include <asm/mem_map.h> + #define LO(con32) ((con32) & 0xFFFF) #define lo(con32) ((con32) & 0xFFFF) #define HI(con32) (((con32) >> 16) & 0xFFFF) @@ -59,7 +61,7 @@ extern u_long get_vco(void); extern u_long get_cclk(void); extern u_long get_sclk(void); -# define bfin_revid() (*pCHIPID >> 28) +# define bfin_revid() (bfin_read_CHIPID() >> 28) extern bool bfin_os_log_check(void); extern void bfin_os_log_dump(void); diff --git a/include/asm-blackfin/config-pre.h b/include/asm-blackfin/config-pre.h index b1d3a946d3..1170a2a904 100644 --- a/include/asm-blackfin/config-pre.h +++ b/include/asm-blackfin/config-pre.h @@ -71,4 +71,7 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) # define BFIN_BOOT_SPI_SSEL 1 #endif +/* We rarely use interrupts, so favor throughput over latency */ +#define CONFIG_BFIN_INS_LOWOVERHEAD + #endif diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 327843d0b6..0ae838abea 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -79,6 +79,11 @@ # define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL #endif +/* We need envcrc to embed the env into LDRs */ +#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR +# define CONFIG_BUILD_ENVCRC +#endif + /* Default/common Blackfin memory layout */ #ifndef CONFIG_SYS_SDRAM_BASE # define CONFIG_SYS_SDRAM_BASE 0 @@ -87,7 +92,11 @@ # define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) #endif #ifndef CONFIG_SYS_MONITOR_BASE -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) +# if CONFIG_SYS_MAX_RAM_SIZE +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) +# else +# define CONFIG_SYS_MONITOR_BASE 0 +# endif #endif #ifndef CONFIG_SYS_MALLOC_BASE # define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) @@ -109,7 +118,8 @@ #endif /* Check to make sure everything fits in external RAM */ -#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) +#if CONFIG_SYS_MAX_RAM_SIZE && \ + ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) # error Memory Map does not fit into configuration #endif diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index b78b04cd6b..c7099e6dac 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -28,6 +28,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <asm/u-boot.h> + /* * The following data structure is placed in some memory wich is * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 6806494983..75244a0731 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -1,25 +1,9 @@ /* * U-boot - io.h IO routines * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright 2004-2009 Analog Devices Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #ifndef _BLACKFIN_IO_H @@ -29,17 +13,13 @@ #include <asm/blackfin.h> +#define __iomem + static inline void sync(void) { SSYNC(); } -/* function prototypes for CF support */ -extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); -extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); -extern unsigned char cf_inb(volatile unsigned char *addr); -extern void cf_outb(unsigned char val, volatile unsigned char *addr); - /* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching @@ -76,114 +56,172 @@ static inline phys_addr_t virt_to_phys(void * vaddr) * * readX/writeX() are used to access memory mapped devices. On some * architectures the memory mapped IO stuff needs to be accessed - * differently. On the m68k architecture, we just read/write the + * differently. On the bfin architecture, we just read/write the * memory location directly. */ - #ifndef __ASSEMBLY__ -static inline unsigned char readb(const volatile void *addr) +static inline unsigned char readb(const volatile void __iomem *addr) { unsigned int val; int tmp; - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = b [%2] (z);\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); + __asm__ __volatile__ ( + "cli %1;" + "NOP; NOP; SSYNC;" + "%0 = b [%2] (z);" + "sti %1;" + : "=d"(val), "=d"(tmp) + : "a"(addr) + ); return (unsigned char) val; } -static inline unsigned short readw(const volatile void *addr) +static inline unsigned short readw(const volatile void __iomem *addr) { unsigned int val; int tmp; - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = w [%2] (z);\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); + __asm__ __volatile__ ( + "cli %1;" + "NOP; NOP; SSYNC;" + "%0 = w [%2] (z);" + "sti %1;" + : "=d"(val), "=d"(tmp) + : "a"(addr) + ); return (unsigned short) val; } -static inline unsigned int readl(const volatile void *addr) +static inline unsigned int readl(const volatile void __iomem *addr) { unsigned int val; int tmp; - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = [%2];\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); + __asm__ __volatile__ ( + "cli %1;" + "NOP; NOP; SSYNC;" + "%0 = [%2];" + "sti %1;" + : "=d"(val), "=d"(tmp) + : "a"(addr) + ); + return val; } -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - #endif /* __ASSEMBLY__ */ #define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) #define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) #define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel - #define memset_io(a, b, c) memset((void *)(a), (b), (c)) #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) -#define inb(addr) cf_inb((volatile unsigned char *)(addr)) -#define outb(x, addr) cf_outb((unsigned char)(x), (volatile unsigned char *)(addr)) - -#define insw(port, addr, count) cf_insw((unsigned short *)addr, (unsigned short *)(port), (count)) +/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ +#define __io(port) ((void *)(unsigned long)(port)) + +#define inb(port) readb(__io(port)) +#define inw(port) readw(__io(port)) +#define inl(port) readl(__io(port)) +#define outb(x, port) writeb(x, __io(port)) +#define outw(x, port) writew(x, __io(port)) +#define outl(x, port) writel(x, __io(port)) + +#define inb_p(port) inb(__io(port)) +#define inw_p(port) inw(__io(port)) +#define inl_p(port) inl(__io(port)) +#define outb_p(x, port) outb(x, __io(port)) +#define outw_p(x, port) outw(x, __io(port)) +#define outl_p(x, port) outl(x, __io(port)) + +#define ioread8_rep(a, d, c) readsb(a, d, c) +#define ioread16_rep(a, d, c) readsw(a, d, c) +#define ioread32_rep(a, d, c) readsl(a, d, c) +#define iowrite8_rep(a, s, c) writesb(a, s, c) +#define iowrite16_rep(a, s, c) writesw(a, s, c) +#define iowrite32_rep(a, s, c) writesl(a, s, c) + +#define ioread8(x) readb(x) +#define ioread16(x) readw(x) +#define ioread32(x) readl(x) +#define iowrite8(val, x) writeb(val, x) +#define iowrite16(val, x) writew(val, x) +#define iowrite32(val, x) writel(val, x) + +#define mmiowb() wmb() -#define outsw(port, addr, count) cf_outsw((unsigned short *)(port), (unsigned short *)addr, (count)) +#ifndef __ASSEMBLY__ -#define IO_SPACE_LIMIT 0xffff +extern void outsb(unsigned long port, const void *addr, unsigned long count); +extern void outsw(unsigned long port, const void *addr, unsigned long count); +extern void outsw_8(unsigned long port, const void *addr, unsigned long count); +extern void outsl(unsigned long port, const void *addr, unsigned long count); -/* Values for nocacheflag and cmode */ -#define IOMAP_FULL_CACHING 0 -#define IOMAP_NOCACHE_SER 1 -#define IOMAP_NOCACHE_NONSER 2 -#define IOMAP_WRITETHROUGH 3 +extern void insb(unsigned long port, void *addr, unsigned long count); +extern void insw(unsigned long port, void *addr, unsigned long count); +extern void insw_8(unsigned long port, void *addr, unsigned long count); +extern void insl(unsigned long port, void *addr, unsigned long count); +extern void insl_16(unsigned long port, void *addr, unsigned long count); -extern void *__ioremap(unsigned long physaddr, unsigned long size, - int cacheflag); -extern void __iounmap(void *addr, unsigned long size); +static inline void readsl(const void __iomem *addr, void *buf, int len) +{ + insl((unsigned long)addr, buf, len); +} -extern inline void *ioremap(unsigned long physaddr, unsigned long size) +static inline void readsw(const void __iomem *addr, void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); + insw((unsigned long)addr, buf, len); } -extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) + +static inline void readsb(const void __iomem *addr, void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); + insb((unsigned long)addr, buf, len); } -extern inline void *ioremap_writethrough(unsigned long physaddr, - unsigned long size) + +static inline void writesl(const void __iomem *addr, const void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); + outsl((unsigned long)addr, buf, len); } -extern inline void *ioremap_fullcache(unsigned long physaddr, - unsigned long size) + +static inline void writesw(const void __iomem *addr, const void *buf, int len) { - return __ioremap(physaddr, size, IOMAP_FULL_CACHING); + outsw((unsigned long)addr, buf, len); } -extern void iounmap(void *addr); +static inline void writesb(const void __iomem *addr, const void *buf, int len) +{ + outsb((unsigned long)addr, buf, len); +} -extern void blkfin_inv_cache_all(void); -#define dma_cache_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) -#define dma_cache_wback(_start, _size) do { } while (0) -#define dma_cache_wback_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) +#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE) +/* This hack for CF/IDE needs to be addressed at some point */ +extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); +extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); +extern unsigned char cf_inb(volatile unsigned char *addr); +extern void cf_outb(unsigned char val, volatile unsigned char *addr); +#undef inb +#undef outb +#undef insw +#undef outsw +#define inb(addr) cf_inb((void *)(addr)) +#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr)) +#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt) +#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt) +#endif #endif + +#endif /* __KERNEL__ */ + #endif diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h index 44143ba893..bc05029aac 100644 --- a/include/asm-blackfin/mach-bf527/BF522_def.h +++ b/include/asm-blackfin/mach-bf527/BF522_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF522_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/include/asm-blackfin/mach-bf527/BF523_def.h index 02675a9526..c27fd646b5 100644 --- a/include/asm-blackfin/mach-bf527/BF523_def.h +++ b/include/asm-blackfin/mach-bf527/BF523_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF523_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF524_def.h b/include/asm-blackfin/mach-bf527/BF524_def.h index 10793e8edf..bd6aa8fdb6 100644 --- a/include/asm-blackfin/mach-bf527/BF524_def.h +++ b/include/asm-blackfin/mach-bf527/BF524_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF524_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF525_def.h b/include/asm-blackfin/mach-bf527/BF525_def.h index c4c2f2f098..5e88b3b468 100644 --- a/include/asm-blackfin/mach-bf527/BF525_def.h +++ b/include/asm-blackfin/mach-bf527/BF525_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF525_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF526_def.h b/include/asm-blackfin/mach-bf527/BF526_def.h index 04db6c7879..2644abf197 100644 --- a/include/asm-blackfin/mach-bf527/BF526_def.h +++ b/include/asm-blackfin/mach-bf527/BF526_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF526_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF527_def.h b/include/asm-blackfin/mach-bf527/BF527_def.h index c1e1aab2c4..c46c2b0ee8 100644 --- a/include/asm-blackfin/mach-bf527/BF527_def.h +++ b/include/asm-blackfin/mach-bf527/BF527_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF527_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/def_local.h b/include/asm-blackfin/mach-bf527/def_local.h index 14c111f712..81eca83bce 100644 --- a/include/asm-blackfin/mach-bf527/def_local.h +++ b/include/asm-blackfin/mach-bf527/def_local.h @@ -1 +1,2 @@ +#include "mem_map.h" #include "ports.h" diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h new file mode 100644 index 0000000000..8386b4b266 --- /dev/null +++ b/include/asm-blackfin/mach-bf527/mem_map.h @@ -0,0 +1,21 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BF52X_MEM_MAP_H__ +#define __BF52X_MEM_MAP_H__ + +#define L1_DATA_A_SRAM (0xFF800000) +#define L1_DATA_A_SRAM_SIZE (0x4000) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM (0xFF900000) +#define L1_DATA_B_SRAM_SIZE (0x4000) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM (0xFFA00000) +#define L1_INST_SRAM_SIZE (0xC000) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h index 40fe555c8a..1324a136fd 100644 --- a/include/asm-blackfin/mach-bf548/BF542_def.h +++ b/include/asm-blackfin/mach-bf548/BF542_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF542_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h index 042e2ac82f..aef6e4858d 100644 --- a/include/asm-blackfin/mach-bf548/BF544_def.h +++ b/include/asm-blackfin/mach-bf548/BF544_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF544_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h index 1cb338154c..ce7c8804c0 100644 --- a/include/asm-blackfin/mach-bf548/BF547_def.h +++ b/include/asm-blackfin/mach-bf548/BF547_def.h @@ -113,14 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF547_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h index 950ce4325e..e02e843e57 100644 --- a/include/asm-blackfin/mach-bf548/BF548_def.h +++ b/include/asm-blackfin/mach-bf548/BF548_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF548_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h index 55b0a296cd..a16ff5aaf6 100644 --- a/include/asm-blackfin/mach-bf548/BF549_def.h +++ b/include/asm-blackfin/mach-bf548/BF549_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF549_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/def_local.h b/include/asm-blackfin/mach-bf548/def_local.h index 14c111f712..81eca83bce 100644 --- a/include/asm-blackfin/mach-bf548/def_local.h +++ b/include/asm-blackfin/mach-bf548/def_local.h @@ -1 +1,2 @@ +#include "mem_map.h" #include "ports.h" diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h new file mode 100644 index 0000000000..4f943977f5 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -0,0 +1,21 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BF54X_MEM_MAP_H__ +#define __BF54X_MEM_MAP_H__ + +#define L1_DATA_A_SRAM (0xFF800000) +#define L1_DATA_A_SRAM_SIZE (0x4000) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM (0xFF900000) +#define L1_DATA_B_SRAM_SIZE (0x4000) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM (0xFFA00000) +#define L1_INST_SRAM_SIZE (0xC000) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h new file mode 100644 index 0000000000..3e361d614a --- /dev/null +++ b/include/asm-blackfin/mem_map.h @@ -0,0 +1,26 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MEM_MAP_H__ +#define __BFIN_MEM_MAP_H__ + +/* Every Blackfin so far has MMRs like this */ +#ifndef COREMMR_BASE +# define COREMMR_BASE 0xFFE00000 +#endif +#ifndef SYSMMR_BASE +# define SYSMMR_BASE 0xFFC00000 +#endif + +/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ +#ifndef L1_SRAM_SCRATCH +# define L1_SRAM_SCRATCH 0xFFB00000 +# define L1_SRAM_SCRATCH_SIZE 0x1000 +# define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) +#endif + +#endif diff --git a/include/asm-blackfin/mmc.h b/include/asm-blackfin/mmc.h deleted file mode 100644 index aa2ac95a9e..0000000000 --- a/include/asm-blackfin/mmc.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-avr32/arch-at32ap700x/mmc.h> diff --git a/include/asm-blackfin/sdh.h b/include/asm-blackfin/sdh.h new file mode 100644 index 0000000000..2c2f63ed55 --- /dev/null +++ b/include/asm-blackfin/sdh.h @@ -0,0 +1,17 @@ +/* + * sdh.h, export bfin_mmc_init + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_SDH_H__ +#define __ASM_SDH_H__ + +#include <mmc.h> +#include <asm/u-boot.h> + +int bfin_mmc_init(bd_t *bis); + +#endif diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index 18306dd54c..117f44c4d3 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -29,9 +29,6 @@ #ifdef __KERNEL__ /* only set these up for kernel code */ -#include <config.h> -#include <asm/blackfin.h> - #define __HAVE_ARCH_STRCPY #define __HAVE_ARCH_STRNCPY #define __HAVE_ARCH_STRCMP @@ -47,7 +44,7 @@ extern int strcmp(const char *cs, const char *ct); extern int strncmp(const char *cs, const char *ct, size_t count); extern void *memcpy(void *dest, const void *src, size_t count); extern void *memset(void *s, int c, size_t count); -extern int memcmp(const void *, const void *, __kernel_size_t); +extern int memcmp(const void *, const void *, size_t); extern void *memmove(void *dest, const void *src, size_t count); #else /* KERNEL */ diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 3db8171fb3..1e821d9084 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -53,7 +53,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (384 * 1024) @@ -109,7 +109,7 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 #endif -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* @@ -125,6 +125,7 @@ * SDH Settings */ #if !defined(__ADSPBF512__) +#define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_BFIN_SDH #endif diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 97853af2d0..711fa27b44 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -126,7 +126,7 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 #endif -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 0d0235478b..7800c3276a 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -61,7 +61,8 @@ * (can't be used same time as ethernet) */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC_BOOTROM_ECC #endif #ifdef CONFIG_BFIN_NFC #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 @@ -69,7 +70,6 @@ #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CONFIG_CMD_NAND #endif @@ -118,14 +118,19 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x20000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif -#define ENV_IS_EMBEDDED_CUSTOM /* @@ -150,6 +155,15 @@ /* + * Video Settings + */ +#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 +# define CONFIG_LQ035Q1_SPI_BUS 0 +# define CONFIG_LQ035Q1_SPI_CS 7 +#endif + + +/* * Misc Settings */ #define CONFIG_MISC_INIT_R diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 0006b029e2..083c030179 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -117,7 +117,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 463b7d08cc..86aa1f61e6 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -115,7 +115,7 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x10000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 0f908efff2..6627a04f59 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -94,7 +94,7 @@ * Env Storage Settings */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_OFFSET 0x4000 #else diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 7368629981..7e9dd36bce 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -115,7 +115,7 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x10000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 74b9ecd0b0..de2add7595 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -113,7 +113,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -145,7 +145,7 @@ * SPI_MMC Settings */ #define CONFIG_MMC -#define CONFIG_BFIN_SPI_MMC +#define CONFIG_SPI_MMC /* diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index c4d899dca2..4ea2300f4b 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -110,7 +110,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 5b9de16958..f9c97114ad 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -107,7 +107,7 @@ #define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x40000 @@ -118,7 +118,7 @@ #define CONFIG_ENV_OFFSET 0x2000 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif @@ -133,7 +133,6 @@ #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CONFIG_CMD_NAND /* @@ -162,6 +161,7 @@ * SDH Settings */ #if !defined(__ADSPBF544__) +#define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_BFIN_SDH #endif diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h new file mode 100644 index 0000000000..0be170c3ee --- /dev/null +++ b/include/configs/bf561-acvilon.h @@ -0,0 +1,178 @@ +/* + * U-boot - Configuration file for BF561 Acvilon System On Module + * For more information please go to http://www.niistt.ru/ + */ + +#ifndef __CONFIG_BF561_ACVILON_H__ +#define __CONFIG_BF561_ACVILON_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf561-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 12000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 50 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 128 + +#define CONFIG_EBIU_SDRRC_VAL 0x300 +#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189 + +#define CONFIG_EBIU_AMGCTL_VAL 0x4e +#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 +#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * RTC Settings + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_I2C_DTT_ADDR 0x49 +/*#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3*/ + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DTT + +#if defined(CONFIG_CMD_NET) + +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT +/* #define CONFIG_SMC911X_16_BIT */ +#define CONFIG_SMC911X_BASE 0x28000000 + +#endif /* (CONFIG_CMD_NET) */ + +#define CONFIG_HOSTNAME bf561-acvilon + +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_SYS_NO_FLASH + + +/* + * I2C Settings + */ +#define CONFIG_HARD_I2C +/* Use 300kHz speed by default */ +#define CONFIG_SYS_I2C_SPEED 0x00 +#define CONFIG_PCA9564_I2C +#define CONFIG_PCA9564_BASE 0x2c000000 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +/* #define CONFIG_CMD_SAVEENV */ +#define CONFIG_ENV_SECT_SIZE (1056 * 8) +#define CONFIG_ENV_OFFSET ((16 + 256) * 1056) +#define CONFIG_ENV_SIZE (8 * 1056) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) + + +/* + * NAND Settings + * We're using NAND_PLAT driver to make things simplier + */ +#define CONFIG_NAND_PLAT +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BASE 0x24000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) +#define BFIN_NAND_READY PF10 +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \ + bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \ + } while (0) + + +/* + * Misc Settings + */ +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_PROMPT "Acvilon> " + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif /* __CONFIG_BF561_ACVILON_H__ */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index a1fa80bb89..8ab38bbacb 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -87,7 +87,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 0fbd8f4980..6a2f1c7aa5 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -45,7 +45,7 @@ # define CONFIG_CMD_USB_STORAGE # define CONFIG_DOS_PARTITION # endif -# ifdef CONFIG_NAND_PLAT +# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN) # define CONFIG_CMD_NAND # endif # ifdef CONFIG_POST @@ -75,6 +75,9 @@ # else # define CONFIG_CMD_JFFS2 # endif +# ifdef CONFIG_CMD_JFFS2 +# define CONFIG_JFFS2_SUMMARY +# endif # define CONFIG_CMD_BOOTLDR # define CONFIG_CMD_CACHE # define CONFIG_CMD_CPLBINFO @@ -96,6 +99,7 @@ #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_LOADS_ECHO 1 #define CONFIG_JTAG_CONSOLE +#define CONFIG_SILENT_CONSOLE #ifndef CONFIG_BAUDRATE # define CONFIG_BAUDRATE 57600 #endif @@ -127,6 +131,9 @@ #ifndef CONFIG_BOOTARGS_ROOT # define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw" #endif +#ifndef FLASHBOOT_ENV_SETTINGS +# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0" +#endif #define CONFIG_BOOTARGS \ "root=" CONFIG_BOOTARGS_ROOT " " \ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ @@ -174,7 +181,19 @@ "erase 0x20000000 +$(filesize);" \ "cp.b $(loadaddr) 0x20000000 $(filesize)" # endif +# ifdef CONFIG_NETCONSOLE +# define NETCONSOLE_ENV \ + "nc=" \ + "set ncip ${serverip};" \ + "set stdin nc;" \ + "set stdout nc" \ + "\0" +# else +# define NETCONSOLE_ENV +# endif # define NETWORK_ENV_SETTINGS \ + NETCONSOLE_ENV \ + \ "ubootfile=" UBOOT_ENV_FILE "\0" \ "update=" \ "tftp $(loadaddr) $(ubootfile);" \ @@ -211,7 +230,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ NAND_ENV_SETTINGS \ NETWORK_ENV_SETTINGS \ - "flashboot=bootm 0x20100000\0" + FLASHBOOT_ENV_SETTINGS /* * Network Settings diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index 159271996b..ad1dd12964 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000) + /* * Memory Settings @@ -105,8 +108,8 @@ #define CONFIG_ENV_ADDR 0x20008000 #define CONFIG_ENV_OFFSET 0x8000 #define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* @@ -125,6 +128,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 300000;" \ + "bootm 0x1000000\0" /* diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index 06eb2889e3..75152964b6 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 5 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -93,6 +96,8 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" /* diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 34d429935e..0d68ebae2a 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -92,7 +95,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -127,6 +130,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 300000;" \ + "bootm 0x1000000\0" /* diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index d1870a8963..c1179b0aee 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -96,7 +96,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -131,6 +131,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 280000;" \ + "bootm 0x1000000\0" /* @@ -138,13 +142,4 @@ */ #include <configs/bfin_adi_common.h> -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "run flashboot" - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - NAND_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0" - #endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index b5cfc2199e..93c4c8ddc1 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -96,7 +99,7 @@ #define CONFIG_ENV_ADDR 0x20008000 #define CONFIG_ENV_OFFSET 0x8000 #define CONFIG_ENV_SIZE 0x8000 -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* @@ -115,6 +118,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" #ifndef __ADSPBF542__ /* Don't waste time transferring a logo over the UART */ diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 4a77435648..1741ed4932 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -30,7 +30,7 @@ #define CONFIG_PLL_BYPASS 0 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ /* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 22 +#define CONFIG_VCO_MULT 20 /* CCLK_DIV controls the core clock divider */ /* Values can be 1, 2, 4, or 8 ONLY */ #define CONFIG_CCLK_DIV 1 @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 5 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -98,6 +101,8 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" /* diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 066859f8ee..7c9f71e888 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -75,7 +75,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h new file mode 100644 index 0000000000..9c04d8a28e --- /dev/null +++ b/include/configs/tcm-bf518.h @@ -0,0 +1,129 @@ +/* + * U-boot - Configuration file for Bluetechnix TCM-BF518 board + */ + +#ifndef __CONFIG_TCM_BF518_H__ +#define __CONFIG_TCM_BF518_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf518-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 16 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +/* This board has a 32meg MT48H16M16 */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (384 * 1024) + + +/* + * Network Settings + */ +#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME tcm-bf518 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 19 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 9794e1b904..5a5fbddac3 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4 +/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) + /* * Memory Settings @@ -93,7 +96,7 @@ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR #endif #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -128,6 +131,10 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 280000;" \ + "bootm 0x1000000\0" /* diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile index cbf47f0129..eebb131191 100644 --- a/lib_blackfin/Makefile +++ b/lib_blackfin/Makefile @@ -31,10 +31,12 @@ CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"' LIB = $(obj)lib$(ARCH).a +SOBJS-y += ins.o SOBJS-y += memcmp.o SOBJS-y += memcpy.o SOBJS-y += memmove.o SOBJS-y += memset.o +SOBJS-y += outs.o COBJS-y += board.o COBJS-y += boot.o diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 6cade7d110..90da2b4358 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -14,6 +14,7 @@ #include <stdio_dev.h> #include <environment.h> #include <malloc.h> +#include <mmc.h> #include <net.h> #include <timestamp.h> #include <status_led.h> @@ -130,17 +131,26 @@ void init_cplbtables(void) dcplb_add(0xFF800000, L1_DMEMORY); ++i; - icplb_add(CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_IKERNEL); - dcplb_add(CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK, SDRAM_DKERNEL); - ++i; + if (CONFIG_MEM_SIZE) { + uint32_t mbase = CONFIG_SYS_MONITOR_BASE; + uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN; + mbase &= CPLB_PAGE_MASK; + mend &= CPLB_PAGE_MASK; - /* If the monitor crosses a 4 meg boundary, we'll need - * to lock two entries for it. - */ - if ((CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK) != ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK)) { - icplb_add((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_IKERNEL); - dcplb_add((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) & CPLB_PAGE_MASK, SDRAM_DKERNEL); + icplb_add(mbase, SDRAM_IKERNEL); + dcplb_add(mbase, SDRAM_DKERNEL); ++i; + + /* + * If the monitor crosses a 4 meg boundary, we'll need + * to lock two entries for it. We assume it doesn't + * cross two 4 meg boundaries ... + */ + if (mbase != mend) { + icplb_add(mend, SDRAM_IKERNEL); + dcplb_add(mend, SDRAM_DKERNEL); + ++i; + } } icplb_add(0x20000000, SDRAM_INON_CHBL); @@ -239,6 +249,8 @@ void board_init_f(ulong bootflag) bd->bi_vco = get_vco(); bd->bi_cclk = get_cclk(); bd->bi_sclk = get_sclk(); + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; /* Initialize */ serial_early_puts("IRQ init\n"); @@ -262,7 +274,7 @@ void board_init_f(ulong bootflag) printf("System: %s MHz\n", strmhz(buf, get_sclk())); printf("RAM: "); - print_size(initdram(0), "\n"); + print_size(bd->bi_memsize, "\n"); #if defined(CONFIG_POST) post_init_f(); post_bootmode_init(); @@ -329,6 +341,11 @@ void board_init_r(gd_t * id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif +#ifdef CONFIG_GENERIC_MMC + puts("MMC: "); + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ env_relocate(); diff --git a/lib_blackfin/config.mk b/lib_blackfin/config.mk index ce2fe6773e..323d28f068 100644 --- a/lib_blackfin/config.mk +++ b/lib_blackfin/config.mk @@ -43,6 +43,11 @@ endif ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) ALL += $(obj)u-boot.ldr endif +ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) +CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o +else +CREATE_LDR_ENV = +endif SYM_PREFIX = _ @@ -53,9 +58,8 @@ LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE)) LDR_FLAGS += --use-vmas LDR_FLAGS += --initcode $(obj)cpu/$(CPU)/initcode.o ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART) -ifneq ($(ENV_IS_EMBEDDED_CUSTOM),ENV_IS_EMBEDDED_CUSTOM) -LDR_FLAGS += --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o -endif +LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \ + --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o endif ifneq (,$(findstring s,$(MAKEFLAGS))) LDR_FLAGS += --quiet diff --git a/lib_blackfin/ins.S b/lib_blackfin/ins.S new file mode 100644 index 0000000000..4519596420 --- /dev/null +++ b/lib_blackfin/ins.S @@ -0,0 +1,117 @@ +/* + * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops + * + * Copyright 2004-2008 Analog Devices Inc. + * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> + * Licensed under the GPL-2 or later. + */ + +#include <asm/blackfin.h> + +.align 2 + +#ifdef CONFIG_IPIPE +# define DO_CLI \ + [--sp] = rets; \ + [--sp] = (P5:0); \ + sp += -12; \ + call ___ipipe_disable_root_irqs_hw; \ + sp += 12; \ + (P5:0) = [sp++]; +# define CLI_INNER_NOP +#else +# define DO_CLI cli R3; +# define CLI_INNER_NOP nop; nop; nop; +#endif + +#ifdef CONFIG_IPIPE +# define DO_STI \ + sp += -12; \ + call ___ipipe_enable_root_irqs_hw; \ + sp += 12; \ +2: rets = [sp++]; +#else +# define DO_STI 2: sti R3; +#endif + +#ifdef CONFIG_BFIN_INS_LOWOVERHEAD +# define CLI_OUTER DO_CLI; +# define STI_OUTER DO_STI; +# define CLI_INNER 1: +# if ANOMALY_05000416 +# define STI_INNER nop; 2: nop; +# else +# define STI_INNER 2: +# endif +#else +# define CLI_OUTER +# define STI_OUTER +# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP; +# define STI_INNER DO_STI; +#endif + +/* + * Reads on the Blackfin are speculative. In Blackfin terms, this means they + * can be interrupted at any time (even after they have been issued on to the + * external bus), and re-issued after the interrupt occurs. + * + * If a FIFO is sitting on the end of the read, it will see two reads, + * when the core only sees one. The FIFO receives the read which is cancelled, + * and not delivered to the core. + * + * To solve this, interrupts are turned off before reads occur to I/O space. + * There are 3 versions of all these functions + * - turns interrupts off every read (higher overhead, but lower latency) + * - turns interrupts off every loop (low overhead, but longer latency) + * - DMA version, which do not suffer from this issue. DMA versions have + * different name (prefixed by dma_ ), and are located in + * ../kernel/bfin_dma_5xx.c + * Using the dma related functions are recommended for transfering large + * buffers in/out of FIFOs. + */ + +#define COMMON_INS(func, ops) \ +ENTRY(_ins##func) \ + P0 = R0; /* P0 = port */ \ + CLI_OUTER; /* 3 instructions before first read access */ \ + P1 = R1; /* P1 = address */ \ + P2 = R2; /* P2 = count */ \ + SSYNC; \ + \ + LSETUP(1f, 2f) LC0 = P2; \ + CLI_INNER; \ + ops; \ + STI_INNER; \ + \ + STI_OUTER; \ + RTS; \ +ENDPROC(_ins##func) + +COMMON_INS(l, \ + R0 = [P0]; \ + [P1++] = R0; \ +) + +COMMON_INS(w, \ + R0 = W[P0]; \ + W[P1++] = R0; \ +) + +COMMON_INS(w_8, \ + R0 = W[P0]; \ + B[P1++] = R0; \ + R0 = R0 >> 8; \ + B[P1++] = R0; \ +) + +COMMON_INS(b, \ + R0 = B[P0]; \ + B[P1++] = R0; \ +) + +COMMON_INS(l_16, \ + R0 = [P0]; \ + W[P1++] = R0; \ + R0 = R0 >> 16; \ + W[P1++] = R0; \ +) diff --git a/lib_blackfin/outs.S b/lib_blackfin/outs.S new file mode 100644 index 0000000000..90c6033c9e --- /dev/null +++ b/lib_blackfin/outs.S @@ -0,0 +1,60 @@ +/* + * Implementation of outs{bwl} for BlackFin processors using zero overhead loops. + * + * Copyright 2005-2009 Analog Devices Inc. + * 2005 BuyWays BV + * Bas Vermeulen <bas@buyways.nl> + * + * Licensed under the GPL-2. + */ + +#include <asm/linkage.h> + +.align 2 + +ENTRY(_outsl) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2; +.Llong_loop_s: R0 = [P1++]; +.Llong_loop_e: [P0] = R0; + RTS; +ENDPROC(_outsl) + +ENTRY(_outsw) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2; +.Lword_loop_s: R0 = W[P1++]; +.Lword_loop_e: W[P0] = R0; + RTS; +ENDPROC(_outsw) + +ENTRY(_outsb) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2; +.Lbyte_loop_s: R0 = B[P1++]; +.Lbyte_loop_e: B[P0] = R0; + RTS; +ENDPROC(_outsb) + +ENTRY(_outsw_8) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; +.Lword8_loop_s: R1 = B[P1++]; + R0 = B[P1++]; + R0 = R0 << 8; + R0 = R0 + R1; +.Lword8_loop_e: W[P0] = R0; + RTS; +ENDPROC(_outsw_8) diff --git a/lib_blackfin/u-boot.lds.S b/lib_blackfin/u-boot.lds.S index 3604b7888d..3be341fad0 100644 --- a/lib_blackfin/u-boot.lds.S +++ b/lib_blackfin/u-boot.lds.S @@ -57,7 +57,14 @@ OUTPUT_ARCH(bfin) MEMORY { +#if CONFIG_MEM_SIZE ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN +# define ram_code ram +# define ram_data ram +#else +# define ram_code l1_code +# define ram_data l1_data +#endif l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } @@ -65,27 +72,31 @@ MEMORY ENTRY(_start) SECTIONS { - .text : + .text.pre : { cpu/blackfin/start.o (.text .text.*) LDS_BOARD_TEXT + } >ram_code - __initcode_start = .; + .text.init : + { cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; + } >ram_code + __initcode_lma = LOADADDR(.text.init); + __initcode_len = SIZEOF(.text.init); + .text : + { *(.text .text.*) - } >ram + } >ram_code .rodata : { . = ALIGN(4); - *(.rodata .rodata.*) - *(.rodata1) - *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) . = ALIGN(4); - } >ram + } >ram_data .data : { @@ -96,14 +107,14 @@ SECTIONS *(.sdata2) *(.dynamic) CONSTRUCTORS - } >ram + } >ram_data .u_boot_cmd : { ___u_boot_cmd_start = .; *(.u_boot_cmd) ___u_boot_cmd_end = .; - } >ram + } >ram_data .text_l1 : { @@ -112,8 +123,10 @@ SECTIONS *(.l1.text) . = ALIGN(4); __etext_l1 = .; - } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); + } >l1_code AT>ram_code + __text_l1_lma = LOADADDR(.text_l1); + __text_l1_len = SIZEOF(.text_l1); + ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!") .data_l1 : { @@ -123,17 +136,19 @@ SECTIONS *(.l1.bss) . = ALIGN(4); __edata_l1 = .; - } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); + } >l1_data AT>ram_data + __data_l1_lma = LOADADDR(.data_l1); + __data_l1_len = SIZEOF(.data_l1); + ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") .bss : { . = ALIGN(4); - __bss_start = .; *(.sbss) *(.scommon) *(.dynbss) *(.bss .bss.*) *(COMMON) - __bss_end = .; - } >ram + } >ram_data + __bss_vma = ADDR(.bss); + __bss_len = SIZEOF(.bss); } |
