Merge branch 'u-boot/master' into 'u-boot-arm/master'

25 files changed, 334 insertions, 2978 deletions

diff --git a/include/altera.h b/include/altera.h
index ae5f7eec46..c2991ad800 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -10,35 +10,59 @@
 #ifndef _ALTERA_H_
 #define _ALTERA_H_
 
-typedef enum {				/* typedef Altera_iface */
-	min_altera_iface_type,		/* insert all new types after this */
-	passive_serial,			/* serial data and external clock */
-	passive_parallel_synchronous,	/* parallel data */
-	passive_parallel_asynchronous,	/* parallel data */
-	passive_serial_asynchronous,	/* serial data w/ internal clock (not used)	*/
-	altera_jtag_mode,		/* jtag/tap serial (not used ) */
-	fast_passive_parallel,		/* fast passive parallel (FPP) */
-	fast_passive_parallel_security,	/* fast passive parallel with security (FPPS) */
-	max_altera_iface_type		/* insert all new types before this */
-} Altera_iface;				/* end, typedef Altera_iface */
+enum altera_iface {
+	/* insert all new types after this */
+	min_altera_iface_type,
+	/* serial data and external clock */
+	passive_serial,
+	/* parallel data */
+	passive_parallel_synchronous,
+	/* parallel data */
+	passive_parallel_asynchronous,
+	/* serial data w/ internal clock (not used) */
+	passive_serial_asynchronous,
+	/* jtag/tap serial (not used ) */
+	altera_jtag_mode,
+	/* fast passive parallel (FPP) */
+	fast_passive_parallel,
+	/* fast passive parallel with security (FPPS) */
+	fast_passive_parallel_security,
+	/* insert all new types before this */
+	max_altera_iface_type,
+};
 
-typedef enum {			/* typedef Altera_Family */
-	min_altera_type,	/* insert all new types after this */
-	Altera_ACEX1K,		/* ACEX1K Family */
-	Altera_CYC2,		/* CYCLONII Family */
-	Altera_StratixII,	/* StratixII Family */
-/* Add new models here */
-	max_altera_type		/* insert all new types before this */
-} Altera_Family;		/* end, typedef Altera_Family */
+enum altera_family {
+	/* insert all new types after this */
+	min_altera_type,
+	/* ACEX1K Family */
+	Altera_ACEX1K,
+	/* CYCLONII Family */
+	Altera_CYC2,
+	/* StratixII Family */
+	Altera_StratixII,
+	/* SoCFPGA Family */
+	Altera_SoCFPGA,
 
-typedef struct {		/* typedef Altera_desc */
-	Altera_Family	family;	/* part type */
-	Altera_iface	iface;	/* interface type */
-	size_t		size;	/* bytes of data part can accept */
-	void *		iface_fns;/* interface function table */
-	void *		base;	/* base interface address */
-	int		cookie;	/* implementation specific cookie */
-} Altera_desc;			/* end, typedef Altera_desc */
+	/* Add new models here */
+
+	/* insert all new types before this */
+	max_altera_type,
+};
+
+typedef struct {
+	/* part type */
+	enum altera_family	family;
+	/* interface type */
+	enum altera_iface	iface;
+	/* bytes of data part can accept */
+	size_t			size;
+	/* interface function table */
+	void			*iface_fns;
+	/* base interface address */
+	void			*base;
+	/* implementation specific cookie */
+	int			cookie;
+} Altera_desc;
 
 /* Generic Altera Functions
  *********************************************************************/
@@ -69,4 +93,8 @@ typedef struct {
 	Altera_post_fn post;
 } altera_board_specific_func;
 
+#ifdef CONFIG_FPGA_SOCFPGA
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
 #endif /* _ALTERA_H_ */
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
deleted file mode 100644
index 788fa0f91c..0000000000
--- a/include/configs/CRAYL1.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * David Updegraff, Cray, Inc.  dave@cray.com: our 405 is walnut-lite..
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_CRAYL1
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU	*/
-
-/*
- * Note: I make an "image" from U-Boot itself, which prefixes 0x40
- * bytes of header info, hence start address is thus shifted.
- */
-#define	CONFIG_SYS_TEXT_BASE	0xFFFD0040
-
-#define CONFIG_SYS_CLK_FREQ 25000000
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		    1	/* MII PHY management */
-#define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
-#define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
- * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
- #define CONFIG_PRAM			16
- */
-#define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
-#undef CONFIG_BOOTARGS
-
-/* Bootcmd is overridden by the bootscript in board/cray/L1
- */
-#define	CONFIG_SYS_AUTOLOAD		"no"
-#define CONFIG_BOOTCOMMAND	"dhcp"
-
-/*
- * ..during experiments..
- #define CONFIG_SERVERIP         10.0.0.1
- #define CONFIG_ETHADDR          00:40:a6:80:14:5
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SDRAM_BANK0		1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		    400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		    0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_IDENT_STRING     "Cray L1"
-#define CONFIG_ENV_OVERWRITE     1
-#define CONFIG_SYS_HUSH_PARSER			1
-#define CONFIG_SOURCE			1
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * how many time to fail & restart a net-TFTP before giving up & resetting
- * the board hoping that a reset of net interface might help..
- */
-#define CONFIG_NET_RESET 5
-
-/*
- * bauds.  Just to make it compile; in our case, I read the base_baud
- * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
- * drives the system clock.
- */
-#define CONFIG_SYS_BASE_BAUD       403225
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE			/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16				/* max number of command args	*/
-
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* where to load what we get from TFTP */
-#define CONFIG_SYS_EXTBDINFO		1		/* To use extended board_into (bd_t) */
-#define CONFIG_SYS_DRAM_TEST		1
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFC00000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
-
-/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
-#define CONFIG_ENV_OFFSET		0x3c8000
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define	CONFIG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
-#define CONFIG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/
-
-/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
- * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
- */
-#define CONFIG_SYS_SDRAM_SIZE		32		/* megs of ram */
-#define CONFIG_SYS_MEMTEST_START	0x2000  /* memtest works from the end of */
-									/* the exception vector table */
-									/* to the end of the DRAM  */
-									/* less monitor and malloc area */
-#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
-#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
-				+ CONFIG_SYS_MALLOC_LEN \
-				+ CONFIG_ENV_SECT_SIZE \
-				+ CONFIG_SYS_STACK_USAGE )
-
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
-/* END ENVIRONNEMENT FLASH */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in OnChipMem )
- */
-#if 1
-/* On Chip Memory location */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	     */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- */
-#define EEPROM_WRITE_ADDRESS 0xA0
-#define EEPROM_READ_ADDRESS  0xA1
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
deleted file mode 100644
index 546b725317..0000000000
--- a/include/configs/KAREF.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2004 Sandburst Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
- *		    design.
- ***********************************************************************/
-
-/*
- * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
-#define CONFIG_440GX		  1	     /* Specifc GX support	*/
-#define CONFIG_440		  1	     /* ... PPC440 family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
-#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
-#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
-#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
-
-#define CONFIG_VERY_BIG_RAM 1
-#define CONFIG_VERSION_VARIABLE
-
-#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
-#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
-#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
-#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
-#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
-#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
-#define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
-#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
-#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/* Here for completeness */
-#define CONFIG_SYS_OFEMAC_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM    1
-#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
-#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#define CONFIG_BAUDRATE	      9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
-#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
-#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
-#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
-#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
-#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
-#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
-
-#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
-#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
-
-#define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */
-
-#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
-
-/*-----------------------------------------------------------------------
- * Networking
- *----------------------------------------------------------------------*/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII	      1		     /* MII PHY management	*/
-#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
-#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
-#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
-#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
-#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
-#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
-#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_NETMASK	      255.255.0.0
-#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
-#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
-#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-
-
-/* Include NetConsole support */
-#define CONFIG_NETCONSOLE
-
-/* Include auto complete with tabs */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
-
-#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
-
-#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
-
-
-/*-----------------------------------------------------------------------
- * Console Buffer
- *----------------------------------------------------------------------*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-					     /* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
-#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
-
-/*-----------------------------------------------------------------------
- * Memory Test
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
-
-/*-----------------------------------------------------------------------
- * Compact Flash (in true IDE mode)
- *----------------------------------------------------------------------*/
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
-					    to get to the correct offset */
-#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
-
-/*-----------------------------------------------------------------------
- * PCI
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI			     /* include pci support	*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
-#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
-#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
-#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
-#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
deleted file mode 100644
index 19ea3167af..0000000000
--- a/include/configs/MERGERBOX.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300	1
-#define CONFIG_MPC837x	1
-#define CONFIG_MPC8377	1
-
-#define CONFIG_SYS_TEXT_BASE	0xFC000000
-
-#define CONFIG_PCI	1
-#define CONFIG_PCI_INDIRECT_BRIDGE 1
-
-#define	CONFIG_MASK_AER_AO
-#define CONFIG_DISPLAY_AER_FULL
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- */
-#define CONFIG_TSEC_ENET
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
-#define CONFIG_PCIE
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
-#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word stored in EEPROM.
- */
-#define CONFIG_SYS_HRCW_LOW	0
-#define CONFIG_SYS_HRCW_HIGH	0
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP	3
-#define CONFIG_SYS_ACR_RPTCNT	3
-
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP	3
-
-/* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM		3
-#define CONFIG_SYS_SCCR_TSEC2CM		0
-#define CONFIG_SYS_SCCR_SDHCCM		3
-#define CONFIG_SYS_SCCR_ENCCM		3 /* also clock for I2C-1 */
-#define CONFIG_SYS_SCCR_USBDRCM		CONFIG_SYS_SCCR_ENCCM /* must match */
-#define CONFIG_SYS_SCCR_PCIEXP1CM	3
-#define CONFIG_SYS_SCCR_PCIEXP2CM	3
-#define CONFIG_SYS_SCCR_PCICM		1
-#define CONFIG_SYS_SCCR_SATACM		0xFF
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH	0x087c0000
-#define CONFIG_SYS_SICRL	0x40000000
-
-/*
- * Output Buffer Impedance
- */
-#define CONFIG_SYS_OBIR		0x30000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_EN | DDRCDR_PZ_HIZ |\
-					 DDRCDR_NZ_HIZ | DDRCDR_ODT |\
-					 DDRCDR_Q_DRN)
-
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_MODE_WEAK
-#define CONFIG_SYS_DDR_WRITE_DATA_DELAY	2
-#define CONFIG_SYS_DDR_CPO	0x1f
-
-/* SPD table located at offset 0x20 in extended adressing ROM
- * used for HRCW fetch after power-on reset
- */
-#define	CONFIG_SPD_EEPROM
-#define	SPD_EEPROM_ADDRESS	0x50
-#define	SPD_EEPROM_OFFSET	0x20
-#define	SPD_EEPROM_ADDR_LEN	2
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(512*1024)
-#define CONFIG_SYS_MALLOC_LEN		(512*1024)
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
-					 GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-#define CONFIG_FSL_ELBC		1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		64
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
-				 BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
-				 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
-				 OR_GPCM_XACS | OR_GPCM_SCY_15 |\
-				 OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
-				 OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_MTD_NAND_VERIFY_WRITE	1
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_NAND_FSL_ELBC		1
-
-#define CONFIG_SYS_NAND_BASE	0xE0600000
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
-				 BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
-				 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
-				 OR_FCM_TRLX | OR_FCM_EHTR)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CONSOLE		ttyS0
-#define CONFIG_BAUDRATE		115200
-
-/* SERDES */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1	0xe3000
-#define CONFIG_FSL_SERDES2	0xe3100
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE		(256 << 20)
-#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	(256 << 20)
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE		(1 << 20)
-
-#ifdef CONFIG_PCIE
-#define CONFIG_SYS_PCIE1_BASE		0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE	(128 << 20)
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	(256 << 20)
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	(8 << 20)
-
-#define CONFIG_SYS_PCIE2_BASE		0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE	(128 << 20)
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	(256 << 20)
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	(8 << 20)
-#endif
-
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
-
-/*
- * TSEC
- */
-#define CONFIG_GMII			/* MII PHY management */
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define	CONFIG_SYS_VSC8601_SKEW_TX	3
-#define	CONFIG_SYS_VSC8601_SKEW_RX	3
-
-#define CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME		"TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET		0x24000
-#define TSEC1_PHY_ADDR			0x10
-#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX			0
-
-#define CONFIG_ETHPRIME			"TSEC0"
-#define CONFIG_HAS_ETH0
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET	0x18000
-#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET	0x19000
-#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
-
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_SATA
-
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
-#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
-
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	1
-
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_AUTO_COMPLETE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_LOAD_ADDR	0x2000000
-#define CONFIG_LOADADDR		0x4000000
-#define CONFIG_SYS_CBSIZE	256
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-#define CONFIG_LOADS_ECHO		1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
-
-#define CONFIG_SYS_MEMTEST_START	(60<<20)
-#define CONFIG_SYS_MEMTEST_END		(70<<20)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2		HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS	1
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE
-
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM | BATL_PP_RW |\
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
-				 BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* unused */
-#define CONFIG_SYS_IBAT1L	(0)
-#define CONFIG_SYS_IBAT1U	(0)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR | BATL_PP_RW |\
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
-				 BATU_VP)
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* unused */
-#define CONFIG_SYS_IBAT3L	(0)
-#define CONFIG_SYS_IBAT3U	(0)
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-/*
- * I2C EEPROM settings
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_EEPROM_SIZE			0x4000
-
-/*
- * Environment Configuration
- */
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0xFFD00000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-
-/*
- * Video
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501_PCI
-#define VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_CMD_BMP
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_SM501_FBMEM_OFFSET	0x10000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
-
-/*
- * SPI
- */
-#define CONFIG_MPC8XXX_SPI
-
-/*
- * USB
- */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_KEYBOARD
-/*
- *
- */
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY	1000
-
-#define MV_CI		"MergerBox"
-#define MV_VCI		"MergerBox"
-#define MV_FPGA_DATA	0xfc100000
-#define MV_FPGA_SIZE	0x00200000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x02800000
-#define MV_DTB_ADDR_RAM		0x00600000
-#define MV_INITRD_ADDR_RAM	0x01000000
-#define MV_FITADDR		0xfc300000
-#define	MV_SPLAH_ADDR		0xffe00000
-
-#define CONFIG_BOOTCOMMAND	"run i2c_init;if test ${boot_sqfs} -eq 1;"\
-				"then; run fitboot;else;run ubiboot;fi;"
-#define CONFIG_BOOTARGS		"console=ttyS0,115200n8"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"console_nr=0\0"\
-	"stdin=serial\0"\
-	"stdout=serial\0"\
-	"stderr=serial\0"\
-	"boot_sqfs=1\0"\
-	"usb_dr_mode=host\0"\
-	"bootfile=MergerBox.fit\0"\
-	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
-	"fpga=0\0"\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
-	"mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
-	"mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
-	"mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
-	"uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
-	"fitaddr=" __stringify(MV_FITADDR) "\0"\
-	"mv_version=" U_BOOT_VERSION "\0"\
-	"mtdids=" MTDIDS_DEFAULT "\0"\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"\
-	"dhcp_client_id=" MV_CI "\0"\
-	"dhcp_vendor-class-identifier=" MV_VCI "\0"\
-	"upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
-		"protect off all;erase $uboota +0xC0000;"\
-		"cp.b $loadaddr $uboota $filesize\0"\
-	"upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
-		"cp.b $loadaddr $fpgadata $filesize\0"\
-	"upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
-		"cp.b $loadaddr $fitaddr $filesize\0"\
-	"addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
-		"rootfstype=squashfs\0"\
-	"addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
-		"rootfstype=ubifs\0"\
-	"addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
-		"rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
-	"netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
-	"netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
-	"ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
-	"doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
-	"fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
-		"imxtract $fitaddr ramdisk $mv_initrd_ram;"\
-		"imxtract $fitaddr fdt $mv_dtb_ram\0"\
-	"fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
-	"fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
-	"i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
-	"i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
-		"i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
-		"i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
-	"i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
-	"init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
-		"i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
-	"splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
-	""
-
-/*
- * FPGA
- */
-#define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
deleted file mode 100644
index 69ab5bb517..0000000000
--- a/include/configs/METROBOX.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * (C) Copyright 2004 Sandburst Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/************************************************************************
- * METROBOX.h - configuration Sandburst MetroBox
- ***********************************************************************/
-
-/*
- * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
- *
- *
- * $Log: METROBOX.h,v $
- * Revision 1.21  2005/06/03 15:05:25  tsawyer
- * MB rev 2.0.3 KA rev 0.0.7.  Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
- *
- * Revision 1.20  2005/04/11 20:51:11  tsawyer
- * fix ethernet
- *
- * Revision 1.19  2005/04/06 15:13:36  tsawyer
- * Update appropriate files to coincide with u-boot 1.1.3
- *
- * Revision 1.18  2005/03/10 14:16:02  tsawyer
- * add def'n for cis8201 short etch option.
- *
- * Revision 1.17  2005/03/09 19:49:51  tsawyer
- * Remove KGDB to allow use of 2nd serial port
- *
- * Revision 1.16  2004/12/02 19:00:23  tsawyer
- * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
- *
- * Revision 1.15  2004/09/15 18:04:12  tsawyer
- * add multiple serial port support
- *
- * Revision 1.14  2004/09/03 15:27:51  tsawyer
- * All metrobox boards are at 66.66 sys clock
- *
- * Revision 1.13  2004/08/05 20:27:46  tsawyer
- * Remove system ace definitions, add net console support
- *
- * Revision 1.12  2004/07/29 20:00:13  tsawyer
- * Add i2c bus 1
- *
- * Revision 1.11  2004/07/21 13:44:18  tsawyer
- * SystemACE is out, CF direct to local bus is in
- *
- * Revision 1.10  2004/06/29 19:08:55  tsawyer
- * Add CONFIG_MISC_INIT_R
- *
- * Revision 1.9	 2004/06/28 21:30:53  tsawyer
- * Fix default BOOTARGS
- *
- * Revision 1.8	 2004/06/17 15:51:08  tsawyer
- * auto complete
- *
- * Revision 1.7	 2004/06/17 15:08:49  tsawyer
- * Add autocomplete
- *
- * Revision 1.6	 2004/06/15 12:33:57  tsawyer
- * debugging checkpoint
- *
- * Revision 1.5	 2004/06/12 19:48:28  tsawyer
- * Debugging checkpoint
- *
- * Revision 1.4	 2004/06/02 13:03:06  tsawyer
- * Fix eth addrs
- *
- * Revision 1.3	 2004/05/18 19:56:10  tsawyer
- * Change default bootcommand to pImage.metrobox
- *
- * Revision 1.2	 2004/05/18 14:13:44  tsawyer
- * Add bringup values for bootargs and bootcommand.
- * Remove definition of ipaddress and serverip addresses.
- *
- * Revision 1.1	 2004/04/16 15:08:54  tsawyer
- * Initial Revision
- *
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_METROBOX		  1	     /* Board is Metrobox	*/
-#define CONFIG_440GX		  1	     /* Specifc GX support	*/
-#define CONFIG_440		  1	     /* ... PPC440 family	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
-#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
-#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
-
-#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
-#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
-
-#define CONFIG_VERY_BIG_RAM 1
-#define CONFIG_VERSION_VARIABLE
-
-#define CONFIG_IDENT_STRING " Sandburst Metrobox"
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
-#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
-#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
-#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
-#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
-#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_FPGA_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
-#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
-#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM    1
-#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
-#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#define CONFIG_BAUDRATE	      9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
-#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
-#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
-#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
-#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
-#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
-#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
-
-#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
-#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
-
-#define CONFIG_BOOTARGS	      "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
-#define CONFIG_BOOTCOMMAND    "tftp 8000000 pImage.metrobox;bootm 8000000"
-#define CONFIG_BOOTDELAY      5		    /* disable autoboot */
-
-#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
-
-/*-----------------------------------------------------------------------
- * Networking
- *----------------------------------------------------------------------*/
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII	      1		     /* MII PHY management	*/
-#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
-#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
-#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
-#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
-#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
-#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
-#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
-#define CONFIG_PHY_RESET_DELAY 1000
-#define CONFIG_NETMASK	      255.255.0.0
-#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
-#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
-#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-
-
-/* Include NetConsole support */
-#define CONFIG_NETCONSOLE
-
-/* Include auto complete with tabs */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
-
-#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	      "MetroBox=> "  /* Monitor Command Prompt	*/
-
-#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
-
-
-/*-----------------------------------------------------------------------
- * Console Buffer
- *----------------------------------------------------------------------*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-					     /* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
-#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
-
-/*-----------------------------------------------------------------------
- * Memory Test
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
-
-/*-----------------------------------------------------------------------
- * Compact Flash (in true IDE mode)
- *----------------------------------------------------------------------*/
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
-					    to get to the correct offset */
-#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
-
-/*-----------------------------------------------------------------------
- * PCI
- *----------------------------------------------------------------------*/
-/* General PCI */
-#define CONFIG_PCI			     /* include pci support	*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
-#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
-#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
-#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
-#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 68824fd2d4..147f122967 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -21,6 +21,8 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /***********************************************************
  * Note that it may also be a MIP405T board which is a subset of the
  * MIP405
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
deleted file mode 100644
index 1ab2b3d51a..0000000000
--- a/include/configs/MVBC_P.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2008
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 	1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_PSC_CONSOLE	1
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#undef	CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-#define CONFIG_HIGH_BATS	1
-
-#define MV_CI			mvBlueCOUGAR-P
-#define MV_VCI			mvBlueCOUGAR-P
-#define MV_FPGA_DATA		0xff860000
-#define MV_FPGA_SIZE		0
-#define MV_KERNEL_ADDR		0xffd00000
-#define MV_INITRD_ADDR		0xff900000
-#define MV_INITRD_LENGTH	0x00400000
-#define MV_SCRATCH_ADDR		0x00000000
-#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
-#define MV_SCRIPT_ADDR		0xff840000
-#define MV_SCRIPT_ADDR2		0xff850000
-#define MV_DTB_ADDR		0xfffc0000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_DTB_ADDR_RAM		0x00600000
-#define MV_INITRD_ADDR_RAM	0x01000000
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define MV_DTB_NAME		mvbc-p.dtb
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY		2
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR 	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		1000
-
-#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; \
-					then source ${script_addr};	\
-					else source ${script_addr2};	\
-				fi;"
-
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"console=yes\0"						\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
-	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
-	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
-	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
-	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
-	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.90.10\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvbc-p-rfs\0"			\
-	"zcip=no\0"						\
-	"netboot=yes\0"						\
-	"mvtest=Ff\0"						\
-	"tried_bootfromflash=no\0"				\
-	"tried_bootfromnet=no\0"				\
-	"use_dhcp=yes\0"					\
-	"gev_start=yes\0"					\
-	"mvbcdma_debug=0\0"					\
-	"mvbcia_debug=0\0"					\
-	"propdev_debug=0\0"					\
-	"gevss_debug=0\0"					\
-	"watchdog=1\0"						\
-	"sensor_cnt=1\0"					\
-	""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-
-/*
- * Flash configuration
- */
-#undef 	CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef	CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_ADDR		0xFFFE0000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE	1
-#define CONFIG_SYS_I2C_SPEED	86000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_E1000
-#define CONFIG_E1000_FALLBACK_MAC	{ 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
-#undef CONFIG_MPC5xxx_FEC
-#undef CONFIG_PHY_ADDR
-#define CONFIG_NETDEV		eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef 	CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00800000
-#define CONFIG_SYS_MEMTEST_END		0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 	0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x20000004
-
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS	0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA	1
-#define CONFIG_FPGA_CYCLON2	1
-#define CONFIG_FPGA_COUNT	1
-
-#endif
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
deleted file mode 100644
index 1ee4d7cc33..0000000000
--- a/include/configs/MVBLM7.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright (C) Matrix Vision GmbH 2008
- *
- * Matrix Vision mvBlueLYNX-M7 configuration file
- * based on Freescale's MPC8349ITX.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300	1
-#define CONFIG_MPC834x	1
-#define CONFIG_MPC8343	1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_SYS_IMMR		0xE0000000
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_TSEC_ENET
-#define CONFIG_MPC8XXX_SPI
-#define CONFIG_HARD_SPI
-#define MVBLM7_MMC_CS   0x04000000
-#define CONFIG_MISC_INIT_R
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	100000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	100000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-/*
- * DDR Setup
- */
-#undef	CONFIG_SPD_EEPROM
-
-#define CONFIG_SYS_DDR_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0	1
-#define CONFIG_SYS_MEMTEST_START	(60<<20)
-#define CONFIG_SYS_MEMTEST_END		(70<<20)
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_DDRCDR		(DDRCDR_PZ_HIZ \
-					| DDRCDR_NZ_HIZ \
-					| DDRCDR_Q_DRN)
-					/* 0x22000001 */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_SIZE		512
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
-
-#define CONFIG_SYS_DDR_TIMING_0		0x00260802
-#define CONFIG_SYS_DDR_TIMING_1		0x3837c322
-#define CONFIG_SYS_DDR_TIMING_2		0x0f9848c6
-#define CONFIG_SYS_DDR_TIMING_3		0x00000000
-
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080008
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_INTERVAL		0x02000100
-
-#define CONFIG_SYS_DDR_MODE		0x04040242
-#define CONFIG_SYS_DDR_MODE2		0x00800000
-
-/* Flash */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE		0xFF800000
-#define CONFIG_SYS_FLASH_SIZE		8
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16 \
-				| BR_MS_GPCM \
-				| BR_V)
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET \
-				| OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
-
-/*
- * U-Boot memory configuration
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#undef	CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-
-/*
- * Local Bus LCRR and LBCR regs
- *  LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT	0x32000000
-/* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR	0x20000000
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CONSOLE		ttyS0
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-#define MV_DTB_NAME	"mvblm7.dtb"
-
-/*
- * PCI
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCI1_MMIO_BASE	\
-			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000
-#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000
-
-#define CONFIG_NET_RETRY_COUNT	3
-
-#define CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN	66666667
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-/* TSEC */
-#define CONFIG_GMII
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define	CONFIG_SYS_VSC8601_SKEW_TX	3
-#define	CONFIG_SYS_VSC8601_SKEW_RX	3
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_FEC1_PHY_NORXERR
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define TSEC1_PHY_ADDR		0x10
-#define TSEC1_PHYIDX		0
-#define TSEC1_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME	"TSEC1"
-#define CONFIG_FEC2_PHY_NORXERR
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-#define TSEC2_PHY_ADDR		0x11
-#define TSEC2_PHYIDX		0
-#define TSEC2_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME		"TSEC0"
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/* USB */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * Environment
- */
-#undef  CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0xFF800000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_USB
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR	0x200000
-
-#define CONFIG_SYS_PROMPT	"mvBL-M7> "
-#define CONFIG_SYS_CBSIZE	256
-
-#define CONFIG_SYS_PBSIZE	\
-			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-				/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-
-#define CONFIG_SYS_HRCW_LOW	0x0
-#define CONFIG_SYS_HRCW_HIGH	0x0
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
-
-/* clocking */
-#define CONFIG_SYS_SCCR_ENCCM		0
-#define CONFIG_SYS_SCCR_USBMPHCM	0
-#define	CONFIG_SYS_SCCR_USBDRCM	2
-#define CONFIG_SYS_SCCR_TSEC1CM	1
-#define CONFIG_SYS_SCCR_TSEC2CM	1
-
-#define CONFIG_SYS_SICRH	0x1fef0003
-#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2	HID2_HBE
-#define CONFIG_HIGH_BATS	1
-
-/* DDR  */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* PCI  */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* no PCI2 */
-#define CONFIG_SYS_IBAT3L	0
-#define CONFIG_SYS_IBAT3U	0
-#define CONFIG_SYS_IBAT4L	0
-#define CONFIG_SYS_IBAT4U	0
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
-				| BATL_PP_RW \
-				| BATL_CACHEINHIBIT \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-
-/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
-#define CONFIG_SYS_IBAT6L	(0xF0000000 \
-				| BATL_PP_RW \
-				| BATL_MEMCOHERENCE \
-				| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U	(0xF0000000 \
-				| BATU_BL_256M \
-				| BATU_VS \
-				| BATU_VP)
-#define CONFIG_SYS_IBAT7L	0
-#define CONFIG_SYS_IBAT7U	0
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV		eth0
-
-/* Default path and filenames */
-#define CONFIG_BOOTDELAY		5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		1000
-
-#define MV_CI			"mvBL-M7"
-#define MV_VCI			"mvBL-M7"
-#define MV_FPGA_DATA		0xfff40000
-#define MV_FPGA_SIZE		0
-#define MV_KERNEL_ADDR		0xff810000
-#define MV_INITRD_ADDR		0xffb00000
-#define MV_SCRIPT_ADDR		0xff804000
-#define MV_SCRIPT_ADDR2		0xff806000
-#define MV_DTB_ADDR		0xff808000
-#define MV_INITRD_LENGTH	0x00400000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_DTB_ADDR_RAM		0x00600000
-#define MV_INITRD_ADDR_RAM	0x01000000
-
-#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; "		\
-					"then source ${script_addr}; "	\
-					"else source ${script_addr2}; "	\
-				"fi;"
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"		\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
-	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
-	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" MV_CI "\0"				\
-	"dhcp_vendor-class-identifier=" MV_VCI "\0"		\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.90.10\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvBL-M7-rfs\0"			\
-	"zcip=no\0"						\
-	"netboot=yes\0"						\
-	"mvtest=Ff\0"						\
-	"tried_bootfromflash=no\0"				\
-	"tried_bootfromnet=no\0"				\
-	"bootfile=mvblm72625.boot\0"				\
-	"use_dhcp=yes\0"					\
-	"gev_start=yes\0"					\
-	"mvbcdma_debug=0\0"					\
-	"mvbcia_debug=0\0"					\
-	"propdev_debug=0\0"					\
-	"gevss_debug=0\0"					\
-	"watchdog=0\0"						\
-	"usb_dr_mode=host\0"					\
-	"sensor_cnt=2\0"					\
-	""
-
-#define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
deleted file mode 100644
index 27f730d84b..0000000000
--- a/include/configs/MVSMR.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2010
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 	1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#endif
-#define CONFIG_SYS_LDSCRIPT	"board/matrix_vision/mvsmr/u-boot.lds"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_PSC_CONSOLE	1
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200,\
-						230400}
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#undef	CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-#define CONFIG_HIGH_BATS	1
-
-#define MV_CI			mvSMR
-#define MV_VCI			mvSMR
-#define MV_FPGA_DATA		0xff840000
-#define MV_FPGA_SIZE		0x1ff88
-#define MV_KERNEL_ADDR		0xfff00000
-#define MV_SCRIPT_ADDR		0xff806000
-#define MV_INITRD_ADDR		0xff880000
-#define MV_INITRD_LENGTH	0x00240000
-#define MV_SCRATCH_ADDR		0xffcc0000
-#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_INITRD_ADDR_RAM	0x00400000
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR 	"abcdefg"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_BOOTCOMMAND      "source ${script_addr}"
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs" \
-					" allocate=6M"
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"console=no\0"						\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
-	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
-	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.0.101\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvsmr-rfs\0"			\
-	"zcip=yes\0"						\
-	"netboot=no\0"						\
-	""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-
-/*
- * Flash configuration
- */
-#undef 	CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef	CONFIG_SYS_FLASH_PROTECTION
-#define	CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-
-/* used by linker script to wrap code around */
-#define CONFIG_SCRIPT_OFFSET	0x6000
-#define CONFIG_SCRIPT_SECT_SIZE	0x2000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE	1
-#define CONFIG_SYS_I2C_SPEED	86000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_NETDEV		eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef 	CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00800000
-#define CONFIG_SYS_MEMTEST_END		0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 		0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00050044
-
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS	0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX	1
-#define CONFIG_FPGA_SPARTAN2	1
-#define CONFIG_FPGA_COUNT	1
-
-#endif
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index d823b0f3cc..3ca204e1e2 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -21,6 +21,8 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF00000
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Serial Console Configuration */
 #define	CONFIG_5xx_CONS_SCI1
 #undef	CONFIG_5xx_CONS_SCI2
@@ -96,6 +98,7 @@
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
 
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /***********************************************************************
  * Last Stage Init
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index a6f505aaa9..9a1b2acac3 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -21,6 +21,8 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /***********************************************************
  * Clock
  ***********************************************************/
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index d40185e1e2..a97f5faae4 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -28,6 +28,8 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x0
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /* input clock of PLL (VCMA9 has 12MHz input clock) */
@@ -214,7 +216,6 @@
 
 /* File system */
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_JFFS2
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index e2f7ead9bc..476430ddd0 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -223,6 +223,7 @@
 /* Bootcount using the RTC block */
 #define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
 
 /* USB gadget RNDIS */
 #define CONFIG_SPL_MUSB_NEW_SUPPORT
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index c22d6d0c75..1bf8390722 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -125,7 +125,6 @@
  */
 #define CONFIG_DESIGNWARE_ETH
 #define CONFIG_DW_AUTONEG
-#define CONFIG_DW_SEARCH_PHY
 #define CONFIG_NET_MULTI
 
 /*
diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h
deleted file mode 100644
index 8bd71c6a15..0000000000
--- a/include/configs/bluestone.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * bluestone.h - configuration for Bluestone (APM821XX)
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_APM821XX		1	/* APM821XX series    */
-#define CONFIG_HOSTNAME		bluestone
-
-#define CONFIG_440		1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-#define CONFIG_SYS_CLK_FREQ	50000000
-
-#define CONFIG_BOARD_TYPES		1	/* support board types */
-#define CONFIG_BOARD_EARLY_INIT_F	1       /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R		1       /* Call misc_init_r */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-/* EBC stuff */
-/* later mapped to this addr */
-#define CONFIG_SYS_FLASH_BASE		0xFFF00000
-#define CONFIG_SYS_FLASH_SIZE		(4 << 20)	/* 1MB usable */
-
-/* EBC Boot Space: 0xFF000000 */
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000
-#define CONFIG_SYS_OCM_BASE		0xE3000000 /* OCM: 32k             */
-#define CONFIG_SYS_SRAM_BASE		0xE8000000 /* SRAM: 256k           */
-#define CONFIG_SYS_AHB_BASE		0xE2000000 /* internal AHB peripherals*/
-
-#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM    */
-#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI	/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-/* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-/* max number of sectors on one chip    */
-#define CONFIG_SYS_MAX_FLASH_SECT	80
-/* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
-/* Timeout for Flash Write (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-/* use buffered writes (20x faster)     */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector  */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector   */
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/* SDRAM */
-#define CONFIG_SPD_EEPROM	1       /* Use SPD EEPROM for setup     */
-#define SPD_EEPROM_ADDRESS	{0x53, 0x51}	/* SPD i2c spd addresses */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
-#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
-#define CONFIG_DDR_ECC		1	/* with ECC support             */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* Data sheet */
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_NONE_RGMII
-#define CONFIG_HAS_ETH0
-/* PHY address, See schematics  */
-#define CONFIG_PHY_ADDR			0x1f
-/* reset phy upon startup       */
-#define CONFIG_PHY_RESET		1
-/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_GIGE			1
-#define CONFIG_PHY_DYNAMIC_ANEG		1
-
-/*
- * External Bus Controller (EBC) Setup
- **/
-#define CONFIG_SYS_EBC_CFG	(EBC_CFG_LE_LOCK    |	\
-				 EBC_CFG_PTD_ENABLE   |	\
-				 EBC_CFG_RTC_2048PERCLK | \
-				 EBC_CFG_ATC_HI | \
-				 EBC_CFG_DTC_HI | \
-				 EBC_CFG_CTC_HI | \
-				 EBC_CFG_OEO_PREVIOUS)
-/* NOR Flash */
-#define CONFIG_SYS_EBC_PB0AP 	(EBC_BXAP_BME_DISABLED   | \
-				EBC_BXAP_TWT_ENCODE(64)  | \
-				EBC_BXAP_BCE_DISABLE    | \
-				EBC_BXAP_BCT_2TRANS     | \
-				EBC_BXAP_CSN_ENCODE(1)  | \
-				EBC_BXAP_OEN_ENCODE(2)  | \
-				EBC_BXAP_WBN_ENCODE(2)  | \
-				EBC_BXAP_WBF_ENCODE(2)  | \
-				EBC_BXAP_TH_ENCODE(7)   | \
-				EBC_BXAP_SOR_DELAYED    | \
-				EBC_BXAP_BEM_WRITEONLY  | \
-				EBC_BXAP_PEN_DISABLED)
-/* Peripheral Bank Configuration Register - EBC_BxCR */
-#define CONFIG_SYS_EBC_PB0CR	\
-			(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
-			EBC_BXCR_BS_1MB                | \
-			EBC_BXCR_BU_RW                  | \
-			EBC_BXCR_BW_8BIT)
-
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index e66f30655d..b17e495f5f 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -151,7 +151,7 @@
 			"run mmcboot;" \
 		"fi;" \
 		"if run loadzimage; then " \
-			"if test $fdtfile; then " \
+			"if test -z \"${fdtfile}\"; then " \
 				"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
 			"fi;" \
 			"if run loadfdt; then " \
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 7e2ecd53f5..e8dc462f14 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -72,7 +72,6 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
-#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_CMD_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index bf9752f874..1ce0965912 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -231,7 +231,7 @@
 #define CONFIG_MUSB_GADGET
 #define CONFIG_MUSB_PIO_ONLY
 #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DUALSPEED
+#undef CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_MUSB_HOST
 
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
new file mode 100644
index 0000000000..49504dcafb
--- /dev/null
+++ b/include/configs/socfpga_common.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Virtual target or real hardware */
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#define CONFIG_ARMV7
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SOCFPGA
+
+/*
+ * High level configuration
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CLOCKS
+
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x0
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+#define CONFIG_SYS_INIT_SP_ADDR					\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -	\
+	GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000040
+#endif
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Cache
+ */
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * Ethernet on SoC (EMAC)
+ */
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_MII
+#define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_GIGE
+#endif
+
+/*
+ * FPGA Driver
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_SOCFPGA
+#define CONFIG_FPGA_COUNT		1
+#endif
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE		2400000
+#else
+#define CONFIG_SYS_TIMER_RATE		25000000
+#endif
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	12000
+#endif
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
+/* FIXME */
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
+#endif
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_NS16550_CLK		1000000
+#else
+#define CONFIG_SYS_NS16550_CLK		100000000
+#endif
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * U-Boot environment
+ */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			4096
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)	/* FIXME */
+#define CONFIG_SYS_SPL_MALLOC_START	((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(&__malloc_end - &__malloc_start)
+
+#define CHUNKSZ_CRC32			(1 * 1024)	/* FIXME: ewww */
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 5d145cd821..8d54bf892d 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -1,287 +1,100 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_H__
 
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
 #include "../../board/altera/socfpga/iocsr_config.h"
 #include "../../board/altera/socfpga/pll_config.h"
 
-/*
- * High level configuration
- */
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
-#define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_USE_IRQ
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SINGLE_BOOTLOADER
-#define CONFIG_SOCFPGA
-
-/* base address for .text section */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TEXT_BASE		0x08000040
-#else
-#define CONFIG_SYS_TEXT_BASE		0x01000040
-#endif
-#define CONFIG_SYS_LOAD_ADDR		0x7fc0
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		256
-/* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/*
- * Display CPU and Board Info
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/*
- * Enable early stage initialization at C environment
- */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* flat device tree */
-#define CONFIG_OF_LIBFDT
-/* skip updating the FDT blob */
-#define CONFIG_FDT_BLOB_SKIP_UPDATE
-/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
-#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
-
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
-#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
-
-/*
- * Memory allocation (MALLOC)
- */
-/* Room required on the stack for the environment data */
-#define CONFIG_ENV_SIZE			1024
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/* SP location before relocation, must use scratch RAM */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-/* Reserving 0x100 space at back of scratch RAM for debug info */
-#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
-/* Stack pointer prior relocation, must situated at on-chip RAM */
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Command line configuration.
- */
+/* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH
 #include <config_cmd_default.h>
-/* FAT file system support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
 
+#define CONFIG_REGEX			/* Enable regular expression support */
 
-/*
- * Misc
- */
-#define CONFIG_DOS_PARTITION            1
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #endif
+#define CONFIG_LOADADDR		0x8000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
-/*
- * Environment setup
- */
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC0_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+#define CONFIG_EPHY0_PHY_ADDR		0
 
-/* Delay before automatically booting the default image */
-#define CONFIG_BOOTDELAY		3
-/* Enable auto completion of commands using TAB */
-#define CONFIG_AUTO_COMPLETE
-/* use "hush" command parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_CMD_RUN
+/* PHY */
+#define CONFIG_EPHY1_PHY_ADDR		4
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
 
-#define CONFIG_BOOTCOMMAND "run ramboot"
+#endif
 
-/*
- * arguments passed to the bootm command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will overide also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
+/* Extra Environment */
+#define CONFIG_HOSTNAME		socfpga_cyclone5
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=uImage\0" \
+	"bootimage=zImage\0" \
 	"fdt_addr=100\0" \
-	"fsloadcmd=ext2load\0" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
 	"qspiroot=/dev/mtdblock0\0" \
 	"qspirootfstype=jffs2\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
 
-/* using environment setting for stdin, stdout, stderr */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-/* Enable the call to overwrite_console() */
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-/* Enable overwrite of previous console environment settings */
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-
-/* max number of command args	 */
-#define CONFIG_SYS_MAXARGS		16
-
-
-/*
- * Hardware drivers
- */
-
-/*
- * SDRAM Memory Map
- */
-/* We have 1 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS		1
-/* SDRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE		0x40000000
-
-#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START	0x00000000
-#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
-
-/*
- * NS16550 Configuration
- */
-#define UART0_BASE			SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
-#define CONFIG_CONS_INDEX               1
-#define CONFIG_SYS_NS16550_COM1		UART0_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define V_NS16550_CLK			1000000
-#else
-#define V_NS16550_CLK			100000000
-#endif
-#define CONFIG_BAUDRATE			115200
-
-/*
- * FLASH
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * L4 OSC1 Timer 0
- */
-/* This timer use eosc1 where the clock frequency is fixed
- * throughout any condition */
-#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
-/* reload value when timer count to zero */
-#define TIMER_LOAD_VAL			0xFFFFFFFF
-/* Timer info */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE		2400000
-#else
-#define CONFIG_SYS_TIMER_RATE		25000000
-#endif
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
-
-#define CONFIG_ENV_IS_NOWHERE
-
-/*
- * network support
- */
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_DESIGNWARE_ETH          1
-#endif
-
-#ifdef CONFIG_DESIGNWARE_ETH
-#define CONFIG_EMAC0_BASE              SOCFPGA_EMAC0_ADDRESS
-#define CONFIG_EMAC1_BASE              SOCFPGA_EMAC1_ADDRESS
-/* console support for network */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-/* designware */
-#define CONFIG_NET_MULTI
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_MII
-#define CONFIG_PHY_GIGE
-#define CONFIG_DW_AUTONEG
-#define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-/* EMAC controller and PHY used */
-#define CONFIG_EMAC_BASE               CONFIG_EMAC1_BASE
-#define CONFIG_EPHY_PHY_ADDR           CONFIG_EPHY1_PHY_ADDR
-#define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
-#endif /* CONFIG_DESIGNWARE_ETH */
-
-/*
- * L4 Watchdog
- */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
-#define CONFIG_DESIGNWARE_WATCHDOG
-#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
-/* Clocks source frequency to watchdog timer */
-#define CONFIG_DW_WDT_CLOCK_KHZ		25000
-
-
-/*
- * SPL "Second Program Loader" aka Initial Software
- */
-
-/* Enable building of SPL globally */
-#define CONFIG_SPL_FRAMEWORK
-
-/* TEXT_BASE for linking the SPL binary */
-#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
-
-/* Stack size for SPL */
-#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
-
-/* MALLOC size for SPL */
-#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
-
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-
-#define CHUNKSZ_CRC32			(1 * 1024)
-
-#define CONFIG_CRC32_VERIFY
-
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
-
-/* Support for common/libcommon.o in SPL binary */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-/* Support for lib/libgeneric.o in SPL binary */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
-/* Support for watchdog */
-#define CONFIG_SPL_WATCHDOG_SUPPORT
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
 
-#endif	/* __CONFIG_H */
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_H__ */
diff --git a/include/dwmmc.h b/include/dwmmc.h
index b67f11b113..109f7c8ac7 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -157,7 +157,7 @@ struct dwmci_idmac {
 	u32 cnt;
 	u32 addr;
 	u32 next_addr;
-};
+} __aligned(ARCH_DMA_MINALIGN);
 
 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
 {
diff --git a/include/image.h b/include/image.h
index 340105658c..4347532520 100644
--- a/include/image.h
+++ b/include/image.h
@@ -232,6 +232,7 @@ struct lmb;
 #define IH_TYPE_MXSIMAGE	16	/* Freescale MXSBoot Image	*/
 #define IH_TYPE_GPIMAGE		17	/* TI Keystone GPHeader Image	*/
 #define IH_TYPE_ATMELIMAGE	18	/* ATMEL ROM bootable Image	*/
+#define IH_TYPE_SOCFPGAIMAGE	19	/* Altera SOCFPGA Preloader	*/
 
 /*
  * Compression Types
diff --git a/include/net.h b/include/net.h
index 735b0b9d26..18d279ebe7 100644
--- a/include/net.h
+++ b/include/net.h
@@ -3,7 +3,7 @@
  *
  *	Copyright 1994 - 2000 Neil Russell.
  *	(See License)
- *
+ *	SPDX-License-Identifier:	GPL-2.0
  *
  * History
  *	9/16/00	  bor  adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 268de8ea70..24da23fe50 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -103,8 +103,8 @@ int stdio_init(void);
 
 void	stdio_print_current_devices(void);
 #ifdef CONFIG_SYS_STDIO_DEREGISTER
-int	stdio_deregister(const char *devname);
-int stdio_deregister_dev(struct stdio_dev *dev);
+int stdio_deregister(const char *devname, int force);
+int stdio_deregister_dev(struct stdio_dev *dev, int force);
 #endif
 struct list_head* stdio_get_list(void);
 struct stdio_dev* stdio_get_by_name(const char* name);
diff --git a/include/usb.h b/include/usb.h
index d9fedeeff7..c355fbe481 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -216,7 +216,7 @@ int usb_host_eth_scan(int mode);
 #ifdef CONFIG_USB_KEYBOARD
 
 int drv_usb_kbd_init(void);
-int usb_kbd_deregister(void);
+int usb_kbd_deregister(int force);
 
 #endif
 /* routines */