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| author | TsiChung Liew <tsicliew@gmail.com> | 2009-06-11 15:39:57 +0000 |
|---|---|---|
| committer | TsiChung Liew <Tsi-Chung.Liew@freescale.com> | 2009-07-14 09:27:14 -0500 |
| commit | 709b384b6493d9726dce20663ebe31bf7cab2925 (patch) | |
| tree | e4c685869604d834cc30d67186ec23e55d817c18 /include/configs/M54451EVB.h | |
| parent | bbf6bbffcaf694c03504c661e58fbd1aefe5bf64 (diff) | |
| download | blackbird-obmc-uboot-709b384b6493d9726dce20663ebe31bf7cab2925.tar.gz blackbird-obmc-uboot-709b384b6493d9726dce20663ebe31bf7cab2925.zip | |
ColdFire: Update for M54451EVB
Update serial boot DRAM's Internal RAM, vector table and DRAM in
start.S, serial flash's read status command over SPI and NOR
flash.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Diffstat (limited to 'include/configs/M54451EVB.h')
| -rw-r--r-- | include/configs/M54451EVB.h | 39 |
1 files changed, 17 insertions, 22 deletions
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 45f701652f..cc57da816b 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -70,6 +70,7 @@ #define CONFIG_CMD_MISC #define CONFIG_CMD_MII #define CONFIG_CMD_NET +#define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SPI @@ -163,7 +164,7 @@ #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI @@ -175,7 +176,7 @@ # define CONFIG_SPI_FLASH # define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ +# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ DSPI_DCTAR_CPOL | \ DSPI_DCTAR_CPHA | \ DSPI_DCTAR_PCSSCK_1CLK | \ @@ -191,7 +192,7 @@ /* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK -#define CONFIG_PRAM 2048 /* 2048 KB */ +#define CONFIG_PRAM 2048 /* 2048 KB */ #define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -209,7 +210,7 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CONFIG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -265,7 +266,7 @@ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#if defined(CONFIG_CF_SBF) +#if defined(CONFIG_SYS_STMICRO_BOOT) # define CONFIG_ENV_IS_IN_SPI_FLASH 1 # define CONFIG_ENV_SPI_CS 1 # define CONFIG_ENV_OFFSET 0x20000 @@ -273,8 +274,9 @@ # define CONFIG_ENV_SECT_SIZE 0x10000 #else # define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -# define CONFIG_ENV_SECT_SIZE 0x2000 +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000) +# define CONFIG_ENV_SIZE 0x2000 +# define CONFIG_ENV_SECT_SIZE 0x8000 #endif #undef CONFIG_ENV_OVERWRITE #undef CONFIG_ENV_IS_EMBEDDED @@ -286,8 +288,7 @@ # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT +#else # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_SER_FLASH_BASE @@ -297,6 +298,7 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -311,27 +313,20 @@ * This is setting for JFFS2 support in u-boot. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ -#ifdef CONFIG_SYS_SPANSION_BOOT -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) -#endif -#ifdef CONFIG_SYS_STMICRO_BOOT +#ifdef CONFIG_CMD_JFFS2 # define CONFIG_JFFS2_DEV "nor0" # define CONFIG_JFFS2_PART_SIZE 0x01000000 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ +/* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 /*----------------------------------------------------------------------- * Memory bank definitions */ /* - * CS0 - NOR Flash 8MB + * CS0 - NOR Flash 16MB * CS1 - Available * CS2 - Available * CS3 - Available @@ -339,10 +334,10 @@ * CS5 - Available */ - /* SPANSION Flash */ + /* Flash */ #define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x007F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001180 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00004D80 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE |
