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authorMarek Vasut <marex@denx.de>2015-07-12 20:49:39 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:11 +0200
commit6cb9f167817a30b9d8d482023164d4a3ca458501 (patch)
tree7491db143165a844a1091e3478fab78e7f6098c8 /drivers/ddr/altera/sequencer.h
parent17fdc9167fd8598d49f8edc930a5e5e649bd1299 (diff)
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ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
Use the proper structure which describes these registers, especially since this is already in place. Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/ddr/altera/sequencer.h')
-rw-r--r--drivers/ddr/altera/sequencer.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 7591d40728..5d4d80016d 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -99,10 +99,6 @@
#define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
-
#define PHY_MGR_CAL_RESET (0)
#define PHY_MGR_CAL_SUCCESS (1)
#define PHY_MGR_CAL_FAIL (2)
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