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| author | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:24:54 +0200 |
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| committer | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:25:13 +0200 |
| commit | dc557e9a1fe00ca9d884bd88feef5bebf23fede4 (patch) | |
| tree | ec09fdf8f7c4c44e30f4b38b7459a2cbbb71d094 /board/freescale/ls1012aqds/README | |
| parent | d2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4 (diff) | |
| parent | 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff) | |
| download | blackbird-obmc-uboot-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.tar.gz blackbird-obmc-uboot-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.zip | |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/freescale/ls1012aqds/README')
| -rw-r--r-- | board/freescale/ls1012aqds/README | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README new file mode 100644 index 0000000000..dee4b302c1 --- /dev/null +++ b/board/freescale/ls1012aqds/README @@ -0,0 +1,59 @@ +Overview +-------- +QorIQ LS1012A Development System (LS1012AQDS) is a high-performance +development platform, with a complete debugging environment. +The LS1012AQDS board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A +SoC overview. + +LS1012AQDS board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + - QSPI Controller + - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to QSPI NOR flash memory (2 virtual banks) and the QSPI + emulator + - USB 3.0 + - One USB 3.0 controller with integrated PHY + - One high-speed USB 3.0 port + - USB 2.0 + - One USB 2.0 controller with ULPI interface + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices + - 2 I2C controllers + - One SATA onboard connectors + - UART + - 5 SAI + - One SAI port with audio codec SGTL5000: + • Provides MIC bias + • Provides headphone and line output + - One SAI port terminated at 2x6 header + - Three SAI Tx/Rx ports terminated at 2x3 headers + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 |
