powerpc/mpc8xxx: Merge entries in DDR speed table

It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.

Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.

Removed ODT overriding for P2020DS as it is not necessary.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 97 insertions, 125 deletions

diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 3b4dfa3f8c..4a53b8d933 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -107,166 +107,138 @@ phys_size_t fixed_sdram(void)
 	return ddr_size;
 }
 
-typedef struct {
-	u32 datarate_mhz_low;
-	u32 datarate_mhz_high;
+struct board_specific_parameters {
 	u32 n_ranks;
+	u32 datarate_mhz_high;
 	u32 clk_adjust;
 	u32 wrlvl_start;
 	u32 cpo;
 	u32 write_data_delay;
 	u32 force_2T;
-} board_specific_parameters_t;
+};
 
-const board_specific_parameters_t board_specific_parameters_udimm[][30] = {
-	{
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
-	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
-	 * mhz| mhz|ranks|adjst| start |      |delay |
+	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |      |delay |
 	 */
-		{  0, 850,    4,    4,     6,   0xff,    2,  0},
-		{851, 950,    4,    5,     7,   0xff,    2,  0},
-		{951, 1050,   4,    5,     8,   0xff,    2,  0},
-		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
-		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
-		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
-		{  0, 850,    2,    5,     6,   0xff,    2,  0},
-		{851, 950,    2,    5,     7,   0xff,    2,  0},
-		{951, 1050,   2,    5,     7,   0xff,    2,  0},
-		{1051, 1250,  2,    4,     6,   0xff,    2,  0},
-		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
-		{1351, 1666,  2,    5,     8,   0xff,    2,  0},
-		{  0, 850,    1,    4,     5,   0xff,    2,  0},
-		{851, 950,    1,    4,     7,   0xff,    2,  0},
-		{951, 1050,   1,    4,     8,   0xff,    2,  0},
-		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
-		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
-		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
-	},
+	{4,   850,    4,     6,   0xff,    2,  0},
+	{4,   950,    5,     7,   0xff,    2,  0},
+	{4,  1050,    5,     8,   0xff,    2,  0},
+	{4,  1250,    5,    10,   0xff,    2,  0},
+	{4,  1350,    5,    11,   0xff,    2,  0},
+	{4,  1666,    5,    12,   0xff,    2,  0},
+	{2,   850,    5,     6,   0xff,    2,  0},
+	{2,  1050,    5,     7,   0xff,    2,  0},
+	{2,  1250,    4,     6,   0xff,    2,  0},
+	{2,  1350,    5,     7,   0xff,    2,  0},
+	{2,  1666,    5,     8,   0xff,    2,  0},
+	{1,   850,    4,     5,   0xff,    2,  0},
+	{1,   950,    4,     7,   0xff,    2,  0},
+	{1,  1666,    4,     8,   0xff,    2,  0},
+	{}
+};
 
-	{
-	/*
-	 * memory controller 1
-	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
-	 * mhz| mhz|ranks|adjst| start |      |delay |
-	 */
-		{  0, 850,    4,    4,     6,   0xff,    2,  0},
-		{851, 950,    4,    5,     7,   0xff,    2,  0},
-		{951, 1050,   4,    5,     8,   0xff,    2,  0},
-		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
-		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
-		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
-		{  0, 850,    2,    5,     6,   0xff,    2,  0},
-		{851, 950,    2,    5,     7,   0xff,    2,  0},
-		{951, 1050,   2,    5,     7,   0xff,    2,  0},
-		{1051, 1250,  2,    4,     6,   0xff,    2,  0},
-		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
-		{1351, 1666,  2,    5,     8,   0xff,    2,  0},
-		{  0, 850,    1,    4,     5,   0xff,    2,  0},
-		{851, 950,    1,    4,     7,   0xff,    2,  0},
-		{951, 1050,   1,    4,     8,   0xff,    2,  0},
-		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
-		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
-		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
-	}
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+	udimm0,
 };
 
-const board_specific_parameters_t board_specific_parameters_rdimm[][30] = {
-	{
+static const struct board_specific_parameters rdimm0[] = {
 	/*
 	 * memory controller 0
-	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
-	 * mhz| mhz|ranks|adjst| start |      |delay |
+	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |      |delay |
 	 */
-		{  0, 850,    4,    4,     6,   0xff,    2,  0},
-		{851, 950,    4,    5,     7,   0xff,    2,  0},
-		{951, 1050,   4,    5,     8,   0xff,    2,  0},
-		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
-		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
-		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
-		{  0, 850,    2,    4,     6,   0xff,    2,  0},
-		{851, 950,    2,    4,     7,   0xff,    2,  0},
-		{951, 1050,   2,    4,     7,   0xff,    2,  0},
-		{1051, 1250,  2,    4,     8,   0xff,    2,  0},
-		{1251, 1350,  2,    4,     8,   0xff,    2,  0},
-		{1351, 1666,  2,    4,     8,   0xff,    2,  0},
-		{  0, 850,    1,    4,     5,   0xff,    2,  0},
-		{851, 950,    1,    4,     7,   0xff,    2,  0},
-		{951, 1050,   1,    4,     8,   0xff,    2,  0},
-		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
-		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
-		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
-	},
+	{4,   850,    4,     6,   0xff,    2,  0},
+	{4,   950,    5,     7,   0xff,    2,  0},
+	{4,  1050,    5,     8,   0xff,    2,  0},
+	{4,  1250,    5,    10,   0xff,    2,  0},
+	{4,  1350,    5,    11,   0xff,    2,  0},
+	{4,  1666,    5,    12,   0xff,    2,  0},
+	{2,   850,    4,     6,   0xff,    2,  0},
+	{2,  1050,    4,     7,   0xff,    2,  0},
+	{2,  1666,    4,     8,   0xff,    2,  0},
+	{1,   850,    4,     5,   0xff,    2,  0},
+	{1,   950,    4,     7,   0xff,    2,  0},
+	{1,  1666,    4,     8,   0xff,    2,  0},
+	{}
+};
 
-	{
-	/*
-	 * memory controller 1
-	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
-	 * mhz| mhz|ranks|adjst| start |      |delay |
-	 */
-		{  0, 850,    4,    4,     6,   0xff,    2,  0},
-		{851, 950,    4,    5,     7,   0xff,    2,  0},
-		{951, 1050,   4,    5,     8,   0xff,    2,  0},
-		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
-		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
-		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
-		{  0, 850,    2,    4,     6,   0xff,    2,  0},
-		{851, 950,    2,    4,     7,   0xff,    2,  0},
-		{951, 1050,   2,    4,     7,   0xff,    2,  0},
-		{1051, 1250,  2,    4,     8,   0xff,    2,  0},
-		{1251, 1350,  2,    4,     8,   0xff,    2,  0},
-		{1351, 1666,  2,    4,     8,   0xff,    2,  0},
-		{  0, 850,    1,    4,     5,   0xff,    2,  0},
-		{851, 950,    1,    4,     7,   0xff,    2,  0},
-		{951, 1050,   1,    4,     8,   0xff,    2,  0},
-		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
-		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
-		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
-	}
+/*
+ * The two slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+	rdimm0,
 };
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
-	const board_specific_parameters_t *pbsp;
-	u32 num_params;
-	u32 i;
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 
-	if (popts->registered_dimm_en) {
-		pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]);
-		num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) /
-				sizeof(board_specific_parameters_rdimm[0][0]);
-	} else {
-		pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
-		num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
-				sizeof(board_specific_parameters_udimm[0][0]);
+	if (ctrl_num > 1) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
 	}
+	if (!pdimm->n_ranks)
+		return;
+
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[ctrl_num];
+	else
+		pbsp = udimms[ctrl_num];
+
+
 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
 	ddr_freq = get_ddr_freq(0) / 1000000;
-	for (i = 0; i < num_params; i++) {
-		if (ddr_freq >= pbsp->datarate_mhz_low &&
-			ddr_freq <= pbsp->datarate_mhz_high &&
-			pdimm[0].n_ranks == pbsp->n_ranks) {
-			popts->cpo_override = pbsp->cpo;
-			popts->write_data_delay = pbsp->write_data_delay;
-			popts->clk_adjust = pbsp->clk_adjust;
-			popts->wrlvl_start = pbsp->wrlvl_start;
-			popts->twoT_en = pbsp->force_2T;
-			break;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->twoT_en = pbsp->force_2T;
+				goto found;
+			}
+			pbsp_highest = pbsp;
 		}
 		pbsp++;
 	}
 
-	if (i == num_params) {
-		printf("Warning: board specific timing not found "
-			"for data rate %lu MT/s!\n", ddr_freq);
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s!\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->twoT_en = pbsp_highest->force_2T;
+	} else {
+		panic("DIMM is not supported by this board");
 	}
-
+found:
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed