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-rw-r--r--board/freescale/corenet_ds/ddr.c222
-rw-r--r--board/freescale/mpc8349emds/ddr.c80
-rw-r--r--board/freescale/mpc8572ds/ddr.c203
-rw-r--r--board/freescale/mpc8641hpcn/ddr.c165
-rw-r--r--board/freescale/p1022ds/ddr.c79
-rw-r--r--board/freescale/p2020ds/ddr.c105
-rw-r--r--board/freescale/p2041rdb/ddr.c78
7 files changed, 472 insertions, 460 deletions
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 3b4dfa3f8c..4a53b8d933 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -107,166 +107,138 @@ phys_size_t fixed_sdram(void)
return ddr_size;
}
-typedef struct {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
+struct board_specific_parameters {
u32 n_ranks;
+ u32 datarate_mhz_high;
u32 clk_adjust;
u32 wrlvl_start;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
-} board_specific_parameters_t;
+};
-const board_specific_parameters_t board_specific_parameters_udimm[][30] = {
- {
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
- * mhz| mhz|ranks|adjst| start | |delay |
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
*/
- { 0, 850, 4, 4, 6, 0xff, 2, 0},
- {851, 950, 4, 5, 7, 0xff, 2, 0},
- {951, 1050, 4, 5, 8, 0xff, 2, 0},
- {1051, 1250, 4, 5, 10, 0xff, 2, 0},
- {1251, 1350, 4, 5, 11, 0xff, 2, 0},
- {1351, 1666, 4, 5, 12, 0xff, 2, 0},
- { 0, 850, 2, 5, 6, 0xff, 2, 0},
- {851, 950, 2, 5, 7, 0xff, 2, 0},
- {951, 1050, 2, 5, 7, 0xff, 2, 0},
- {1051, 1250, 2, 4, 6, 0xff, 2, 0},
- {1251, 1350, 2, 5, 7, 0xff, 2, 0},
- {1351, 1666, 2, 5, 8, 0xff, 2, 0},
- { 0, 850, 1, 4, 5, 0xff, 2, 0},
- {851, 950, 1, 4, 7, 0xff, 2, 0},
- {951, 1050, 1, 4, 8, 0xff, 2, 0},
- {1051, 1250, 1, 4, 8, 0xff, 2, 0},
- {1251, 1350, 1, 4, 8, 0xff, 2, 0},
- {1351, 1666, 1, 4, 8, 0xff, 2, 0},
- },
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 5, 6, 0xff, 2, 0},
+ {2, 1050, 5, 7, 0xff, 2, 0},
+ {2, 1250, 4, 6, 0xff, 2, 0},
+ {2, 1350, 5, 7, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0xff, 2, 0},
+ {1, 850, 4, 5, 0xff, 2, 0},
+ {1, 950, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
- {
- /*
- * memory controller 1
- * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
- * mhz| mhz|ranks|adjst| start | |delay |
- */
- { 0, 850, 4, 4, 6, 0xff, 2, 0},
- {851, 950, 4, 5, 7, 0xff, 2, 0},
- {951, 1050, 4, 5, 8, 0xff, 2, 0},
- {1051, 1250, 4, 5, 10, 0xff, 2, 0},
- {1251, 1350, 4, 5, 11, 0xff, 2, 0},
- {1351, 1666, 4, 5, 12, 0xff, 2, 0},
- { 0, 850, 2, 5, 6, 0xff, 2, 0},
- {851, 950, 2, 5, 7, 0xff, 2, 0},
- {951, 1050, 2, 5, 7, 0xff, 2, 0},
- {1051, 1250, 2, 4, 6, 0xff, 2, 0},
- {1251, 1350, 2, 5, 7, 0xff, 2, 0},
- {1351, 1666, 2, 5, 8, 0xff, 2, 0},
- { 0, 850, 1, 4, 5, 0xff, 2, 0},
- {851, 950, 1, 4, 7, 0xff, 2, 0},
- {951, 1050, 1, 4, 8, 0xff, 2, 0},
- {1051, 1250, 1, 4, 8, 0xff, 2, 0},
- {1251, 1350, 1, 4, 8, 0xff, 2, 0},
- {1351, 1666, 1, 4, 8, 0xff, 2, 0},
- }
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm0,
};
-const board_specific_parameters_t board_specific_parameters_rdimm[][30] = {
- {
+static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
- * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
- * mhz| mhz|ranks|adjst| start | |delay |
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
*/
- { 0, 850, 4, 4, 6, 0xff, 2, 0},
- {851, 950, 4, 5, 7, 0xff, 2, 0},
- {951, 1050, 4, 5, 8, 0xff, 2, 0},
- {1051, 1250, 4, 5, 10, 0xff, 2, 0},
- {1251, 1350, 4, 5, 11, 0xff, 2, 0},
- {1351, 1666, 4, 5, 12, 0xff, 2, 0},
- { 0, 850, 2, 4, 6, 0xff, 2, 0},
- {851, 950, 2, 4, 7, 0xff, 2, 0},
- {951, 1050, 2, 4, 7, 0xff, 2, 0},
- {1051, 1250, 2, 4, 8, 0xff, 2, 0},
- {1251, 1350, 2, 4, 8, 0xff, 2, 0},
- {1351, 1666, 2, 4, 8, 0xff, 2, 0},
- { 0, 850, 1, 4, 5, 0xff, 2, 0},
- {851, 950, 1, 4, 7, 0xff, 2, 0},
- {951, 1050, 1, 4, 8, 0xff, 2, 0},
- {1051, 1250, 1, 4, 8, 0xff, 2, 0},
- {1251, 1350, 1, 4, 8, 0xff, 2, 0},
- {1351, 1666, 1, 4, 8, 0xff, 2, 0},
- },
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 4, 6, 0xff, 2, 0},
+ {2, 1050, 4, 7, 0xff, 2, 0},
+ {2, 1666, 4, 8, 0xff, 2, 0},
+ {1, 850, 4, 5, 0xff, 2, 0},
+ {1, 950, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
- {
- /*
- * memory controller 1
- * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
- * mhz| mhz|ranks|adjst| start | |delay |
- */
- { 0, 850, 4, 4, 6, 0xff, 2, 0},
- {851, 950, 4, 5, 7, 0xff, 2, 0},
- {951, 1050, 4, 5, 8, 0xff, 2, 0},
- {1051, 1250, 4, 5, 10, 0xff, 2, 0},
- {1251, 1350, 4, 5, 11, 0xff, 2, 0},
- {1351, 1666, 4, 5, 12, 0xff, 2, 0},
- { 0, 850, 2, 4, 6, 0xff, 2, 0},
- {851, 950, 2, 4, 7, 0xff, 2, 0},
- {951, 1050, 2, 4, 7, 0xff, 2, 0},
- {1051, 1250, 2, 4, 8, 0xff, 2, 0},
- {1251, 1350, 2, 4, 8, 0xff, 2, 0},
- {1351, 1666, 2, 4, 8, 0xff, 2, 0},
- { 0, 850, 1, 4, 5, 0xff, 2, 0},
- {851, 950, 1, 4, 7, 0xff, 2, 0},
- {951, 1050, 1, 4, 8, 0xff, 2, 0},
- {1051, 1250, 1, 4, 8, 0xff, 2, 0},
- {1251, 1350, 1, 4, 8, 0xff, 2, 0},
- {1351, 1666, 1, 4, 8, 0xff, 2, 0},
- }
+/*
+ * The two slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- const board_specific_parameters_t *pbsp;
- u32 num_params;
- u32 i;
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
- if (popts->registered_dimm_en) {
- pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]);
- num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) /
- sizeof(board_specific_parameters_rdimm[0][0]);
- } else {
- pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
- num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
- sizeof(board_specific_parameters_udimm[0][0]);
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
}
+ if (!pdimm->n_ranks)
+ return;
+
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
- for (i = 0; i < num_params; i++) {
- if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high &&
- pdimm[0].n_ranks == pbsp->n_ranks) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twoT_en = pbsp->force_2T;
- break;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
}
pbsp++;
}
- if (i == num_params) {
- printf("Warning: board specific timing not found "
- "for data rate %lu MT/s!\n", ddr_freq);
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
}
-
+found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
index 0209c1eca9..1d9d9959bd 100644
--- a/board/freescale/mpc8349emds/ddr.c
+++ b/board/freescale/mpc8349emds/ddr.c
@@ -26,40 +26,42 @@
#include <asm/fsl_ddr_dimm_params.h>
struct board_specific_parameters {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
u32 n_ranks;
+ u32 datarate_mhz_high;
u32 clk_adjust;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
};
-const struct board_specific_parameters board_specific_parameters_udimm[][20] = {
- {
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
/*
- * memory controller 0
- * lo| hi| num| clk| cpo|wrdata|2T
- * mhz| mhz|ranks|adjst| | delay|
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
*/
- { 0, 300, 2, 4, 4, 2, 0},
- {301, 365, 2, 4, 6, 2, 0},
- {366, 450, 2, 4, 7, 2, 0},
- {451, 850, 2, 4, 31, 2, 0},
- { 0, 300, 1, 4, 4, 2, 0},
- {301, 365, 1, 4, 6, 2, 0},
- {366, 450, 1, 4, 7, 2, 0},
- {451, 850, 1, 4, 31, 2, 0}
- }
+ {2, 300, 4, 4, 2, 0},
+ {2, 365, 4, 6, 2, 0},
+ {2, 450, 4, 7, 2, 0},
+ {2, 850, 4, 31, 2, 0},
+ {1, 300, 4, 4, 2, 0},
+ {1, 365, 4, 6, 2, 0},
+ {1, 450, 4, 7, 2, 0},
+ {1, 850, 4, 31, 2, 0},
+ {}
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- const struct board_specific_parameters *pbsp;
- u32 num_params;
- u32 i, dimm_num;
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ unsigned int i;
ulong ddr_freq;
if (ctrl_num != 0) /* we have only one controller */
@@ -71,33 +73,41 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
return;
- dimm_num = i;
- pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
- num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
- sizeof(board_specific_parameters_udimm[0][0]);
+ pbsp = udimm0;
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
- for (i = 0; i < num_params; i++) {
- if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high &&
- pdimm[dimm_num].n_ranks == pbsp->n_ranks) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->twoT_en = pbsp->force_2T;
- break;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm[i].n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
}
pbsp++;
}
- if (i == num_params) {
- printf("Warning: board specific timing not found "
- "for data rate %lu MT/s!\n", ddr_freq);
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
}
+found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index adcbd58545..a7ff668b1b 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -11,155 +11,156 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-typedef struct {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
+struct board_specific_parameters {
u32 n_ranks;
+ u32 datarate_mhz_high;
u32 clk_adjust;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
-} board_specific_parameters_t;
+};
/*
- * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
*
* For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
* tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
* all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
* For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
* from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
+ *
+ * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
*/
-const board_specific_parameters_t board_specific_parameters_udimm[][20] = {
- {
+static const struct board_specific_parameters udimm0[] = {
/*
- * memory controller 0
- * lo| hi| num| clk| cpo|wrdata|2T
- * mhz| mhz|ranks|adjst| | delay|
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
*/
- { 0, 333, 2, 8, 7, 5, 0},
- {334, 400, 2, 8, 9, 5, 0},
- {401, 549, 2, 8, 11, 5, 0},
- {550, 680, 2, 8, 10, 5, 0},
- {681, 850, 2, 8, 12, 5, 1},
- { 0, 333, 1, 6, 7, 3, 0},
- {334, 400, 1, 6, 9, 3, 0},
- {401, 549, 1, 6, 11, 3, 0},
- {550, 680, 1, 1, 10, 5, 0},
- {681, 850, 1, 1, 12, 5, 0}
- },
+ {2, 333, 8, 7, 5, 0},
+ {2, 400, 8, 9, 5, 0},
+ {2, 549, 8, 11, 5, 0},
+ {2, 680, 8, 10, 5, 0},
+ {2, 850, 8, 12, 5, 1},
+ {1, 333, 6, 7, 3, 0},
+ {1, 400, 6, 9, 3, 0},
+ {1, 549, 6, 11, 3, 0},
+ {1, 680, 1, 10, 5, 0},
+ {1, 850, 1, 12, 5, 0},
+ {}
+};
- {
+static const struct board_specific_parameters udimm1[] = {
/*
- * memory controller 1
- * lo| hi| num| clk| cpo|wrdata|2T
- * mhz| mhz|ranks|adjst| | delay|
+ * memory controller 1
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
*/
- { 0, 333, 2, 8, 7, 5, 0},
- {334, 400, 2, 8, 9, 5, 0},
- {401, 549, 2, 8, 11, 5, 0},
- {550, 680, 2, 8, 11, 5, 0},
- {681, 850, 2, 8, 13, 5, 1},
- { 0, 333, 1, 6, 7, 3, 0},
- {334, 400, 1, 6, 9, 3, 0},
- {401, 549, 1, 6, 11, 3, 0},
- {550, 680, 1, 1, 11, 6, 0},
- {681, 850, 1, 1, 13, 6, 0}
- }
+ {2, 333, 8, 7, 5, 0},
+ {2, 400, 8, 9, 5, 0},
+ {2, 549, 8, 11, 5, 0},
+ {2, 680, 8, 11, 5, 0},
+ {2, 850, 8, 13, 5, 1},
+ {1, 333, 6, 7, 3, 0},
+ {1, 400, 6, 9, 3, 0},
+ {1, 549, 6, 11, 3, 0},
+ {1, 680, 1, 11, 6, 0},
+ {1, 850, 1, 13, 6, 0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm1,
};
-const board_specific_parameters_t board_specific_parameters_rdimm[][20] = {
- {
+static const struct board_specific_parameters rdimm0[] = {
/*
- * memory controller 0
- * lo| hi| num| clk| cpo|wrdata|2T
- * mhz| mhz|ranks|adjst| | delay|
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
*/
- { 0, 333, 2, 4, 7, 3, 0},
- {334, 400, 2, 4, 9, 3, 0},
- {401, 549, 2, 4, 11, 3, 0},
- {550, 680, 2, 4, 10, 3, 0},
- {681, 850, 2, 4, 12, 3, 1},
- },
+ {2, 333, 4, 7, 3, 0},
+ {2, 400, 4, 9, 3, 0},
+ {2, 549, 4, 11, 3, 0},
+ {2, 680, 4, 10, 3, 0},
+ {2, 850, 4, 12, 3, 1},
+ {}
+};
- {
+static const struct board_specific_parameters rdimm1[] = {
/*
- * memory controller 1
- * lo| hi| num| clk| cpo|wrdata|2T
- * mhz| mhz|ranks|adjst| | delay|
+ * memory controller 1
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
*/
- { 0, 333, 2, 4, 7, 3, 0},
- {334, 400, 2, 4, 9, 3, 0},
- {401, 549, 2, 4, 11, 3, 0},
- {550, 680, 2, 4, 11, 3, 0},
- {681, 850, 2, 4, 13, 3, 1},
- }
+ {2, 333, 4, 7, 3, 0},
+ {2, 400, 4, 9, 3, 0},
+ {2, 549, 4, 11, 3, 0},
+ {2, 680, 4, 11, 3, 0},
+ {2, 850, 4, 13, 3, 1},
+ {}
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm1,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- const board_specific_parameters_t *pbsp;
- u32 num_params;
- u32 i;
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
- if (!pdimm->n_ranks)
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
return;
-
- if (popts->registered_dimm_en) {
- pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]);
- num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) /
- sizeof(board_specific_parameters_rdimm[0][0]);
- } else {
- pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
- num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
- sizeof(board_specific_parameters_udimm[0][0]);
}
+ if (!pdimm->n_ranks)
+ return;
- /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i&1) { /* odd CS */
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 0;
- } else { /* even CS */
- if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 4;
- } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
- popts->cs_local_opts[i].odt_rd_cfg = 3;
- popts->cs_local_opts[i].odt_wr_cfg = 3;
- }
- }
- }
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
- for (i = 0; i < num_params; i++) {
- if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high &&
- pdimm->n_ranks == pbsp->n_ranks) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->twoT_en = pbsp->force_2T;
- break;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
}
pbsp++;
}
- if (i == num_params) {
- printf("Warning: board specific timing not found "
- "for data rate %lu MT/s!\n", ddr_freq);
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
}
+found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 4f2e853cd1..5d3575738a 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -11,127 +11,100 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-typedef struct {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
+struct board_specific_parameters {
u32 n_ranks;
+ u32 datarate_mhz_high;
u32 clk_adjust;
u32 cpo;
u32 write_data_delay;
-} board_specific_parameters_t;
-
-/* XXX: these values need to be checked for all interleaving modes. */
-const board_specific_parameters_t board_specific_parameters[2][16] = {
- {
- /* memory controller 0 */
- /* lo| hi| num| clk| cpo|wrdata */
- /* mhz| mhz|ranks|adjst| | delay */
- { 0, 333, 4, 7, 7, 3},
- {334, 400, 4, 7, 9, 3},
- {401, 549, 4, 7, 9, 3},
- {550, 650, 4, 7, 10, 4},
-
- { 0, 333, 3, 7, 7, 3},
- {334, 400, 3, 7, 9, 3},
- {401, 549, 3, 7, 9, 3},
- {550, 650, 3, 7, 10, 4},
-
- { 0, 333, 2, 7, 7, 3},
- {334, 400, 2, 7, 9, 3},
- {401, 549, 2, 7, 9, 3},
- {550, 650, 2, 7, 10, 4},
-
- { 0, 333, 1, 7, 7, 3},
- {334, 400, 1, 7, 9, 3},
- {401, 549, 1, 7, 9, 3},
- {550, 650, 1, 7, 10, 4}
- },
-
- {
- /* memory controller 1 */
- /* lo| hi| num| clk| cpo|wrdata */
- /* mhz| mhz|ranks|adjst| | delay */
- { 0, 333, 4, 7, 7, 3},
- {334, 400, 4, 7, 9, 3},
- {401, 549, 4, 7, 9, 3},
- {550, 650, 4, 7, 10, 4},
-
- { 0, 333, 3, 7, 7, 3},
- {334, 400, 3, 7, 9, 3},
- {401, 549, 3, 7, 9, 3},
- {550, 650, 3, 7, 10, 4},
+};
- { 0, 333, 2, 7, 7, 3},
- {334, 400, 2, 7, 9, 3},
- {401, 549, 2, 7, 9, 3},
- {550, 650, 2, 7, 10, 4},
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {4, 333, 7, 7, 3},
+ {4, 549, 7, 9, 3},
+ {4, 650, 7, 10, 4},
+ {2, 333, 7, 7, 3},
+ {2, 549, 7, 9, 3},
+ {2, 650, 7, 10, 4},
+ {1, 333, 7, 7, 3},
+ {1, 549, 7, 9, 3},
+ {1, 650, 7, 10, 4},
+ {}
+};
- { 0, 333, 1, 7, 7, 3},
- {334, 400, 1, 7, 9, 3},
- {401, 549, 1, 7, 9, 3},
- {550, 650, 1, 7, 10, 4}
- }
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+const struct board_specific_parameters *dimms[] = {
+ dimm0,
+ dimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- const board_specific_parameters_t *pbsp =
- &(board_specific_parameters[ctrl_num][0]);
- u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
- sizeof(board_specific_parameters[0][0]);
- u32 i;
- u32 j;
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ unsigned int i;
ulong ddr_freq;
- /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i&1) { /* odd CS */
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 0;
- } else { /* even CS */
- if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
- (pdimm[i/2].n_ranks != 0)) {
- popts->cs_local_opts[i].odt_rd_cfg = 3;
- popts->cs_local_opts[i].odt_wr_cfg = 3;
- } else {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 4;
- }
- }
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
}
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (pdimm[i].n_ranks)
+ break;
+ }
+ if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
+ return;
+
+ pbsp = dimms[ctrl_num];
/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
- for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
- if (pdimm[j].n_ranks > 0) {
- for (i = 0; i < num_params; i++) {
- if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high &&
- pdimm[j].n_ranks == pbsp->n_ranks) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- break;
- }
- pbsp++;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm[i].n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ goto found;
}
+ pbsp_highest = pbsp;
}
+ pbsp++;
}
- if (i == num_params) {
- printf("Warning: board specific timing not found "
- "for data rate %lu MT/s!\n", ddr_freq);
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ } else {
+ panic("DIMM is not supported by this board");
}
+found:
/* 2T timing enable */
popts->twoT_en = 1;
}
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
index 20b996e52a..455e5e725f 100644
--- a/board/freescale/p1022ds/ddr.c
+++ b/board/freescale/p1022ds/ddr.c
@@ -14,62 +14,89 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-typedef struct {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
+struct board_specific_parameters {
u32 n_ranks;
+ u32 datarate_mhz_high;
u32 clk_adjust; /* Range: 0-8 */
u32 cpo; /* Range: 2-31 */
u32 write_data_delay; /* Range: 0-6 */
u32 force_2T;
-} board_specific_parameters_t;
+};
-static const board_specific_parameters_t bsp[] = {
/*
- * lo| hi| num| clk| cpo|wrdata|2T
- * mhz| mhz|ranks|adjst| | delay|
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
*/
- { 0, 333, 1, 5, 31, 3, 0},
- {334, 400, 1, 5, 31, 3, 0},
- {401, 549, 1, 5, 31, 3, 0},
- {550, 680, 1, 5, 31, 5, 0},
- {681, 850, 1, 5, 31, 5, 0},
- { 0, 333, 2, 5, 31, 3, 0},
- {334, 400, 2, 5, 31, 3, 0},
- {401, 549, 2, 5, 31, 3, 0},
- {550, 680, 2, 5, 31, 5, 0},
- {681, 850, 2, 5, 31, 5, 0},
+static const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {1, 549, 5, 31, 3, 0},
+ {1, 850, 5, 31, 5, 0},
+ {2, 549, 5, 31, 3, 0},
+ {2, 850, 5, 31, 5, 0},
+ {}
};
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
unsigned long ddr_freq;
unsigned int i;
+
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
/* set odt_rd_cfg and odt_wr_cfg. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 1;
}
+ pbsp = dimm0;
/*
* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
- for (i = 0; i < ARRAY_SIZE(bsp); i++) {
- if (ddr_freq >= bsp[i].datarate_mhz_low &&
- ddr_freq <= bsp[i].datarate_mhz_high &&
- pdimm->n_ranks == bsp[i].n_ranks) {
- popts->clk_adjust = bsp[i].clk_adjust;
- popts->cpo_override = bsp[i].cpo;
- popts->write_data_delay = bsp[i].write_data_delay;
- popts->twoT_en = bsp[i].force_2T;
- break;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
}
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
}
+found:
popts->half_strength_driver_enable = 1;
/* Per AN4039, enable ZQ calibration. */
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index 926fd19271..c43f874c92 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -11,88 +11,95 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-typedef struct {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
+struct board_specific_parameters {
u32 n_ranks;
+ u32 datarate_mhz_high;
u32 clk_adjust;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
-} board_specific_parameters_t;
+};
-/* ranges for parameters:
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ *
+ * ranges for parameters:
* wr_data_delay = 0-6
* clk adjust = 0-8
* cpo 2-0x1E (30)
*/
-
-const board_specific_parameters_t board_specific_parameters[][20] = {
- {
- /* memory controller 0 */
- /* lo| hi| num| clk| cpo|wrdata|2T */
- /* mhz| mhz|ranks|adjst| | delay| */
+static const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
#ifdef CONFIG_FSL_DDR2
- { 0, 333, 2, 4, 0x1f, 2, 0},
- {334, 400, 2, 4, 0x1f, 2, 0},
- {401, 549, 2, 4, 0x1f, 2, 0},
- {550, 680, 2, 4, 0x1f, 3, 0},
- {681, 850, 2, 4, 0x1f, 4, 0},
- { 0, 333, 1, 4, 0x1f, 2, 0},
- {334, 400, 1, 4, 0x1f, 2, 0},
- {401, 549, 1, 4, 0x1f, 2, 0},
- {550, 680, 1, 4, 0x1f, 3, 0},
- {681, 850, 1, 4, 0x1f, 4, 0}
+ {2, 549, 4, 0x1f, 2, 0},
+ {2, 680, 4, 0x1f, 3, 0},
+ {2, 850, 4, 0x1f, 4, 0},
+ {1, 549, 4, 0x1f, 2, 0},
+ {1, 680, 4, 0x1f, 3, 0},
+ {1, 850, 4, 0x1f, 4, 0},
#else
- { 0, 850, 2, 6, 0x1f, 4, 0},
- { 0, 850, 1, 4, 0x1f, 4, 0}
+ {2, 850, 6, 0x1f, 4, 0},
+ {1, 850, 4, 0x1f, 4, 0},
#endif
- },
+ {}
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- const board_specific_parameters_t *pbsp =
- &(board_specific_parameters[ctrl_num][0]);
- u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
- sizeof(board_specific_parameters[0][0]);
- u32 i;
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
- /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
}
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = dimm0;
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
- for (i = 0; i < num_params; i++) {
- if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high &&
- pdimm->n_ranks == pbsp->n_ranks) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->twoT_en = pbsp->force_2T;
- break;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
}
pbsp++;
}
- if (i == num_params) {
- printf("Warning: board specific timing not found "
- "for data rate %lu MT/s!\n", ddr_freq);
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
}
+found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index 36370933b4..6d9a5de1c5 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -14,69 +14,91 @@
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
-typedef struct {
- u32 datarate_mhz_low;
- u32 datarate_mhz_high;
+struct board_specific_parameters {
u32 n_ranks;
+ u32 datarate_mhz_high;
u32 clk_adjust;
u32 wrlvl_start;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
-} board_specific_parameters_t;
+};
/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ *
* ranges for parameters:
* wr_data_delay = 0-6
* clk adjust = 0-8
* cpo 2-0x1E (30)
*/
-const board_specific_parameters_t board_specific_parameters[] = {
+static const struct board_specific_parameters dimm0[] = {
/*
* memory controller 0
- * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
- * mhz| mhz|ranks|adjst| start | delay|
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | delay|
*/
- { 0, 750, 2, 3, 5, 0xff, 2, 0},
- { 751, 1250, 2, 4, 6, 0xff, 2, 0},
- { 1251, 1350, 2, 5, 7, 0xff, 2, 0},
- { 1351, 1666, 2, 5, 8, 0xff, 2, 0},
+ {2, 750, 3, 5, 0xff, 2, 0},
+ {2, 1250, 4, 6, 0xff, 2, 0},
+ {2, 1350, 5, 7, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0xff, 2, 0},
+ {}
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
- const board_specific_parameters_t *pbsp =
- &board_specific_parameters[0];
- u32 num_params = ARRAY_SIZE(board_specific_parameters);
- u32 i;
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = dimm0;
+
/*
* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
- for (i = 0; i < num_params; i++) {
- if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high &&
- pdimm[0].n_ranks == pbsp->n_ranks) {
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->twoT_en = pbsp->force_2T;
- break;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
}
pbsp++;
}
- if (i == num_params) {
- printf("Warning: board specific timing not found "
- "for data rate %lu MT/s!\n", ddr_freq);
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
}
+found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
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