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| author | Stefan Roese <sr@denx.de> | 2007-08-14 14:44:41 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-14 14:44:41 +0200 |
| commit | 779e975117a75e91fcebe226a63104dbfb924ab1 (patch) | |
| tree | 42f48ba97342287f8e155cce29e8e0600064a16f /board/amcc | |
| parent | c5a172a5fd636c12467429e3f7910e53773979c6 (diff) | |
| download | blackbird-obmc-uboot-779e975117a75e91fcebe226a63104dbfb924ab1.tar.gz blackbird-obmc-uboot-779e975117a75e91fcebe226a63104dbfb924ab1.zip | |
ppc4xx: Add initial Zeus (PPC405EP) board support
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc')
| -rw-r--r-- | board/amcc/bubinga/bubinga.c | 13 | ||||
| -rw-r--r-- | board/amcc/taihu/taihu.c | 6 |
2 files changed, 18 insertions, 1 deletions
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index fe6ce8a6d1..66e7509da8 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -20,10 +20,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -long int spd_sdram(void); #include <common.h> #include <asm/processor.h> +#include <asm/io.h> + +long int spd_sdram(void); int board_early_init_f(void) { @@ -34,6 +36,15 @@ int board_early_init_f(void) mtdcr(uictr, 0x00000010); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + /* + * Configure CPC0_PCI to enable PerWE as output + * and enable the internal PCI arbiter if selected + */ + if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + else + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN); + return 0; } diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index ee9d3b5446..ea83671988 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -50,6 +50,12 @@ int board_early_init_f(void) mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ mtebc(pb3cr, CFG_EBC_PB3CR); + /* + * Configure CPC0_PCI to enable PerWE as output + * and enable the internal PCI arbiter + */ + mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + return 0; } |
