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authorLokesh Vutla <lokeshvutla@ti.com>2015-07-28 14:16:45 +0530
committerTom Rini <trini@konsulko.com>2015-08-12 20:47:53 -0400
commit74af583e9f7a255443d8f625c8dce6da7b9703be (patch)
treefbd63bb5fad0a796a8dcfcf4cfca0623fa235f17 /arch/arm/mach-keystone/clock-k2e.c
parent7b50e1599f4e6551a3348ca5f061a596f6f6896e (diff)
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ARM: keystone2: Use common structure for PLLs
Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/clock-k2e.c')
-rw-r--r--arch/arm/mach-keystone/clock-k2e.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 42092e1060..b23d2a561e 100644
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -11,12 +11,6 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
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