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* soc: qcom: Drop help text for QCOM_QMI_HELPERSNiklas Cassel2018-11-141-5/+0
| | | | | | | | | | | | | The help text is visible in menuconfig, however QCOM_QMI_HELPERS is a hidden kconfig, so it is not selectable in menuconfig. Remove the help text so that it is more clear that this is intentionally a hidden kconfig. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: Allow COMPILE_TEST of qcom SoC KconfigsNiklas Cassel2018-09-131-7/+8
| | | | | | | | | | | | | | | | | | Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"), we unconditionally include the soc/qcom/Makefile. This opens up the possibility to compile test the code even when building for other architectures. Allow COMPILE_TEST for all qcom SoC Kconfigs, except for two Kconfigs that depend on QCOM_SCM, since that triggers lots of build errors in qcom_scm. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: Remove depends on OF from QCOM_RPMHNiklas Cassel2018-09-131-1/+1
| | | | | | | | | | | | | | QCOM_RPHM already selects ARM64, which always selects OF. Additionally, the rpmh driver only uses linux/of.h, which has dummy definitions for all functions, in order for code to to be able to build without CONFIG_OF set. Remove the superfluous depends on OF. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: Remove bogus depends on OF from QCOM_SMD_RPMNiklas Cassel2018-09-131-1/+1
| | | | | | | | | | QCOM_SMD_RPM builds perfectly fine without CONFIG_OF set. Remove the bogus depends on OF. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: smsm: Add select IRQ_DOMAINNiklas Cassel2018-09-131-0/+1
| | | | | | | | | | | | | | | | Since we are using irq_domain_add_linear(), add a select on IRQ_DOMAIN. This is needed in order to be able to remove the depends on ARCH_QCOM. drivers/soc/qcom/smsm.c: In function ‘smsm_inbound_entry’: drivers/soc/qcom/smsm.c:411:18: error: implicit declaration of function ‘irq_domain_add_linear’ entry->domain = irq_domain_add_linear(node, 32, &smsm_irq_ops, entry); ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: smp2p: Add select IRQ_DOMAINNiklas Cassel2018-09-131-0/+1
| | | | | | | | | | | | | | | | Since we are using irq_domain_add_linear(), add a select on IRQ_DOMAIN. This is needed in order to be able to remove the depends on ARCH_QCOM. drivers/soc/qcom/smp2p.c: In function ‘qcom_smp2p_inbound_entry’: drivers/soc/qcom/smp2p.c:317:18: error: implicit declaration of function ‘irq_domain_add_linear’ entry->domain = irq_domain_add_linear(node, 32, &smp2p_irq_ops, entry); ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* Merge branch 'regulator-4.19' into regulator-nextMark Brown2018-08-101-0/+27
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| * drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCsLina Iyer2018-07-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add controller driver for QCOM SoCs that have hardware based shared resource management. The hardware IP known as RSC (Resource State Coordinator) houses multiple Direct Resource Voter (DRV) for different execution levels. A DRV is a unique voter on the state of a shared resource. A Trigger Control Set (TCS) is a bunch of slots that can house multiple resource state requests, that when triggered will issue those requests through an internal bus to the Resource Power Manager Hardened (RPMH) blocks. These hardware blocks are capable of adjusting clocks, voltages, etc. The resource state request from a DRV are aggregated along with state requests from other processors in the SoC and the aggregate value is applied on the resource. Some important aspects of the RPMH communication - - Requests are <addr, value> with some header information - Multiple requests (upto 16) may be sent through a TCS, at a time - Requests in a TCS are sent in sequence - Requests may be fire-n-forget or completion (response expected) - Multiple TCS from the same DRV may be triggered simultaneously - Cannot send a request if another request for the same addr is in progress from the same DRV - When all the requests from a TCS are complete, an IRQ is raised - The IRQ handler needs to clear the TCS before it is available for reuse - TCS configuration is specific to a DRV - Platform drivers may use DRV from different RSCs to make requests Resource state requests made when CPUs are active are called 'active' state requests. Requests made when all the CPUs are powered down (idle state) are called 'sleep' state requests. They are matched by a corresponding 'wake' state requests which puts the resources back in to previously requested active state before resuming any CPU. TCSes are dedicated for each type of requests. Active mode TCSes (AMC) are used to send requests immediately to the resource, while control TCS are used to provide specific information to the controller. Sleep and Wake TCS send sleep and wake requests, after and before the system halt respectively. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
| * drivers: soc: Add LLCC driverRishabh Bhatnagar2018-07-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* | qcom: cmd-db: enforce CONFIG_OF_RESERVED_MEM dependencyArnd Bergmann2018-06-251-1/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without CONFIG_OF_RESERVED_MEM, gcc sees that the global cmd_db_header variable is never initialized, and through code optimization concludes that a lot of other code cannot possibly work after that: drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_addr': drivers/soc/qcom/cmd-db.c:197:21: error: 'ent.addr' may be used uninitialized in this function [-Werror=maybe-uninitialized] return ret < 0 ? 0 : le32_to_cpu(ent.addr); drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_aux_data': drivers/soc/qcom/cmd-db.c:224:10: error: 'ent.len' may be used uninitialized in this function [-Werror=maybe-uninitialized] ent_len = le16_to_cpu(ent.len); drivers/soc/qcom/cmd-db.c:115:6: error: 'rsc_hdr.data_offset' may be used uninitialized in this function [-Werror=maybe-uninitialized] u16 offset = le16_to_cpu(hdr->data_offset); ^~~~~~ drivers/soc/qcom/cmd-db.c:116:6: error: 'ent.offset' may be used uninitialized in this function [-Werror=maybe-uninitialized] u16 loffset = le16_to_cpu(ent->offset); ^~~~~~~ drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_aux_data_len': drivers/soc/qcom/cmd-db.c:250:38: error: 'ent.len' may be used uninitialized in this function [-Werror=maybe-uninitialized] return ret < 0 ? 0 : le16_to_cpu(ent.len); ^ drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_slave_id': drivers/soc/qcom/cmd-db.c:272:7: error: 'ent.addr' may be used uninitialized in this function [-Werror=maybe-uninitialized] Using a hard CONFIG_OF_RESERVED_MEM dependency avoids this warning, and we can remove the CONFIG_OF dependency. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* Merge tag 'armsoc-late' of ↵Linus Torvalds2018-06-111-0/+18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late updates from Olof Johansson: "This is a branch with a few merge requests that either came in late, or took a while longer for us to review and merge than usual and thus cut it a bit close to the merge window. We stage them in a separate branch and if things look good, we still send them up -- and that's the case here. This is mostly DT additions for Renesas platforms, adding IP block descriptions for existing and new SoCs. There are also some driver updates for Qualcomm platforms for SMEM/QMI and GENI, which is their generalized serial protocol interface" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits) soc: qcom: smem: introduce qcom_smem_virt_to_phys() soc: qcom: qmi: fix a buffer sizing bug MAINTAINERS: Update pattern for qcom_scm soc: Unconditionally include qcom Makefile soc: qcom: smem: check sooner in qcom_smem_set_global_partition() soc: qcom: smem: fix qcom_smem_set_global_partition() soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private() soc: qcom: smem: byte swap values properly soc: qcom: smem: return proper type for cached entry functions soc: qcom: smem: fix first cache entry calculation soc: qcom: cmd-db: Make endian-agnostic drivers: qcom: add command DB driver arm64: dts: renesas: salvator-common: Add ADV7482 support ARM: dts: r8a7740: Add CEU1 ARM: dts: r8a7740: Add CEU0 arm64: dts: renesas: salvator-common: enable VIN arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7795-es1: add CSI-2 node ...
| * drivers: qcom: add command DB driverMahesh Sivasubramanian2018-05-251-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Command DB is a simple database in the shared memory of QCOM SoCs, that provides information regarding shared resources. Some shared resources in the SoC have properties that are probed dynamically at boot by the remote processor. The information pertaining to the SoC and the platform are made available in the shared memory. Drivers can query this information using predefined strings. Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
| * soc: qcom: Add GENI based QUP Wrapper driverKarthikeyan Ramasubramanian2018-04-251-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver manages the Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation programmable module composed of multiple Serial Engines (SE) and supports a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This driver also enables managing the serial interface independent aspects of Serial Engines. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Signed-off-by: Sagar Dharia <sdharia@codeaurora.org> Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* | soc: qcom: Add APR bus driverSrinivas Kandagatla2018-05-111-0/+9
|/ | | | | | | | | | | | | | This patch adds support to APR bus (Asynchronous Packet Router) driver. APR driver is made as a bus driver so that the apr devices can added removed more dynamically depending on the state of the services on the dsp. APR is used for communication between application processor and QDSP to use services on QDSP like Audio and others. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-and-tested-by: Rohit kumar <rohitkr@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'rproc-v4.17' of git://github.com/andersson/remoteprocLinus Torvalds2018-04-101-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull remoteproc updates from Bjorn Andersson: - add support for generating coredumps for remoteprocs using devcoredump - add the Qualcomm sysmon driver for intra-remoteproc crash handling - a number of fixes in Qualcomm and IMX drivers * tag 'rproc-v4.17' of git://github.com/andersson/remoteproc: remoteproc: fix null pointer dereference on glink only platforms soc: qcom: qmi: add CONFIG_NET dependency remoteproc: imx_rproc: Slightly simplify code in 'imx_rproc_probe()' remoteproc: imx_rproc: Re-use existing error handling path in 'imx_rproc_probe()' remoteproc: imx_rproc: Fix an error handling path in 'imx_rproc_probe()' samples: Introduce Qualcomm QMI sample client remoteproc: qcom: Introduce sysmon remoteproc: Pass type of shutdown to subdev remove remoteproc: qcom: Register segments for core dump soc: qcom: mdt-loader: Return relocation base remoteproc: Rename "load_rsc_table" to "parse_fw" remoteproc: Add remote processor coredump support remoteproc: Remove null character write of shared mem
| * soc: qcom: qmi: add CONFIG_NET dependencyArnd Bergmann2018-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Access to the socket API and the root network namespace is only available when networking is enabled: ERROR: "kernel_sendmsg" [drivers/soc/qcom/qmi_helpers.ko] undefined! ERROR: "sock_release" [drivers/soc/qcom/qmi_helpers.ko] undefined! ERROR: "sock_create_kern" [drivers/soc/qcom/qmi_helpers.ko] undefined! ERROR: "kernel_getsockname" [drivers/soc/qcom/qmi_helpers.ko] undefined! ERROR: "init_net" [drivers/soc/qcom/qmi_helpers.ko] undefined! ERROR: "kernel_recvmsg" [drivers/soc/qcom/qmi_helpers.ko] undefined! Adding a dependency on CONFIG_NET lets us build it in all randconfig builds. Fixes: 9b8a11e82615 ("soc: qcom: Introduce QMI encoder/decoder") Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* | soc: qcom: rmtfs-mem: Add support for assigning memory to remoteBjorn Andersson2018-03-081-0/+1
|/ | | | | | | | | | | | | On some platform the remote processor's memory map is not statically configured in TrustZone, so each memory region that is to be accessed by the remote needs a call into TrustZone to set up the remote's permissions. Implement this for the rmtfs memory driver, to give the modem on 8996 access to the shared file system buffers. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: Introduce QMI encoder/decoderBjorn Andersson2017-12-201-0/+9
| | | | | | | | | | | | | | | Add the helper library for encoding and decoding QMI encoded messages. The implementation is taken from lib/qmi_encdec.c of the Qualcomm kernel (msm-3.18). Modifications has been made to the public API, source buffers has been made const and the debug-logging part was omitted, for now. Acked-by: Chris Lew <clew@codeaurora.org> Tested-by: Chris Lew <clew@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: smp2p: Access APCS as mailbox clientBjorn Andersson2017-12-201-0/+1
| | | | | | | | | Attempt to acquire the APCS IPC through the mailbox framework and fall back to the old syscon based approach, to allow us to move away from using the syscon. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: Remote filesystem memory driverBjorn Andersson2017-10-221-0/+11
| | | | | | | | | | | | | | | The Qualcomm remote file system protocol is used by certain remoteprocs, in particular the modem, to read and write persistent storage in platforms where only the application CPU has physical storage access. The protocol is based on a set of QMI-encoded control-messages and a shared memory buffer for exchaning the data. This driver implements the latter, providing the user space service access to the carved out chunk of memory. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2017-09-101-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "This branch contains platform-related driver updates for ARM and ARM64. Among them: - Reset driver updates: + New API for dealing with arrays of resets + Make unimplemented {de,}assert return success on shared resets + MSDKv1 driver + Removal of obsolete Gemini reset driver + Misc updates for sunxi and Uniphier - SoC drivers: + Platform SoC driver registration on Tegra + Shuffle of Qualcomm drivers into a submenu + Allwinner A64 support for SRAM + Renesas R-Car R3 support + Power domains for Rockchip RK3366 - Misc updates and smaller fixes for TEE and memory driver subsystems" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) firmware: arm_scpi: fix endianness of dev_id in struct dev_pstate_set soc/tegra: fuse: Add missing semi-colon soc/tegra: Restrict SoC device registration to Tegra drivers: soc: sunxi: add support for A64 and its SRAM C drivers: soc: sunxi: add support for remapping func value to reg value drivers: soc: sunxi: fix error processing on base address when claiming dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C bus: sunxi-rsb: Enable by default for ARM64 soc/tegra: Register SoC device firmware: tegra: set drvdata earlier memory: Convert to using %pOF instead of full_name soc: Convert to using %pOF instead of full_name bus: Convert to using %pOF instead of full_name firmware: Convert to using %pOF instead of full_name soc: mediatek: add SCPSYS power domain driver for MediaTek MT7622 SoC soc: mediatek: add header files required for MT7622 SCPSYS dt-binding soc: mediatek: reduce code duplication of scpsys_probe across all SoCs dt-bindings: soc: update the binding document for SCPSYS on MediaTek MT7622 SoC reset: uniphier: add analog amplifiers reset control reset: uniphier: add video input subsystem reset control ...
| * soc: qcom: bring all qcom drivers into a submenuSrinivas Kandagatla2017-08-081-0/+4
| | | | | | | | | | | | | | | | | | As the number of qcom drivers increase, entries in SOC menu looks scattered with other SOC drivers. Make a submenu for Qcom drivers to make it visibly clear while selecting qcom SOC specific drivers. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* | soc: qcom: GLINK SSR notifierBjorn Andersson2017-08-021-0/+9
|/ | | | | | | | | | | | | This driver register as a subsystem restart notifier and will send out notifications to remote processors that has opened the "glink_ssr" GLINK channel. This mechanism is used to signal any GLINK participants that a 3rd party is gone and that the communication state has to be reset; i.e. that read and write pointers of the GLINK FIFOs are stale. Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* soc: qcom: smd: Remove standalone driverBjorn Andersson2017-03-281-8/+0
| | | | | | | | | | | | Remove the standalone SMD implementation as we have transitioned the client drivers to use the RPMSG based one. Also remove all dependencies on QCOM_SMD from Kconfig files, in order to keep them selectable in the absence of the removed symbol. Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* soc: qcom: smd: Transition client drivers from smd to rpmsgBjorn Andersson2017-03-281-2/+4
| | | | | | | | | | | | | | | | By moving these client drivers to use RPMSG instead of the direct SMD API we can reuse them ontop of the newly added GLINK wire-protocol support found in the 820 and 835 Qualcomm platforms. As the new (RPMSG-based) and old SMD implementations are mutually exclusive we have to change all client drivers in one commit, to make sure we have a working system before and after this transition. Acked-by: Andy Gross <andy.gross@linaro.org> Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Marcel Holtmann <marcel@holtmann.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* remoteproc: Move qcom_mdt_loader into drivers/soc/qcomBjorn Andersson2017-02-061-0/+4
| | | | | | | | With the remoteproc parts cleaned out of the MDT loader we can move it to drivers/soc/qcom. Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* soc: qcom: Introduce WCNSS_CTRL SMD clientBjorn Andersson2015-12-081-0/+7
| | | | | | | | The WCNSS_CTRL SMD client is used for among other things upload nv firmware to a newly booted WCNSS chip. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* ARM: qcom: select ARM_CPU_SUSPEND for power managementArnd Bergmann2015-12-081-0/+1
| | | | | | | | | | | | | | | | | The qcom spm driver uses cpu_resume_arm(), which is not included in the kernel in all configurations: drivers/built-in.o: In function `qcom_cpu_spc': :(.text+0xbc022): undefined reference to `cpu_suspend' drivers/built-in.o: In function `qcom_cpuidle_init': :(.init.text+0x610c): undefined reference to `cpu_resume_arm' This adds a 'select' Kconfig statement to ensure it's always enabled. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom: enable smsm/smp2p modular buildArnd Bergmann2015-12-081-2/+2
| | | | | | | | | | | | | | | | | | | | | The newly added smp2p and smsm drivers cannot be loadable modules but depend on smem, which can be, and that causes a link error: drivers/built-in.o: In function `qcom_smp2p_intr': :(.text+0xa6e68): undefined reference to `qcom_smem_get' drivers/built-in.o: In function `qcom_smp2p_probe': :(.text+0xa7320): undefined reference to `qcom_smem_alloc' :(.text+0xa736c): undefined reference to `qcom_smem_get' drivers/built-in.o: In function `qcom_smsm_probe': :(.text+0xa7b34): undefined reference to `qcom_smem_get' This marks all the drivers as 'tristate' to make the Kconfig dependency resolution work properly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: dbb04bd7122f ("soc: qcom: smp2p: Qualcomm Shared Memory Point to Point") Fixes: d7387fc6add4 ("soc: qcom: smsm: Add driver for Qualcomm SMSM") Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom: smp2p: Qualcomm Shared Memory Point to PointBjorn Andersson2015-12-081-0/+8
| | | | | | | Introduce the Qualcomm Shard Memory Point to Point driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom: smsm: Add driver for Qualcomm SMSMBjorn Andersson2015-12-081-0/+8
| | | | | | | This driver exposed the Qualcomm Shared Memory State Machine bits. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom: Introduce common SMEM state machine codeBjorn Andersson2015-12-081-0/+3
| | | | | | | | This implements a common API for handling and exposing SMP2P and SMSM state information. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom/smem: add HWSPINLOCK dependencyArnd Bergmann2015-10-151-0/+1
| | | | | | | | | | | | | | | | | | This fixes a build error when smem is enabled without hwspinlock: drivers/built-in.o: In function `qcom_smem_alloc': rockchip-efuse.c:(.text+0x7a3e4): undefined reference to `__hwspin_lock_timeout' rockchip-efuse.c:(.text+0x7a568): undefined reference to `__hwspin_unlock' drivers/built-in.o: In function `qcom_smem_remove': rockchip-efuse.c:(.text+0x7a5cc): undefined reference to `hwspin_lock_free' drivers/built-in.o: In function `qcom_smem_probe': rockchip-efuse.c:(.text+0x7a960): undefined reference to `hwspin_lock_request_specific' rockchip-efuse.c:(.text+0x7a988): undefined reference to `of_hwspin_lock_get_id' drivers/built-in.o: In function `qcom_smem_get': rockchip-efuse.c:(.text+0x7aa24): undefined reference to `__hwspin_lock_timeout' rockchip-efuse.c:(.text+0x7aafc): undefined reference to `__hwspin_unlock' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* soc: qcom: Reorder SMEM/SMD configsStephen Boyd2015-10-141-8/+8
| | | | | | | | | | | | When I make nconfig, having the SMEM option after the SMD option causes the configurator to get confused when I'm enabling and disabling these options. Let's move SMEM before SMD so there's a clear indented dependency chain. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom: Driver for the Qualcomm RPM over SMDBjorn Andersson2015-07-291-0/+14
| | | | | | | | | | Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based devices. The driver exposes resources that child drivers can operate on; to implementing regulator, clock and bus frequency drivers. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom: Add Shared Memory DriverBjorn Andersson2015-07-291-0/+8
| | | | | | | | This adds the Qualcomm Shared Memory Driver (SMD) providing communication channels to remote processors, ontop of SMEM. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
* drivers: qcom: Select QCOM_SCM unconditionally for QCOM_PMLina Iyer2015-07-281-0/+1
| | | | | | | | | Enable QCOM_SCM for QCOM power management driver Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
* soc: qcom: Add Shared Memory Manager driverBjorn Andersson2015-07-281-0/+8
| | | | | | | | | | The Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors in a Qualcomm platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
* ARM: qcom: Add Subsystem Power Manager (SPM) driverLina Iyer2015-04-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPM is a hardware block that controls the peripheral logic surrounding the application cores (cpu/l$). When the core executes WFI instruction, the SPM takes over the putting the core in low power state as configured. The wake up for the SPM is an interrupt at the GIC, which then completes the rest of low power mode sequence and brings the core out of low power mode. The SPM has a set of control registers that configure the SPMs individually based on the type of the core and the runtime conditions. SPM is a finite state machine block to which a sequence is provided and it interprets the bytes and executes them in sequence. Each low power mode that the core can enter into is provided to the SPM as a sequence. Configure the SPM to set the core (cpu or L2) into its low power mode, the index of the first command in the sequence is set in the SPM_CTL register. When the core executes ARM wfi instruction, it triggers the SPM state machine to start executing from that index. The SPM state machine waits until the interrupt occurs and starts executing the rest of the sequence until it hits the end of the sequence. The end of the sequence jumps the core out of its low power mode. Add support for an idle driver to set up the SPM to place the core in Standby or Standalone power collapse mode when the core is idle. Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>, Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org> Original tree available at - git://codeaurora.org/quic/la/kernel/msm-3.10.git Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Kevin Hilman <khilman@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Kumar Gala <galak@codeaurora.org> Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
* soc: qcom: gsbi: Add support for ADM CRCI muxingAndy Gross2015-03-111-0/+1
| | | | | | | | | | This patch adds automatic configuration for the ADM CRCI muxing required to support DMA operations for GSBI clients. The GSBI mode and instance determine the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA works properly. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
* soc: qcom: Add GSBI driverAndy Gross2014-05-231-0/+11
The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
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