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* drm/i915: Block fbdev HPD processing during suspendLyude Paul2019-02-121-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When resuming, we check whether or not any previously connected MST topologies are still present and if so, attempt to resume them. If this fails, we disable said MST topologies and fire off a hotplug event so that userspace knows to reprobe. However, sending a hotplug event involves calling drm_fb_helper_hotplug_event(), which in turn results in fbcon doing a connector reprobe in the caller's thread - something we can't do at the point in which i915 calls drm_dp_mst_topology_mgr_resume() since hotplugging hasn't been fully initialized yet. This currently causes some rather subtle but fatal issues. For example, on my T480s the laptop dock connected to it usually disappears during a suspend cycle, and comes back up a short while after the system has been resumed. This guarantees pretty much every suspend and resume cycle, drm_dp_mst_topology_mgr_set_mst(mgr, false); will be caused and in turn, a connector hotplug will occur. Now it's Rute Goldberg time: when the connector hotplug occurs, i915 reprobes /all/ of the connectors, including eDP. However, eDP probing requires that we power on the panel VDD which in turn, grabs a wakeref to the appropriate power domain on the GPU (on my T480s, this is the PORT_DDI_A_IO domain). This is where things start breaking, since this all happens before intel_power_domains_enable() is called we end up leaking the wakeref that was acquired and never releasing it later. Come next suspend/resume cycle, this causes us to fail to shut down the GPU properly, which causes it not to resume properly and die a horrible complicated death. (as a note: this only happens when there's both an eDP panel and MST topology connected which is removed mid-suspend. One or the other seems to always be OK). We could try to fix the VDD wakeref leak, but this doesn't seem like it's worth it at all since we aren't able to handle hotplug detection while resuming anyway. So, let's go with a more robust solution inspired by nouveau: block fbdev from handling hotplug events until we resume fbdev. This allows us to still send sysfs hotplug events to be handled later by user space while we're resuming, while also preventing us from actually processing any hotplug events we receive until it's safe. This fixes the wakeref leak observed on the T480s and as such, also fixes suspend/resume with MST topologies connected on this machine. Changes since v2: * Don't call drm_fb_helper_hotplug_event() under lock, do it after lock (Chris Wilson) * Don't call drm_fb_helper_hotplug_event() in intel_fbdev_output_poll_changed() under lock (Chris Wilson) * Always set ifbdev->hpd_waiting (Chris Wilson) Signed-off-by: Lyude Paul <lyude@redhat.com> Fixes: 0e32b39ceed6 ("drm/i915: add DP 1.2 MST support (v0.7)") Cc: Todd Previte <tprevite@gmail.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190129191001.442-2-lyude@redhat.com (cherry picked from commit fe5ec65668cdaa4348631d8ce1766eed43b33c10) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915/icl: Add get config functionality for DSIVandita Kulkarni2018-12-031-0/+2
| | | | | | | | | | | | | | | | | | This patch implements the functionality for getting PIPE configuration to which DSI encoder is connected. Use the same method to get port clock like other DDI encoders. Used during the atomic modeset. v2 by Jani: - Squash Madhav's and Vandita's get config bits together - Move cnl_calc_wrpll_link() to intel_drv.h - Drop extra temp variables - Use enc_to_intel_dsi() instead of open coding Co-developed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f21fa4258068d04582f2bf30735e5536a8043bdf.1543500286.git.jani.nikula@intel.com
* drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooksJani Nikula2018-12-031-6/+0
| | | | | | | | | | | | | | | | | | | Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions a bit by moving the pll to port mapping and unmapping functions to the ddi encoder hooks. This allows removal of a bunch of boilerplate code from the functions. Additionally, the ICL DSI encoder needs to do the clock gating and ungating slightly differently, and this allows its own handling in a clean fashion. Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f8e2982ceea4c05dc254a0c15e2b3be1d5f271d3.1543500285.git.jani.nikula@intel.com
* i915/dp/fec: Add fec_enable to the crtc state.Anusha Srivatsa2018-11-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For DP 1.4 and above, Display Stream compression can be enabled only if Forward Error Correctin can be performed. Add a crtc state for FEC. Currently, the state is determined by platform, DP and DSC being enabled. Moving forward we can use the state to have error correction on other scenarios too if needed. v2: - Control compression_enable with the fec_enable parameter in crtc state and with intel_dp_supports_fec() (Ville) - intel_dp_can_fec()/intel_dp_supports_fec()(manasi) v3: Check for FEC support along with setting crtc state. v4: add checks to intel_dp_source_supports_dsc.(manasi) - Move intel_dp_supports_fec() closer to intel_dp_supports_dsc() (Anusha) v5: Move fec check to intel_dp_supports_dsc(Ville) v6: Remove warning. rebase. v7: change crtc state to include DP sink and fec capability of source.(Manasi) v8: Set fec_enable in crtc in intel_dp_compute_config(). v9 (From Manasi): * Combine the !edp and !fec_support check * Derive dev_priv from intel_dp directly v10 (From Manasi): * Rebase Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: dri-devel@lists.freedesktop.org Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.comk> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-14-manasi.d.navare@intel.com
* drm/i915/dsc: Enable and disable appropriate power wells for VDSCManasi Navare2018-11-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | A separate power well 2 (PG2) is required for VDSC on eDP transcoder whereas all other transcoders use the power wells associated with the transcoders for VDSC. This patch adds a helper to obtain correct power domain depending on transcoder being used and enables/disables the power wells during VDSC enabling/disabling. v4: * Get VDSC power domain only if compression en is set in crtc_state (Ville, Imre) v3: * Call it intel_dsc_power_domain, add to intel_ddi_get_power_domains (Ville) v2: * Fix tabs, const crtc_state, fix comments (Ville) Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-13-manasi.d.navare@intel.com
* drm/i915/dp: Enable/Disable DSC in DP SinkGaurav K Singh2018-11-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | This patch enables decompression support in sink device before link training and disables the same during the DDI disabling. v3 (From manasi): * Pass bool state to enable/disable (Ville) v2:(From Manasi) * Change the enable/disable function to take crtc_state instead of intel_dp as an argument (Manasi) * Use the compression_enable flag as part of crtc_state (Manasi) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-6-manasi.d.navare@intel.com
* drm/i915/dsc: Define & Compute VESA DSC paramsGaurav K Singh2018-11-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches does the following: 1. This patch defines all the DSC parameters as per the VESA DSC specification. These are stored in the encoder and used to compute the PPS parameters to be sent to the Sink. 2. Compute all the DSC parameters which are derived from DSC state of intel_crtc_state. 3. Compute all parameters that are VESA DSC specific This computation happens in the atomic check phase during compute_config() to validate if display stream compression can be enabled for the requested mode. v8 (From Manasi): * DEBUG_KMS instead of DRM_ERROR for user triggerable errors (Ville) v7: (From Manasi) * Dont use signed int for rc_range_params (Manasi) * Mask the range_bpg_offset to use only 6 bits * Add SPDX identifier (Chris Wilson) v6 (From Manasi): * Add a check for line_buf_depth return value (Anusha) * Remove DRM DSC constants to different patch (Manasi) v5 (From Manasi): * Add logic to limit the max line buf depth for DSC 1.1 to 13 as per DSC 1.1 spec * Fix dim checkpatch warnings/checks v4 (From Gaurav): * Rebase on latest drm tip * rename variable name(Manasi) * Populate linebuf_depth variable(Manasi) v3 (From Gaurav): * Rebase my previous patches on top of Manasi's latest patch series * Using >>n rather than /2^n (Manasi) * Change the commit message to explain what the patch is doing(Gaurav) Fixed review comments from Ville: * Don't use macro TWOS_COMPLEMENT * Mention in comment about the source of RC params * Return directly from case statements * Using single asssignment for assigning rc_range_params * Using <<n rather than *2^n and removing the comments about the fixed point numbers v2 (From Manasi): * Update logic for minor version to consider the dpcd value and what supported by the HW platform * Use DRM DSC config struct instead of intel_dp struct * Move the DSC constants to DRM DSC header file * Use u16, u8 where bigger data types not needed * * Compute the DSC parameters as part of DSC compute config since the computation can fail (Manasi) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Co-developed-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181129193827.7914-1-manasi.d.navare@intel.com
* drm/i915/dp: Add DSC params and DSC config to intel_crtc_stateManasi Navare2018-11-291-0/+9
| | | | | | | | | | | | | | | | | | | | | | Basic DSC parameters and DSC configuration data needs to be computed for each of the requested mode during atomic check. This is required since for certain modes, valid DSC parameters and config data might not be computed in which case compression cannot be enabled for that mode. For that reason we need to add these params and config structure to the intel_crtc_state so that if valid this state information can directly be used while enabling DSC in atomic commit. v2: * Rebase on drm-tip (Manasi) Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-1-manasi.d.navare@intel.com
* drm/i915: Commit skl+ planes in an order that avoids ddb overlapsVille Syrjälä2018-11-281-4/+4
| | | | | | | | | | | | | | | | | | | | skl+ can go belly up if there are overlapping ddb allocations between planes. If we could absolutely guarantee that we can perform the atomic update within a single frame we shouldn't have to worry about this. But we can't rely on that so let's steal the ddb overlap check trick from skl_update_crtcs() and apply it to the plane updates. Since each step of the sequence is free from ddb overlaps we don't have to worry about a vblank sneaking up on us in the middle of the sequence. The partial state that gets latched by the hardware will be safe. And unlike skl_update_crtcs() we don't have to intoduce any extra vblank waits on account of only having to worry about a single pipe. v2: Fix typo in commit msg (Matt) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-12-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
* drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+Ville Syrjälä2018-11-281-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | On SKL+ the plane WM/BUF_CFG registers are a proper part of each plane's register set. That means accessing them will cancel any pending plane update, and we would need a PLANE_SURF register write to arm the wm/ddb change as well. To avoid all the problems with that let's just move the wm/ddb programming into the plane update/disable hooks. Now all plane registers get written in one (hopefully atomic) operation. To make that feasible we'll move the plane ddb tracking into the crtc state. Watermarks were already tracked there. v2: Rebase due to input CSC v3: Split out a bunch of junk (Matt) v4: Add skl_wm_add_affected_planes() to deal with cursor special case and non-zero wm register reset value v5: Drop the unrelated for_each_intel_plane_mask() fix (Matt) Remove the redundant ddb memset() (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v3 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181127165900.31298-1-ville.syrjala@linux.intel.com
* drm/i915: Pass the new crtc_state to ->disable_plane()Ville Syrjälä2018-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | We're going to need access to the new crtc state in ->disable_plane() for SKL+ wm/ddb programming and pre-skl pipe gamma/csc control. Pass the crtc state down. We'll also try to make intel_crtc_disable_planes() do the right thing as much as it's possible. The fact that we don't have a separate crtc state for the disabled state when we're going to re-enable the crtc later means we might end up poking at a few extra planes in there. But that's harmless. I suppose one might argue that we wouldn't have to care about proper ddb/wm/csc/gamma if the pipe is going to permanently disable anyway, but the state checker probably cares so we should try our best to make sure everything is programmed correctly even in that case. v2: Fix the commit message a bit (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-5-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
* drm/i915: Introduce crtc_state->update_planes bitmaskVille Syrjälä2018-11-281-0/+3
| | | | | | | | | | | | | | | | Keep track which planes need updating during the commit. For now we set the bit for any plane that was or will be visible (including icl+ nv12 slave planes). In the future I'll have need to update invisible planes as well, for skl plane ddbs and for pre-skl pipe gamma/csc control (which lives in the primary plane control register). v2: Pimp the commit message to mention icl+ nv12 slave planes (Matt) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181127163742.30215-1-ville.syrjala@linux.intel.com
* drm/i915: Check PSR errors instead of retrain while PSR is enabledJosé Roberto de Souza2018-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | When a PSR error happens sink sets the PSR error register and also set the link status to a error status. So in the short pulse handling it was returning earlier and doing a full detection and attempting to retrain but it fails as PSR HW is in change of the main-link. Just call intel_psr_short_pulse() before intel_dp_needs_link_retrain() is not the right fix as intel_dp_needs_link_retrain() would return true and trigger a full detection while PSR HW is still in change of main-link. Check for PSR active is also not safe as it could be inactive due a frontbuffer invalidate and still doing the PSR exit sequence. v3: added comment in intel_dp_needs_link_retrain() Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-2-jose.souza@intel.com
* drm/i915: Add rotation readout for plane initial configVille Syrjälä2018-11-211-0/+1
| | | | | | | | | | | | | | | | | If we need to force a full plane update before userspace/fbdev have given us a proper plane state we should try to maintain the current plane state as much as possible (apart from the parts of the state we're trying to fix up with the plane update). To that end add basic readout for the plane rotation and maintain it during the initial fb takeover. Cc: Hans de Goede <hdegoede@redhat.com> Fixes: 516a49cc1946 ("drm/i915: Fix assert_plane() warning on bootup with external display") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120135450.3634-2-ville.syrjala@linux.intel.com Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
* drm/i915: Fix plane allocation/free functionsMaarten Lankhorst2018-11-151-3/+2
| | | | | | | | | | | | | | | | | Use intel_plane_destroy_state in intel_plane_free to free the state. Also fix intel_plane_alloc() to use __drm_atomic_helper_plane_reset(), to get sane defaults from the atomic core. This is needed to get the correct alpha value and blend mode from the core, and any new default values added from new properties. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: b20815255693 ("drm/i915: Add plane alpha blending support, v2.") [mlankhorst: Update commit description to mention alpha blend support] Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181113092804.13304-1-maarten.lankhorst@linux.intel.com
* drm/i915: Account for scale factor when calculating initial phaseVille Syrjälä2018-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | To get the initial phase correct we need to account for the scale factor as well. I forgot this initially and was mostly looking at heavily upscaled content where the minor difference between -0.5 and the proper initial phase was not readily apparent. And let's toss in a comment that tries to explain the formula a little bit. v2: The initial phase upper limit is 1.5, not 24.0! Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 0a59952b24e2 ("drm/i915: Configure SKL+ scaler initial phase correctly") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181029181820.21956-1-ville.syrjala@linux.intel.com Tested-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Tested-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
* drm/i915: Generalize skl_ddb_allocation_overlaps()Ville Syrjälä2018-11-091-4/+3
| | | | | | | | | | | | | | | Make skl_ddb_allocation_overlaps() useful for other callers besides skl_update_crtcs(). We'll need it to do plane updates as well. And while we're here we can reduce the stack utilization a bit by noting that each struct skl_ddb_entry is 4 bytes whereas a pointer to one is 8 bytes (on 64bit). So we'll switch to an array of structs from the array of pointers we used before. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181101150605.18235-9-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
* drm/i915: Keep overlay functions naming consistentJosé Roberto de Souza2018-11-081-2/+2
| | | | | | | | | | | | All other overlay functions(almost all other functions in i915) follow intel_overlay_verb, so renaming overlay ones that do not match that. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181108001647.11276-4-jose.souza@intel.com
* drm/i915/icl: Configure MG DP mode for HDMI ports tooImre Deak2018-11-051-1/+0
| | | | | | | | | | | | | | | The MG DP mode needs to be configured for Type C static/fixed/legacy HDMI ports too, the same way as it's configured for Type C static/fixed/legacy, fix this. Bspec: 4232, 21735 Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Tested-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102192656.4472-3-imre.deak@intel.com
* drm/i915/icl: Configure MG PHY gating for HDMI ports tooImre Deak2018-11-051-2/+0
| | | | | | | | | | | | | | | | The MG PHY clock gating needs to be configured for Type C static/fixed/legacy HDMI ports the same way it's configured for Type C static/fixed/legacy and aternate mode DP ports, fix this. Bspec: 4232, 21735 Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Tested-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102192656.4472-2-imre.deak@intel.com
* i915/dp/fec: Cache the FEC_CAPABLE DPCD registerAnusha Srivatsa2018-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | Similar to DSC DPCD registers, let us cache FEC_CAPABLE register to avoid using stale values. With this we can avoid aux reads everytime and instead read the cached values. v2: Avoid using memset and array for a single field. (Manasi,Jani) v3: Print FEC CAPABILITY value. (Manasi) Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102041455.15818-1-anusha.srivatsa@intel.com
* drm/i915/icl+: Sanitize port to PLL mappingImre Deak2018-11-021-0/+1
| | | | | | | | | | | | | | | BIOS can leave the PLL to port mapping enabled, even if the corresponding encoder is disabled. Disable the port mapping in this case. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-9-imre.deak@intel.com
* drm/i915: Use a helper to get the aux power domainImre Deak2018-11-021-1/+2
| | | | | | | | | | | | | | | | | From ICL onwards the AUX power domain may change dynamically based on whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so use a helper function instead of a static field to get the current domain. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-5-imre.deak@intel.com
* drm/i915: Move aux_ch to intel_digital_portImre Deak2018-11-021-1/+2
| | | | | | | | | | | | | | | | | | | | From ICL onwards all DDI/TypeC ports - even working in HDMI mode - need to know their corresponding AUX CH, so move the field to a common struct. No functional change. v3: - Add code comment about which ports aux_ch is used for. (Jose) Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-3-imre.deak@intel.com
* drm/i915/icl: Find DSI presence for ICLMadhav Chauhan2018-11-011-0/+3
| | | | | | | | | | | | | | This patch detects DSI presence for ICL platform by reading VBT. DSI detection is done while initializing DSI using newly added function intel_gen11_dsi_init. v2 by Jani: - Preserve old behavour of intel_bios_is_dsi_present() - s/intel_gen11_dsi_init/icl_dsi_init/g Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2324cdfc8918bda3165354e5e0d15053b1074f14.1540900289.git.jani.nikula@intel.com
* drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSCManasi Navare2018-10-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds helpers for calculating the maximum compressed BPP supported with small joiner. This also adds a helper for calculating the slice count in case of small joiner. These are inside intel_dp since they take into account hardware limitations. v6: * Take mode_clock and mode_hdisplay as input arguments so that this can be called in intel_dp_mode_valid (Manasi) v5: * Get the max slice width from DPCD * Check against Min_Slice_width of 2560 (Anusha) v4: * #defines for PPR in slice count helper (Gaurav) v3: * Simply logic for bpp (DK) * Limit the valid slice count by max supported by Sink (Manasi) v2: * Change the small joiner RAM buffer constant as bspec changed (Manasi) * rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha) Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-5-manasi.d.navare@intel.com
* drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP InitManasi Navare2018-10-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting GEN 11. This patch implements the discovery phase of DSC. On hotplug, source reads the DSC DPCD register set (0x00060 - 0x0006F) to read the decompression capabilities of the sink device. This entire block of registers is cached in intel_dp so that capability information can be used during DSC configuration phase during compute_config phase of the modeset. For eDP, this caching happens during the eDP initialization. This caching is done only for eDP and DP rev >= 1.4 v5: * Fix the block comment (Gaurav) * Fix the commit message DSC DPCD addresses (Gaurav) * Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha) v4: * Cache these only for Gen >= 11 v3: * Remove the dsc_sink_support field in intel_dp (Jani N) v2: * Clear the cached registers on hotplug always (Jani N) * Combine the eDP and DP caching in same function (Jani N) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-3-manasi.d.navare@intel.com
* drm/i915/icl: Enable DC9 as lowest possible state during screen-offAnimesh Manna2018-10-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable DC5/6 when appropriate. v2: (James Ausmus) - Also handle ICL as GEN9_LP in i915_drm_suspend_late and i915_drm_suspend_early - Add DC9 to gen9_dc_mask for ICL - Re-order GEN checks for newest platform first - Use INTEL_GEN instead of INTEL_INFO->gen - Use INTEL_GEN >= 11 instead of IS_ICELAKE - Consolidate GEN checks v3: (James Ausmus) - Also allow DC6 for ICL (Imre, Art) - Simplify !(GEN >= 11) to GEN < 11 (Imre) v4: (James Ausmus) - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the PPS regs are Always On - Rebase against upstream changes v5: (Anusha Srivatsa) - rebased against the latest upstream changes. v6: (Anusha Srivatsa) - rebased.Use INTEL_GEN consistently. - Simplify the code (Rodrigo) v7: rebased. Change order according to platforms(Jyoti) v8: rebased. Change the check from platform specific to HAS_PCH_SPLIT(). Add comment in code to be more clear.(Rodrigo) Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Tested-by: Jyoti Yadav <jyoti.r.yadav@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181029221410.4423-1-anusha.srivatsa@intel.com
* drm/i915: wrapping all hdcp var into intel_hdcpRamalingam C2018-10-291-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Considering significant number of HDCP specific variables, it will be clean to have separate struct for HDCP. New structure called intel_hdcp is added within intel_connector. v2: struct hdcp statically allocated. [Sean Paul] enable and disable function parameters are retained.[Sean Paul] v3: No Changes. v4: Commit msg is rephrased [Uma] v5: Comment for mutex definition. v6: hdcp_ prefix from all intel_hdcp members are removed [Sean Paul] inline function intel_hdcp_to_connector is defined [Sean Paul] v7: %s/uint64_t/u64 v8: Rebased Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-2-git-send-email-ramalingam.c@intel.com
* drm/i915/gen11: Program the scalers correctly for planar formats, v3.Maarten Lankhorst2018-10-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma upsampler to upscale YUV420 to YUV444 and the scaler should only be used for upscaling. Because of this we shouldn't program the scalers in planar mode if NV12 and the chroma upsampler are used. Instead program the scalers like on normal planes. Sprite 2 and 3 have no dedicated scaler, and need to program the selected Y plane in the scaler mode. Changes since v1: - Make the comment less confusing. Changes since v2: - Fix checkpatch warning (Matt) - gen10- -> Pre-gen11 (Ville) - PS_SCALER_MODE_PACKED -> PS_SCALER_MODE_NORMAL. (Matt) - Add comment about scaler mode in intel_atomic_setup_scaler(). (Matt) - Rename need_scaling to need_scaler. (Matt) - Move the crtc need_scaling check to skl_update_scaler_crtc(). Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181018115134.9061-6-maarten.lankhorst@linux.intel.com
* drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v5.Maarten Lankhorst2018-10-241-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make NV12 working on icl, we need to update 2 planes simultaneously. I've chosen to do this in the CRTC step after plane validation is done, so we know what planes are (in)visible. The linked Y plane will get updated in intel_plane_update_planes_on_crtc(), by the call to update_slave, which gets the master's plane_state as argument. The link requires both planes for atomic_update to work, so make sure skl_ddb_add_affected_planes() adds both states. Changes since v1: - Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers. - Put all the state updating login in intel_plane_atomic_check_with_state(). - Clean up changes in intel_plane_atomic_check(). Changes since v2: - Fix intel_atomic_get_old_plane_state() to actually return old state. - Move visibility changes to preparation patch. - Only try to find a Y plane on gen11, earlier platforms only require a single plane. Changes since v3: - Fix checkpatch warning about to_intel_crtc() usage. - Add affected planes from icl_add_linked_planes() before check_planes(), it's a cleaner way to do this. (Ville) Changes since v4: - Clear plane links in icl_check_nv12_planes() for clarity. - Only pass crtc_state to icl_check_nv12_planes(). - Use for_each_new_intel_plane_in_state() in icl_check_nv12_planes. - Rename aux to linked. (Ville) Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181022135152.15324-1-maarten.lankhorst@linux.intel.com [mlankhorst: Change bool slave to u32, to satisfy checkpatch] [mlankhorst: Add WARN_ON's based on Ville's suggestion]
* drm/i915/debugfs: hdcp capability of a sinkRamalingam C2018-10-241-0/+7
| | | | | | | | | | | | | Add a debugfs entry for providing the hdcp capabilities of the sink connected to the HDCP capable connectors. v2: Squashed the sink's hdcp capability into this patch. [Daniel] Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1540286550-20399-4-git-send-email-ramalingam.c@intel.com
* drm/i915/quirks: pass dev_priv instead of drm dev to quirk codeJani Nikula2018-10-181-1/+1
| | | | | | | | | | | Pass the type we want to simplify. No functional changes. v2: s/dev_priv/i915/g (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181017093539.5468-1-jani.nikula@intel.com
* drm/i915: split out display quirks to a new fileJani Nikula2018-10-171-0/+3
| | | | | | | | | Reduce intel_display.c by splitting out intel_quirks.c. No functional changes. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181016144228.18267-1-jani.nikula@intel.com
* drm/i915: rename and move intel_get_pipe_from_connector()Jani Nikula2018-10-171-2/+1
| | | | | | | | | | Rename intel_get_pipe_from_connector() to intel_connector_get_pipe() and move it near its connector function friends in intel_connector.c. No functional changes. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181016145044.3924-1-jani.nikula@intel.com
* drm/i915/icl: create function to identify combophy portMahesh Kumar2018-10-161-0/+1
| | | | | | | | | | | | | | | | This patch creates a function/wrapper to check if port is combophy port instead of explicitly comparing ports. Changes since V1: - keep all intel_port_is_* helper together (Lucas) Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181004085043.10154-1-mahesh1.kumar@intel.com
* drm/i915: Make intel_dp_set_m_n take crtc_stateMaarten Lankhorst2018-10-161-1/+2
| | | | | | | | | | Another user of crtc->config gone. The functions it calls also needed crtc->config, so convert those as well. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [mlankhorst: Still pass m_n struct to intel_pch_transcoder_set_m_n (Ville)] Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181011100457.8776-3-maarten.lankhorst@linux.intel.com
* drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCONShashank Sharma2018-10-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LSPCON chips can generate YCBCR outputs, if asked nicely :). In order to generate YCBCR 4:2:0 outputs, a source must: - send YCBCR 4:4:4 signals to LSPCON - program color space as 4:2:0 in AVI infoframes Whereas for YCBCR 4:4:4 outputs, the source must: - send YCBCR 4:4:4 signals to LSPCON - program color space as 4:4:4 in AVI infoframes So for both 4:2:0 as well as 4:4:4 outputs, we are driving the pipe for YCBCR 4:4:4 output, but AVI infoframe's color space information indicates LSPCON FW to start scaling down from YCBCR 4:4:4 and generate YCBCR 4:2:0 output. As the scaling is done by LSPCON device, we need not to reserve a scaler for 4:2:0 outputs. V2: rebase V3: Addressed review comments from Ville - add enum crtc_output_format instead of bool ycbcr420 - use crtc_output_format=4:4:4 for modeset of LSPCON 4:2:0 output cases in this way we will have YCBCR 4:4:4 framework ready (except the ABI part) V4: Added r-b from Maarten (for v3) Addressed review comments from Ville: - Do not add a non-atomic state variable to determine lspcon output. Instead add bool in CRTC state to indicate lspcon based scaling. V5: Addressed review comments from Ville: - Change the state bool name from external scaling to something more relavent. - Keep the info and adjusted_mode structures const. - use crtc_state instead of pipe_config. - Push all the config change into lspcon_ycbcr420_config function. V6: Rebase, small changes to accommodate changes in patch 2. V7: Fixed checkpatch warnings for alignment V8: Rebase PS: Ignored following warnings to match the current formatting: drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON -:53: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #53: FILE: drivers/gpu/drm/i915/i915_reg.h:8721: +#define TRANS_MSA_SAMPLING_444 (2<<1) ^ -:54: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #54: FILE: drivers/gpu/drm/i915/i915_reg.h:8722: +#define TRANS_MSA_CLRSP_YCBCR (2<<3) V9: Rebase V10: Rebase V11: Rebase Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-8-git-send-email-shashank.sharma@intel.com
* drm/i915: Write AVI infoframes for MCA LSPCONShashank Sharma2018-10-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LSPCON is a DP branch device, so LSPCON vendors define specific methods to pass AVI infoframes to the the chip. This patch adds: - a generic wrapper function for writing AVI infoframes for all LSPCON devices. - a vendor specific function to wrire AVI infoframes into MCA LSPCON devices. V2: Rebase V3: Added r-b from Maarten V4: Rebase V5: Rebase V6: Rebase V7: Fixed checkpatch warnings for alignment V8: Rebase V9: Added the retry logic, with 50ms incremental delays while writing AVI IF V10: Changed the return value check V11: Fixed checkpatch warning V12: Rebase Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-6-git-send-email-shashank.sharma@intel.com
* drm/i915: Add AVI infoframe support for LSPCONShashank Sharma2018-10-151-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pass AVI infoframes to LSPCON devices, a source has to write them in a vendor recommended method and location. This patch series: - adds generic LSPCON infoframe setup functions. - registers these functions into existing AVI infoframe framework. - triggers these functions from modeset sequence. Next patches in the series will add vendor specific code. V2: Added new parameter to align with new definition of drm_hdmi_avi_infoframe_quant_range V3: Added r-b from Maarten (for V2) Added new parameter output_format in struct lspcon to accommodate Ville's review comments on last patch of the series V4: Addressed Ville's review comment - Do not add output_format in LSPCON state, as its non-atomic. Add this into CRTC state (added in a later patch). V5: Rebase V6: Rebase V7: Rebase V8: Rebase V9: Rebase V10: Rebase V11: Accommodated rebasing changes in intel_git_port fptrs (set_infoframes and infoframe_enabled) Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-5-git-send-email-shashank.sharma@intel.com
* drm/i915: Check LSPCON vendor OUIShashank Sharma2018-10-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel LSPCON chip is provided by 2 vendors: - Megachips America (MCA) - Parade technologies (Parade tech) Its important to know the vendor of this chip, as the address to write AVI infoframes is different for those two. This patch reads the vendor OUI signature, and marks into LSPCON encoder structure for future usages. This patch also does a small re-arrangement of the code, by moving lspcon mode change into probe function. V2: Use dp->desc for OUI detection, dont add a helper for this (Ville) V3: Rebase, Added r-b from Maarten V4: Rebase V5: Rebase V6: Rebase V7: Rebase V8: Rebase V9: Rebase V10: Rebase Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-4-git-send-email-shashank.sharma@intel.com
* drm/i915: Add CRTC output format YCBCR 4:4:4Shashank Sharma2018-10-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for YCBCR 4:4:4 CRTC output format. To do this, this patch extends the existing YCBCR 4:2:0 framework by: - Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format. - Adding case for YCBCR 4:4:4 in while setting AVI infoframes. - Adding necessary checks in modeset sequence. V3: Added this patch in the series V4: Added r-b from Maarten (for v3) Addressed review comment from Ville: Do not use (config->output_format > CRTC_OUTPUT_RGB) V5: Rebase V6: Rebase and small change, to accommodate changes in patch 2 V7: Fixed checkpatch alignment warnings V8: Rebase V9: Rebase V10: Rebase V11: Addressed review comment from Ville Missing output_format_str[INTEL_OUTPUT_FORMAT_YCBCR444] Added Ville's R-B. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-3-git-send-email-shashank.sharma@intel.com
* drm/i915: Add CRTC output format YCBCR 4:2:0Shashank Sharma2018-10-151-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we are using a bool in CRTC state (state->ycbcr420), to indicate modeset, that the output format is YCBCR 4:2:0. Now in order to support other YCBCR formats, we will need more such flags. This patch adds a new enum parameter for YCBCR 4:2:0 outputs, in the CRTC output formats and then plugs it during the modeset. V3: Added this patch in the series, to address review comments from second patchset. V4: Added r-b from Maarten (on v3) Addressed review comments from Ville: - Change the enum name to intel_output_format. - Start the enum value (INVALID) from 0 instaed of 1. - Set the crtc's output_format to RGB in encoder's compute_config. V5: Broke previous patch 1 into two parts, - first patch to add CRTC output format in general - second patch (this one) to add YCBCR 4:2:0 output format specifically. - Use ARRAY_SIZE(format_str) for output format validity check (Ville) V6: Added a separate function to calculate crtc_state->output_format, and calling it from various get_config function (Fix CI build warning) V7: Fixed checkpatch warnings for alignment V8: Rebase V9: Rebase V10: Rebase V11: Addressed review comments from Ville: - Change check for CRTC output format from > ARRAY_SIZE to >= ARRAY_SIZE. - Check for values < INTEL_OUTPUT_FORMAT_RGB is unnecessary. - No need to get CRTC YCBCR config, for pre-BDW functions. Added Ville's r-b. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-2-git-send-email-shashank.sharma@intel.com
* drm/i915: Introduce CRTC output formatShashank Sharma2018-10-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an enum "intel_output_format" to represent the output format of a particular CRTC. This enum will be used to produce a RGB/YCBCR4:4:4/YCBCR4:2:0 output format during the atomic modeset calculations. V5: - Created this separate patch to introduce and init output_format. - Initialize parameters of output_format_str respectively (Jani N). - Call it intel_output_format than crtc_output_format(Ville). - Set output format in pipe_config for every encoder (Ville). - Get rid of extra DRM_DEBUG_KMS during get_pipe_config (Ville) V6: Rebase V7: Fixed alignment warnings (checkpatch) V8: Another check[atch warning for alignment V9: Rebase V10: Rebase on top of DSI restructure V11: Addressed review comment from Ville - Set CRTC format for pre-HSW get_pipe_config() function too. Added Ville's R-B Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-1-git-send-email-shashank.sharma@intel.com
* drm/i915: move intel connector specific functions to intel_connector.cJani Nikula2018-10-101-7/+9
| | | | | | | | | | Now that we have intel_connector.c, move the connector specific functions from intel_display.c there. Fix a few checkpatch complaints while at it. No functional changes. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181010075205.7713-2-jani.nikula@intel.com
* drm/i915: rename intel_modes.c to intel_connector.cJani Nikula2018-10-101-10/+8
| | | | | | | | | | The common denominator here seems to be connector more than modes. Prepare for moving more connector functions to the same place. No functional changes. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181010075205.7713-1-jani.nikula@intel.com
* drm/i915: add a common connector type independent destroy hookJani Nikula2018-10-091-0/+1
| | | | | | | | | | | | | | | Almost all of the connector destroy functions do the same thing. The differences are in the edid, detect_edid and panel cleanups, but those are safely NULL when not initialized. Roll out a common connector destroy hook. Inspired by commit bc3213c44415 ("drm/i915: Drop the eDP check from intel_dp_connector_destroy()"). Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181009141103.20387-1-jani.nikula@intel.com
* drm/i915: Do intel_panel_destroy_backlight() laterVille Syrjälä2018-10-091-1/+0
| | | | | | | | | | | | | | | | | | | Currently we destroy the backlight during connector unregistration. That means the final modeset performed by drm_atomic_helper_shutdown() will leave the backlight on. We don't want that so let's just move intel_panel_destroy_backlight() into intel_panel_fini() which gets called during connector destuction. We still unregister the user visible backlight device during connector unregistration. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181008134641.24868-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106386
* drm/i915: Extract skl_universal_plane_init()Ville Syrjälä2018-10-081-14/+3
| | | | | | | | | | | | | | | | | | | | | | | There's not much point in following the primary vs. sprite split for the SKL+ universal plane init code. The only difference is of our own doing in the form of the .check_plane(). Let's make a small exception for that little detail and otherwise share the same code to initialize all the universal planes. Eventually we should eliminate the mess around .check_plane() as well, but for now let's be happy with some code reduction. v2: Remember to set up plane->has_fbc Make skl_plane_has_ccs() static v3: Rebase due to NV12, rename some variables v4: Don't leave the color_encoding/range props behind v5: Rebase dur to blend properties, skl_plane_max_stride() and skl_plane_check() v6: Make skl_update_plane() static Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20181005125817.22576-10-ville.syrjala@linux.intel.com
* drm/i915: Introduce intel_plane_alloc()Ville Syrjälä2018-10-081-0/+2
| | | | | | | | | | | Pull the common plane+plane_state allocation into a small helper. Reduces the amount of boilerplate in the plane initialization functions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181005125817.22576-9-ville.syrjala@linux.intel.com
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