summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/include/asic_reg
Commit message (Collapse)AuthorAgeFilesLines
* drm/amd/include: Add mmhub 9.4 reg offsets and shift-maskLeo Li2018-12-052-0/+67
| | | | | | | | | | | In particular, we need the mmMC_VM_XGMI_LFB_CNTL register, for determining if xGMI is enabled on VG20. This will be used by DC to determine the correct spread spectrum adjustment for display and audio clocks. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vcn:Add new register offset/mask for VCNJames Zhu2018-10-122-0/+32
| | | | | | | | | | Add new register offset/mask for VCN to support latest VCN implementation. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add CP_DEBUG register definition for GC9.0Tao Zhou2018-10-101-0/+2
| | | | | | | | Add CP_DEBUG register definition. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2Evan Quan2018-10-092-0/+22
| | | | | | | | | | | | | Manual fan RPM and pwm setting on vega20 are available now. V2: correct the register for fan speed setting and avoid divide-by-zero Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay/vega20: tell the correct gfx voltage V2Evan Quan2018-10-092-0/+6
| | | | | | | | | | Export the correct gfx voltage by hwmon interface. V2: update the register naming for consistency Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:Add new register offset/mask to support VCN DPG modeJames Zhu2018-09-262-0/+33
| | | | | | | | | | New register offset/mask need to be added to support VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include: update the bitfield define for PF_MAX_REGIONShaoyun Liu2018-09-101-2/+2
| | | | | | | | | Correct the definition based on vega20 register spec Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/include: Add mp 11.0 header files. (v2)Feifei Xu2018-08-272-0/+892
| | | | | | | | | | Add the system management controller v11.0 header files. v2: cleanup Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/include: add thm 11.0.2 headersEvan Quan2018-08-272-0/+123
| | | | | | | | Headers for thermal controller. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)Feifei Xu2018-08-274-0/+8026
| | | | | | | | | | | These are the System DMA register headers for vega20. v2: cleanups (Alex) v3: add missing licenses (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/include: Add nbio 7.4 header files (v4)Feifei Xu2018-08-272-0/+53063
| | | | | | | | | | v2: Cleanups (Alex) v3: More updates (Alex) v4: more cleanups (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add system interrupt mask for jrbcBoyuan Zhang2018-08-271-0/+2
| | | | | | | | Add new mask for enabling system interrupt for jrbc. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Leo Liu <leo.liu at amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add system interrupt register offset headerBoyuan Zhang2018-08-271-0/+2
| | | | | | | | Add new register offset for enabling system interrupt. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Leo Liu <leo.liu at amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add more jpeg register offset headersBoyuan Zhang2018-06-151-0/+20
| | | | | | | | Add more jpeg registers defines that are needed for jpeg ring functions Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include: Update df 3.6 mask and shift definitionShaoyun Liu2018-06-131-4/+4
| | | | | | | | The register field hsas been changed in df 3.6, update to correct setting Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add new DF 1.7 register defsAlex Deucher2018-05-232-0/+8
| | | | | | Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add df 3.6 headersAlex Deucher2018-05-183-0/+107
| | | | | | | Needed for vega20. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd: Add dce-12.1 gpio aux registers (v2)Roman Li2018-05-172-0/+164
| | | | | | | | | | | | Updating dce12 register headers by adding dc registers required for potential DP LTTPR support. v2: fix mode change Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add df v1_7 header filesHawking Zhang2018-04-113-0/+107
| | | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add CM_TEST_DEBUG regs for DCNHarry Wentland2018-04-112-3/+24
| | | | | | | | We'd like to use them for reading DCN debug status. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include: Add ip header files for vega12.Feifei Xu2018-03-216-0/+52499
| | | | | | | | | | Add ip header files for IPs with a delta for vg12: GC, MMHUB, OSS Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-By: Ken Wang <ken.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header filesTom St Denis2018-03-072-0/+32808
| | | | | | | | These are required by umr to properly parse bitfield offsets. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROLHarry Wentland2018-02-191-0/+14
| | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <tony.cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Export registers for read vddc on VI/Vega10Rex Zhu2018-02-194-2/+11
| | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: remove some old gc 9.x registersAlex Deucher2017-12-134-80/+0
| | | | | | | Leftover from bring up. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 vcn header files.Feifei Xu2017-12-063-202/+0
| | | | | | | | | Cleanup asic_reg/raven1/VCN folder. Remove unused vcn_1_0_default.h. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 thm header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | | Cleanup asic_reg/raven1/THM folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 nbio header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | | Cleanup asic_reg/raven1/NBIO folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 mp header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | | Cleanup asic_reg/raven1/MP folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 mmhub header files.Feifei Xu2017-12-063-1028/+0
| | | | | | | | | Cleanup asic_reg/raven1/MMHUB folder.Remove unused mmhub_9_1_default.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 gc header files.Feifei Xu2017-12-063-35196/+0
| | | | | | | | | | Cleanup asic_reg/raven1/GC folder. Remove unused files: gc_9_1_default.h gc_9_1_sh_mask.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 dcn header files.Feifei Xu2017-12-063-7988/+0
| | | | | | | | | | Cleanup asic_reg/raven1/DCN folder.Remove unused dcn_1_0_default.h. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup raven1 sdma header files.Feifei Xu2017-12-063-1658/+0
| | | | | | | | | Cleanup asic_reg/raven1/SDMA0 folder.Remove unused sdma0_4_1_sh_mask.h. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 header files.Feifei Xu2017-12-062-23874/+0
| | | | | | | | Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 osssys header files.Feifei Xu2017-12-063-176/+0
| | | | | | | Cleanup asic_reg/vega10/OSSSYS folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 smuio header files.Feifei Xu2017-12-063-100/+0
| | | | | | | Cleanup asic_reg/vega10/SMUIO folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 nbif header files.Feifei Xu2017-12-063-1271/+0
| | | | | | | | Cleanup asic_reg/vega10/NBIF folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 nbio header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | Cleanup asic_reg/vega10/NBIO folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 mmhub header files.Feifei Xu2017-12-063-0/+0
| | | | | | | Cleanup asic_reg/vega10/MMHUB folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 gc header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | | | Cleanup asic_reg/vega10/GC folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 vce header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | Cleanup asic_reg/vega10/VCE folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 uvd header files.Feifei Xu2017-12-063-127/+0
| | | | | | | | Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 dce header files.Feifei Xu2017-12-063-9868/+0
| | | | | | | | Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include: cleanup vega10 umc header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | Remove asic/vega10/UMC folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 thm header files.Feifei Xu2017-12-063-0/+0
| | | | | | | | Cleanup asic_reg/vega10/THM folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 athub header files.Feifei Xu2017-12-065-2739/+2498
| | | | | | | | Cleanup asic_reg/vega10/ATHUB folder,remove unused files. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 mp header files.Feifei Xu2017-12-065-2180/+1838
| | | | | | | | Cleanup asic_reg/vega10/MP folder, remove mp_9_0_default.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 hdp header files.Feifei Xu2017-12-065-927/+810
| | | | | | | | | Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include:cleanup vega10 sdma0/1 header files.Feifei Xu2017-12-0612-5316/+5316
| | | | | | | | | | To remove include/asic_reg/vega10 folder,create IP folders sdma0/1. This patch cleanup asic_reg/vega10/SDMA folders. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: New header for fields needed to determine state of ECC.David Panariti2017-12-063-0/+119
| | | | | | | | | Add header files with ECC related definitions (MASKs, SHIFTs, DEFAULTs and OFFSETS). Signed-off-by: David Panariti <David.Panariti@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
OpenPOWER on IntegriCloud