summaryrefslogtreecommitdiffstats
path: root/drivers/clk/renesas/r8a7795-cpg-mssr.c
Commit message (Collapse)AuthorAgeFilesLines
* clk: renesas: r8a7795: Add CPEX clockGeert Uytterhoeven2018-12-041-0/+1
| | | | | | | | Implement support for the CPEX clock on R-Car H3. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org>
* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-181-33/+34
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
| * clk: renesas: r8a7795: Add OSC EXTAL predivider configurationGeert Uytterhoeven2018-08-271-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR register was removed in R-Car H3 ES2.0. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car H3 SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * clk: renesas: rcar-gen3: Rename rint to .rGeert Uytterhoeven2018-08-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | All other internal clock names have a period prepended. Hence rename the internal RCLK from "rint" to ".r", and move it to the section where all other internal clocks are defined. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* | clk: renesas: use SPDX identifier for Renesas driversWolfram Sang2018-08-301-4/+1
|/ | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: renesas: r8a7795: Add CCREE clockGilad Ben-Yossef2018-06-191-0/+1
| | | | | | | | This patch adds the clock used by the CryptoCell 630p instance in the SoC. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add CR clockGeert Uytterhoeven2018-06-191-0/+1
| | | | | | | | | Add the CR core clock, which is used by the Secure Engine (SCEG). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>
* clk: renesas: r8a7795: Add Z2 clockTakeshi Kihara2018-02-121-0/+1
| | | | | | | | This patch adds Z2 clock for r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add Z clockTakeshi Kihara2018-02-121-0/+1
| | | | | | | | This patch adds Z clock for R8A7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+2
| | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017, the parent clock of the INTC-AP module clock on R-Car H3 ES2.0 is S0D3. This change has no functional impact. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven2017-08-161-17/+17
| | | | | | | | | | | On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider value different from one. Extend struct rcar_gen3_cpg_pll_config to handle this. As all multipliers and dividers are small, table size increase can be kept limited by storing them in u8s instead of unsigned ints, which saves ca. 0.5 KiB for a generic kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0Geert Uytterhoeven2017-05-151-13/+26
| | | | | | | | | | | | Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual Rev. 0.53E. These have no user-visible effect, as the clock frequencies stay the same. Fixes: 5573d194128b4733 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a7795: Add HS-USB ch3 clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add USB-DMAC ch3 clockTakeshi Kihara2017-05-151-0/+2
| | | | | | | | | This patch supports the clock of USB-DMAC ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add EHCI/OHCI ch3 clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | | This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add support for R-Car H3 ES2.0Geert Uytterhoeven2017-03-301-50/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Clock Pulse Generator / Module Standby and Software Reset module in R-Car H3 ES2.0 differs from ES1.x in the following areas: - More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12), - Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR, SYS-DMAC, VIN, VSPB, VSPI, - Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2, USB3-IF1, VSPD3, VSPI2, - Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1. The goal is twofold: 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary for now, 2. Make it clear which code supports ES1.x, so it can easily be identified and removed later, when production SoCs are deemed ubiquitous. This is achieved by: - Updating the clock tables for the latest revision (ES2.0), but not removing clocks that only exist on earlier revisions (ES1.x), - Detecting the SoC revision at runtime using the new soc_device_match() API, and fixing up the clocks tables to match the actual SoC revision, by: - NULLifying core and module clocks of modules that do not exist, - Reparenting module clocks that have a different parent on ES1.x. Based on R-Car Gen3 Hardware User's Manual rev. 0.53E. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven2017-03-211-1/+1
| | | | | | | | Pass the mode pin states from the SoC-specific CPG/MSSR driver to the R-Car Gen3 CPG driver core, as their state will be needed to make some core clock configuration decisions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Reformat core clock tableGeert Uytterhoeven2017-03-211-10/+10
| | | | | | | For easier comparison with other clock drivers. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct name of watchdog clockGeert Uytterhoeven2017-03-211-1/+1
| | | | | | There's only a single watchdog clock, and it's named "rwdt". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACsGeert Uytterhoeven2017-03-211-2/+2
| | | | | | | | | The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which maps to S3D1 on R-Car H3 ES1.x. All module clocks must be sorted by clock ID. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
* clk: renesas: r8a7795: Add IMR clocksSergei Shtylyov2017-03-061-0/+4
| | | | | | | | | | | Add the IMR[0-3] clocks to the R8A7795 CPG/MSSR driver. Based on the original (and large) patch by Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com>. Signed-off-by: Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add IIC-DVFS clockKeita Kobayashi2017-01-271-0/+1
| | | | | | | | | | | This patch adds DVFS clock for R8A7795 SoC. Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Fix HDMI parent clockTakeshi Kihara2016-11-071-1/+1
| | | | | | | | | | Correct HDMI parent clock so that the rate of the HDMI clock is 1/4 rather than 1/2 of the rate of PLL1 as per the v0.52 (Jun, 15) manual. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driverGeert Uytterhoeven2016-11-021-1/+7
| | | | | | | | | Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Merge tag 'clk-renesas-for-v4.9-tag3' of ↵Stephen Boyd2016-09-141-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk driver updates from Geert Uytterhoeven: - External crystal selection for RZ/A1, - CMT clocks for R-Car H3 and M3-W, - RAVB and Thermal clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add CMT clocks clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add RAVB clock clk: renesas: r8a7796: Add THS/TSC clock clk: renesas: rz: Select EXTAL vs USB clock
| * clk: renesas: r8a7795: Add CMT clocksBui Duc Phuc2016-09-121-0/+4
| | | | | | | | | | | | | | This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a7795: Fix SD clocksYoshihiro Shimoda2016-08-111-4/+5
|/ | | | | | | | | | | | | | | | According to the datasheet, SDn clocks are from the SDSRC clock. And the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal core clock. Otherwise, since the sdhi driver will calculate clock for a sd card using the wrong parent clock rate, and then performance will be not good. Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: r8a7795: Add THS/TSC clockKhiem Nguyen2016-06-211-0/+1
| | | | | Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add DRIF clockRamesh Shanmugasundaram2016-06-211-0/+8
| | | | | | | This patch adds DRIF module clocks for r8a7795 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct lvds clock parentGeert Uytterhoeven2016-06-211-1/+1
| | | | | | | | | | | According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* clk: renesas: r8a7795: Provide FDP1 clocksKieran Bingham2016-06-211-0/+3
| | | | | | Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kieran Bingham <kieran@bingham.xyz> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Extract common R-Car Gen3 support codeGeert Uytterhoeven2016-06-061-355/+5
| | | | | | | | | | | | | Extract the code to support parts common to all members of the R-Car Gen3 SoC family into a separate file, to ease sharing among SoC-specific drivers. Note that while the cpg_pll_configs[] arrays and the selection of the config based on the MODE bits are identical on R-Car H3 and R-Car M3-W, they are not common, and may be different on other R-Car Gen3 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a7795: Add VIN clocksNiklas Söderlund2016-04-261-0/+8
| | | | | Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add CSI2 clocksNiklas Söderlund2016-04-261-0/+5
| | | | | Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: add RWDT clockWolfram Sang2016-04-061-0/+1
| | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: add R clkWolfram Sang2016-04-061-0/+16
| | | | | | | | | | | | R can select between two parents. We deal with it like this: During initialization, check if EXTALR is populated. If so, use it for R. If not, use R_Internal. clk_mux doesn't help here because we don't want to switch parents depending on the clock rate. The clock rate (and source) should stay constant for the watchdog, so I think a setup like this during initialization makes sense. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: add OSC and RINT clocksWolfram Sang2016-04-061-0/+5
| | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: make SD clk definition specific for GEN3Wolfram Sang2016-03-291-4/+7
| | | | | | | | | About SD clocks: The clock type is Gen3 specific, the callbacks are all Gen3 specific; I think the clock definition should also be Gen3 specific and not in the general header file. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: add PWM clockUlrich Hecht2016-03-291-0/+1
| | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: move drivers to renesas directorySimon Horman2016-03-031-0/+638
This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename directories that only hold drivers for such SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
OpenPOWER on IntegriCloud