diff options
| -rwxr-xr-x | src/usr/targeting/common/genHwsvMrwXml.pl | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl index d42e3ea41..d668d1c7e 100755 --- a/src/usr/targeting/common/genHwsvMrwXml.pl +++ b/src/usr/targeting/common/genHwsvMrwXml.pl @@ -2655,7 +2655,20 @@ sub generate_pcies my $proc_name = "n${node}:p${proc}"; print "\n<!-- $SYSNAME n${node}p${proc} PCI units -->\n"; my $max_index = 2; - # TODO RTC: 94803 + + # TODO RTC: 116091 + # Note: Originally the MRW parser created 3 PCI targets for every processor + # using a hard coded max_index value of 2. Defect SW238553 added logic to + # differentiate the number of targets based on processor type (3 for Murano, + # 4 for Brazos). This was erroneous, but by the time the problem was + # caught, it was too late in the release process to fix because the change + # would end up renumbering the HUID space. Since the extra target is + # benign, it was decided to leave the bad code in for the remainder of P8. + # This issue should be fixed in the first release of P9. If the number of + # PCI targets will be fixed across all P9 processors, simply remove the + # dynamic selection code in favor of a hard coded value. Otherwise, make + # the computation data driven by reading the # of PCI targets from + # appropriate MRW processor part. if ($CHIPNAME eq "venice") { $max_index = 3; |
