Update Default PNOR layout to include all partitions

-Updated the default PNOR layout to include all partitions
-PNOR Layout now matches PNOR Spec layout, but only single side
-Updated PNORRP to support all partitions
-Updated PNORDD to more efficiently track erases
-Added 4-byte addressing workaround to combined.simics to
   workaround SW170513 for FSP PNOR access.
-Disabled test image in VBU to save space since it is
   not used anyway

Change-Id: Ifadd21829b78868a1f2d8b762420a24f256f7a7e
RTC: 49033
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2091
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

8 files changed, 170 insertions, 87 deletions

diff --git a/src/build/buildpnor/defaultPnorLayout.xml b/src/build/buildpnor/defaultPnorLayout.xml
index fe2697aad..87a05ebf3 100644
--- a/src/build/buildpnor/defaultPnorLayout.xml
+++ b/src/build/buildpnor/defaultPnorLayout.xml
@@ -22,7 +22,7 @@
      IBM_PROLOG_END_TAG -->
 <pnor>
     <metadata>
-        <imageSize>0x800000</imageSize>
+        <imageSize>0x4000000</imageSize>
         <blockSize>0x1000</blockSize>
         <partTableSize>0x1</partTableSize>
 	<sideAOffset>0x0</sideAOffset>
@@ -37,63 +37,130 @@
         <sideless>no</sideless>
     </section>
     <section>
-        <description>Hostboot Extended image (2.5MB)</description>
+        <description>Hostboot Extended image (5MB)</description>
         <eyeCatch>HBI</eyeCatch>
-        <physicalOffset>0x1000</physicalOffset>
-        <physicalRegionSize>0x280000</physicalRegionSize>
+        <physicalOffset>0x10000</physicalOffset>
+        <physicalRegionSize>0x500000</physicalRegionSize>
         <ecc>no</ecc>
         <source>File</source>
         <sideless>no</sideless>
     </section>
     <section>
-        <description>Module VPD (512K)</description>
-        <eyeCatch>MVPD</eyeCatch>
-        <physicalOffset>0x281000</physicalOffset>
+        <description>Centaur SBE (512K)</description>
+        <eyeCatch>SBEC</eyeCatch>
+        <physicalOffset>0xA10000</physicalOffset>
         <physicalRegionSize>0x80000</physicalRegionSize>
-        <actualRegionSize>0x80000</actualRegionSize>
         <ecc>no</ecc>
         <source>Blank</source>
-        <sideless>yes</sideless>
+        <sideless>no</sideless>
+    </section>
+    <section>
+        <description>SBE-IPL (Staging Area) (256K)</description>
+        <eyeCatch>SBE</eyeCatch>
+        <physicalOffset>0xB10000</physicalOffset>
+        <physicalRegionSize>0x40000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>Blank</source>
+        <sideless>no</sideless>
+    </section>
+    <section>
+        <description>Sleep Winkle Ref Image (1MB)</description>
+        <eyeCatch>WINK</eyeCatch>
+        <physicalOffset>0xB90000</physicalOffset>
+        <physicalRegionSize>0x100000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>Blank</source>
+        <sideless>no</sideless>
+    </section>
+    <section>
+        <description>Payload (20MB)</description>
+        <eyeCatch>PAYLOAD</eyeCatch>
+        <physicalOffset>0xD90000</physicalOffset>
+        <physicalRegionSize>0x1400000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>Blank</source>
+        <sideless>no</sideless>
+    </section>
+    <section>
+        <description>Special PNOR Test Space (32K)</description>
+        <eyeCatch>TEST</eyeCatch>
+        <physicalOffset>0x3590000</physicalOffset>
+        <physicalRegionSize>0x8000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>Blank</source>
+        <sideless>no</sideless>
+        <testonly>yes</testonly>
+    </section>
+    <section>
+        <description>Hostboot Data (1M)</description>
+        <eyeCatch>HBD</eyeCatch>
+        <physicalOffset>0x3B82000</physicalOffset>
+        <physicalRegionSize>0x100000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>File</source>
+        <sideless>no</sideless>
+    </section>
+    <section>
+        <description>Guard Data (16K)</description>
+        <eyeCatch>GUARD</eyeCatch>
+        <physicalOffset>0x3D82000</physicalOffset>
+        <physicalRegionSize>0x4000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>Blank</source>
+        <sideless>no</sideless>
+    </section>
+    <section>
+        <description>Hostboot Error Logs (128K)</description>
+        <eyeCatch>HBEL</eyeCatch>
+        <physicalOffset>0x3D8A000</physicalOffset>
+        <physicalRegionSize>0x20000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>Blank</source>
+        <sideless>no</sideless>
     </section>
     <section>
         <description>DIMM JEDEC (256K)</description>
         <eyeCatch>DJVPD</eyeCatch>
-        <physicalOffset>0x301000</physicalOffset>
+        <physicalOffset>0x3DCA000</physicalOffset>
         <physicalRegionSize>0x40000</physicalRegionSize>
-        <actualRegionSize>0x40000</actualRegionSize>
         <ecc>no</ecc>
         <source>Blank</source>
         <sideless>yes</sideless>
     </section>
     <section>
-        <description>Hostboot Data (512K)</description>
-        <eyeCatch>HBD</eyeCatch>
-        <physicalOffset>0x341000</physicalOffset>
+        <description>Module VPD (512K)</description>
+        <eyeCatch>MVPD</eyeCatch>
+        <physicalOffset>0x3E0A000</physicalOffset>
         <physicalRegionSize>0x80000</physicalRegionSize>
         <ecc>no</ecc>
-        <source>File</source>
-        <sideless>no</sideless>
+        <source>Blank</source>
+        <sideless>yes</sideless>
     </section>
     <section>
-        <description>Hostboot Base (512K)</description>
+        <description>Centaur VPD (256K)</description>
+        <eyeCatch>CVPD</eyeCatch>
+        <physicalOffset>0x3E8A000</physicalOffset>
+        <physicalRegionSize>0x40000</physicalRegionSize>
+        <ecc>no</ecc>
+        <source>Blank</source>
+        <sideless>yes</sideless>
+    </section>
+    <section>
+        <description>Hostboot Base (576K)</description>
         <eyeCatch>HBB</eyeCatch>
-        <physicalOffset>0x3C1000</physicalOffset>
-        <physicalRegionSize>0x80000</physicalRegionSize>
-        <actualRegionSize>0x80000</actualRegionSize>
+        <physicalOffset>0x3ECA000</physicalOffset>
+        <physicalRegionSize>0x90000</physicalRegionSize>
         <ecc>no</ecc>
         <source>File</source>
         <sideless>no</sideless>
     </section>
     <section>
-        <description>Special PNOR Test Space (32K)</description>
-        <eyeCatch>TEST</eyeCatch>
-        <physicalOffset>0x441000</physicalOffset>
-        <physicalRegionSize>0x8000</physicalRegionSize>
-        <actualRegionSize>0x8000</actualRegionSize>
+        <description>Global Data (36K)</description>
+        <eyeCatch>GLOBAL</eyeCatch>
+        <physicalOffset>0x3FEA000</physicalOffset>
+        <physicalRegionSize>0x9000</physicalRegionSize>
         <ecc>no</ecc>
         <source>Blank</source>
         <sideless>no</sideless>
-        <testonly>yes</testonly>
     </section>
-
 </pnor>
diff --git a/src/build/buildpnor/makefile b/src/build/buildpnor/makefile
index 1cf0f2093..458785563 100644
--- a/src/build/buildpnor/makefile
+++ b/src/build/buildpnor/makefile
@@ -42,23 +42,10 @@ $${IMGDIR}/$(1).pnor: $${IMGDIR}/hbicore_extended.bin $${IMGDIR}/$(1)_targeting.
 	    --binFile_HBI $${IMGDIR}/hbicore_extended.bin \
 	    --binFile_HBD $${IMGDIR}/$(1)_targeting.bin
 endef
-define PNOR_vbu_test_template
-$${IMGDIR}/$(1)_test.pnor: $${IMGDIR}/hbicore_extended.bin $${IMGDIR}/$(1)_targeting.bin
-	./buildpnorOld.pl --pnorLayout ./pnorLayoutVpo.xml --test \
-	    --genToc \
-	    --pnorOutBin $${IMGDIR}/$(1)_test.pnor \
-	    --binFile_part $${IMGDIR}/$(1)_test_pnor.toc \
-	    --binFile_HBI $${IMGDIR}/hbicore_test_extended.bin \
-	    --binFile_HBD $${IMGDIR}/$(1)_targeting.bin
-endef
-
-PNOR_IMAGES = $(addsuffix .pnor, $(addprefix $(IMGDIR)/, ${PNOR_TARGETS})) \
-              $(addsuffix _test.pnor, $(addprefix $(IMGDIR)/, ${PNOR_TARGETS}))
 
 PNOR_VBU_IMAGES =  $(addsuffix .pnor, $(addprefix $(IMGDIR)/, ${PNOR_VBU_TARGETS})) \
-		   $(addsuffix _test.pnor, $(addprefix $(IMGDIR)/, ${PNOR_VBU_TARGETS})) \
 
-EXTRA_CLEAN = ${PNOR_IMAGES} ${PNOR_IMAGES:.pnor=_pnor.toc} ${PNOR_VBU_IMAGES} ${PNOR_VBU_IMAGES:.pnor=_pnor.toc}
+EXTRA_CLEAN = ${PNOR_VBU_IMAGES} ${PNOR_VBU_IMAGES:.pnor=_pnor.toc}
 
 include ${ROOTPATH}/config.mk
 
@@ -68,4 +55,3 @@ buildpnor: ${PNOR_VBU_IMAGES}
 
 #VBU Specific images
 $(foreach pnor,$(PNOR_VBU_TARGETS),$(eval $(call PNOR_vbu_template,$(pnor))))
-$(foreach pnor,$(PNOR_VBU_TARGETS),$(eval $(call PNOR_vbu_test_template,$(pnor))))
diff --git a/src/build/simics/combined.simics b/src/build/simics/combined.simics
index b21247e4c..9e66a731a 100755
--- a/src/build/simics/combined.simics
+++ b/src/build/simics/combined.simics
@@ -19,3 +19,10 @@ try {
         }            
     }
 } except { echo "ERROR: Failed to load tools in combined.simics." }
+
+# 4-byte PNOR addressing workaround for Defect SW170513.
+# Only needed in combined configs to enable FSP communication.  Hostboot
+# PNOR DD covers hostboot access.  Remove with RTC: 51500
+try {
+    fpga0.sfc_master->state_three_bytes=0
+} except { echo "ERROR: Failed to run 4-byte PNOR address workaround in combined.simics." }
diff --git a/src/build/simics/startup.simics b/src/build/simics/startup.simics
index 050dc85cf..45cece49d 100755
--- a/src/build/simics/startup.simics
+++ b/src/build/simics/startup.simics
@@ -10,8 +10,8 @@ python "os.environ['HB_MACHINE'] = \""+$hb_machine+"\""
 # Preload VPD in PNOR
 try {
     run-python-file (lookup-file hbfw/hb-pnor-mvpd-preload.py)
-    fpga0.sfc_master_mem.load-file ./sysmvpd.dat 0x281000
-    fpga0.sfc_master_mem.load-file ./sysspd.dat 0x301000
+    fpga0.sfc_master_mem.load-file ./sysmvpd.dat 0x3E0A000
+    fpga0.sfc_master_mem.load-file ./sysspd.dat 0x3DCA000
 } except { echo "ERROR: Failed to preload VPD into PNOR." }
 
 # Load HB debug tools.
diff --git a/src/include/usr/pnor/pnorif.H b/src/include/usr/pnor/pnorif.H
index 055dadbb9..533c7f932 100644
--- a/src/include/usr/pnor/pnorif.H
+++ b/src/include/usr/pnor/pnorif.H
@@ -38,20 +38,21 @@ enum SectionId
     TOC,            /**< Table of Contents */
             // Value of HB_EXT_CODE must be 1 for debug framework.
     HB_EXT_CODE,    /**< Hostboot Extended Image */
+    GLOBAL_DATA,    /**< Global Data */
+    HB_BASE_CODE,   /**< Hostboot Base Image */
+    CENTAUR_SBE,    /**< Centaur Self-Boot Engine image */
+    SBE_IPL,        /**< Self-Boot Engine IPL image */
+    WINK,           /**< Sleep Winkle Reference image */
+    PAYLOAD,        /**< HAL/OPAL */
     HB_DATA,        /**< Hostboot Data */
+    GUARD_DATA,     /**< Guard Data */
+    HB_ERRLOGS,     /**< Hostboot Error log Repository */
     DIMM_JEDEC_VPD, /**< DIMM JEDEC VPD */
     MODULE_VPD,     /**< Module VPD */
-    HB_BASE_CODE,   /**< Hostboot Base Image */
+    CENTAUR_VPD,     /**< Centaur VPD */
     TEST,           /**< Scratch space for PNOR test cases */
     NUM_SECTIONS,   /**< Number of defined sections */
 
-    //Not currently used
-//    GLOBAL_DATA,    /**< Global Data */
-//    SBE_IPL,        /**< Self-Boot Engine IPL image */
-//    PAYLOAD,        /**< HAL/OPAL */
-//    HB_RUNTIME,     /**< Hostboot Runtime Image */
-//    HB_ERRLOGS,     /**< Hostboot Error log Repository */
-
     FIRST_SECTION = TOC,  /**< First section (for looping) */
     LAST_SECTION = TEST,  /**< Last section (for looping) */
     INVALID_SECTION = NUM_SECTIONS,  /**< Used for error cases, initialization */
diff --git a/src/usr/pnor/pnordd.C b/src/usr/pnor/pnordd.C
index 62982163a..ea36adf02 100644
--- a/src/usr/pnor/pnordd.C
+++ b/src/usr/pnor/pnordd.C
@@ -351,7 +351,9 @@ PnorDD::PnorDD( PnorMode_t i_mode,
 : iv_mode(i_mode)
 {
     iv_erasesize_bytes = ERASESIZE_BYTES_DEFAULT;
-    iv_erases = NULL;
+
+    //Zero out erase counter
+    memset(iv_erases, 0xff, sizeof(iv_erases));
 
     //Use real PNOR for everything except VPO
     if(0 == iv_vpoMode)
@@ -403,10 +405,7 @@ PnorDD::PnorDD( PnorMode_t i_mode,
  */
 PnorDD::~PnorDD()
 {
-    if(iv_erases)
-    {
-        delete iv_erases;
-    }
+
 }
 
 bool PnorDD::cv_sfcInitDone = false;  //Static flag to ensure we only init the SFC one time.
@@ -484,16 +483,16 @@ void PnorDD::sfcInit( )
                                     iv_erasesize_bytes);
                 if(l_err) { break; }
 
-                //create array to count erases.
-                iv_erases = new uint8_t[PNORSIZE/iv_erasesize_bytes];
-                for( uint64_t x=0; x < (PNORSIZE/iv_erasesize_bytes); x++ )
-                {
-                    iv_erases[x] = 0;
-                }
+                //Enable 4-byte addressing for Macronix-type device
+                SfcCmdReg_t sfc_cmd;
+                sfc_cmd.opcode = SPI_START4BA;
+                sfc_cmd.length = 0;
 
+                l_err = writeRegSfc(SFC_CMD_SPACE,
+                                    SFC_REG_CMD,
+                                    sfc_cmd.data32);
                 if(l_err) { break; }
 
-
             }
             else if(VPO_NOR_ID == cv_nor_chipid)
             {
@@ -1361,11 +1360,29 @@ errlHndl_t PnorDD::eraseFlash(uint32_t i_address)
             break;
         }
 
-        if(iv_erases)
+        for(uint32_t idx = 0; idx < ERASE_COUNT_MAX; idx++ )
         {
-            // log the erase of this block
-            iv_erases[i_address/iv_erasesize_bytes]++;
-            TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Block 0x%.8X has %d erasures", i_address, iv_erases[i_address/iv_erasesize_bytes] );
+            if(iv_erases[idx].addr == i_address)
+            {
+                iv_erases[idx].count++;
+                TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Block 0x%.8X has %d erasures", i_address, iv_erases[idx].count );
+                break;
+
+            }
+            //iv_erases is init to all 0xff,
+            //  so can use ~0 to check for an unused position
+            else if(iv_erases[idx].addr == ~0u)
+            {
+                iv_erases[idx].addr = i_address;
+                iv_erases[idx].count = 1;
+                TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Block 0x%.8X has %d erasures", i_address, iv_erases[idx].count );
+                break;
+            }
+            else if( idx == (ERASE_COUNT_MAX - 1))
+            {
+                TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Erase counter full!  Block 0x%.8X Erased", i_address );
+                break;
+            }
         }
 
         if( (MODEL_MEMCPY == iv_mode) ||  (MODEL_LPC_MEM == iv_mode))
diff --git a/src/usr/pnor/pnordd.H b/src/usr/pnor/pnordd.H
index 1f04157ce..407315930 100644
--- a/src/usr/pnor/pnordd.H
+++ b/src/usr/pnor/pnordd.H
@@ -76,9 +76,9 @@ class PnorDD
     enum PnorMode_t {
         MODEL_UNKNOWN,   /**< Invalid */
         MODEL_MEMCPY,    /**< No LPC logic, just do memcpy into cache area */
-        MODEL_LPC_MEM,   /**< Break into 32-bit LPC ops but use memcpy into cache area */
-        MODEL_REAL_CMD,  /**< Code for real hardware or complete sim model using Commands based reads */
-        MODEL_REAL_MMIO, /**< Code for real hardware or complete sim model using MMIO reads-Not currently implemented */
+        MODEL_LPC_MEM,   /**< Break into 32-bit LPC ops but use fake-PNOR */
+        MODEL_REAL_CMD,  /**< Code for real HW using Command based reads */
+        MODEL_REAL_MMIO, /**< Code for real hardware using MMIO reads */
     };
 
     /**
@@ -96,6 +96,11 @@ class PnorDD
 
   protected:
 
+    struct EraseInfo_t
+    {
+        uint32_t addr;  /**< Address of the erase block */
+        uint32_t count;  /**< Num Erases of block */
+    };
 
     /**
      * @brief LPC HC Registers
@@ -114,6 +119,7 @@ class PnorDD
      */
     enum SpiConfigInfo {
         SPI_GET_CHIPID_OP   = 0x9F, /**< Default Op code for getting NOR ChipID */
+        SPI_START4BA        = 0x37, /**< Enable Macronix 4-Byte addressing */
 
         SPI_SIM_SM_ERASE_OP = 0x00000020, /**< Simics Op Code for Small Erase */
         SPI_SIM_SM_ERASE_SZ = 0x1000, /**< Simics Small Erase Size */
@@ -350,9 +356,9 @@ class PnorDD
         LPCHC_REG_SPACE = 0xC0012000, /**< LPC Host Ctlr Register Space */
 
         LPC_DIRECT_READ_OFFSET = 0xFC000000,
-        LPC_SFC_CMDREG_OFFSET = 0xF0000C00,  /** LPC Offest to SFC Command Registers */
-        LPC_SFC_CMDBUF_OFFSET = 0xF0000D00,  /** LPC Offest to SFC Command Buffer space */
-        LPC_SFC_MMIO_OFFSET   = 0xF4000000,  /** LPC Offset into SFC MMIO Direct Read space */
+        LPC_SFC_CMDREG_OFFSET = 0xF0000C00, /** LPC Offest to SFC Cmd Regs */
+        LPC_SFC_CMDBUF_OFFSET = 0xF0000D00, /** LPC Off to SFC Cmd Buf space */
+        LPC_SFC_MMIO_OFFSET = 0xF4000000, /** LPC Off to SFC Direct Read space*/
         LPC_TOP_OF_FLASH_OFFSET = 0xFFFFFFFF,
 
         ECCB_CTL_REG  = 0x000B0020, /**< ECCB Control Reg (FW) */
@@ -365,8 +371,8 @@ class PnorDD
 
         LPC_STAT_REG_ERROR_MASK = 0xFC0000000007F700, /**< Error Bits */
 
-        PNORSIZE = 16 * MEGABYTE, //@fixme - read from TOC instead  (RTC: 42252)
-        ERASESIZE_BYTES_DEFAULT = 4 * KILOBYTE, /**< Minimum Erase Block (bytes) */
+        ERASE_COUNT_MAX = 64,  /**<Max number of tracked erase blocks */
+        ERASESIZE_BYTES_DEFAULT = 4 * KILOBYTE, /**< Min Erase Block (bytes) */
         ECCB_POLL_TIME_NS = 400000, /**< max time from Manfred Walz is 400ms */
         ECCB_POLL_INCR_NS = 10, /**< minimum increment during poll */
     };
@@ -537,13 +543,10 @@ class PnorDD
      */
     static mutex_t cv_mutex;
 
-    //TODO: Make this dynamically sized.
     /**
      * @brief Track PNOR erases for wear monitoring
-     *    (making this static so tools can find it easier)
-     *    track writes by page (=erase block)
      */
-    uint8_t* iv_erases;
+    EraseInfo_t iv_erases[ERASE_COUNT_MAX];
 
     /**
      * @brief Determine how much of the PNOR logic to use,
diff --git a/src/usr/pnor/pnorrp.C b/src/usr/pnor/pnorrp.C
index e3831e2b4..7e27bf7e6 100644
--- a/src/usr/pnor/pnorrp.C
+++ b/src/usr/pnor/pnorrp.C
@@ -51,19 +51,21 @@ TRAC_INIT(&g_trac_pnor, "PNOR", 4096); //4K
 const char* cv_EYECATCHER[] = {  //@todo - convert there to uint64_t
     "part",   /**< PNOR::TOC           : Table of Contents */
     "HBI",    /**< PNOR::HB_EXT_CODE   : Hostboot Extended Image */
+    "GLOBAL", /**< PNOR::GLOBAL_DATA   : Global Data */
+    "HBB",    /**< PNOR::HB_BASE_CODE  : Hostboot Base Image */
+    "SBEC",   /**< PNOR::CENTAUR_SBE   : Centaur Self-Boot Engine image */
+    "SBE",    /**< PNOR::SBE_IPL       : Self-Boot Enginer IPL image */
+    "WINK",   /**< PNOR::WINK          : Sleep Winkle Reference image */
+    "PAYLOAD",/**< PNOR::PAYLOAD       : HAL/OPAL */
     "HBD",    /**< PNOR::HB_DATA       : Hostboot Data */
+    "GUARD",  /**< PNOR::GUARD_DATA    : Hostboot Data */
+    "HBEL",   /**< PNOR::HB_ERRLOGS    : Hostboot Error log Repository */
     "DJVPD",  /**< PNOR::DIMM_JEDEC_VPD: Dimm JEDEC VPD */
     "MVPD",   /**< PNOR::MODULE_VPD    : Module VPD */
-    "HBB",    /**< PNOR::HB_BASE_CODE  : Hostboot Base Image */
+    "CVPD",   /**< PNOR::CENTAUR_VPD   : Centaur VPD */
     "TEST",   /**< PNOR::TEST          : Test space for PNOR*/
 
     //Not currently used
-//    "GLOBAL", /**< PNOR::GLOBAL_DATA   : Global Data */
-//    "SBE",    /**< PNOR::SBE_IPL       : Self-Boot Enginer IPL image */
-//    "XXX",    /**< PNOR::HB_ERRLOGS    : Hostboot Error log Repository */
-//    "HBR",    /**< PNOR::HB_RUNTIME    : Hostboot Runtime Image */
-//    "PART",   /**< PNOR::KVM_PART_INFO : KVM Partition Information */
-//    "XXX",    /**< PNOR::CODE_UPDATE   : Code Update Overhead */
 //    "XXX",    /**< NUM_SECTIONS       : Used as invalid entry */
 };