From 799ce7095b6a019d4103685ae85558418b9368c7 Mon Sep 17 00:00:00 2001 From: Adam Muhle Date: Thu, 18 Oct 2012 13:08:15 -0500 Subject: Update Default PNOR layout to include all partitions -Updated the default PNOR layout to include all partitions -PNOR Layout now matches PNOR Spec layout, but only single side -Updated PNORRP to support all partitions -Updated PNORDD to more efficiently track erases -Added 4-byte addressing workaround to combined.simics to workaround SW170513 for FSP PNOR access. -Disabled test image in VBU to save space since it is not used anyway Change-Id: Ifadd21829b78868a1f2d8b762420a24f256f7a7e RTC: 49033 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2091 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III --- src/build/buildpnor/defaultPnorLayout.xml | 121 +++++++++++++++++++++++------- src/build/buildpnor/makefile | 16 +--- src/build/simics/combined.simics | 7 ++ src/build/simics/startup.simics | 4 +- src/include/usr/pnor/pnorif.H | 17 +++-- src/usr/pnor/pnordd.C | 49 ++++++++---- src/usr/pnor/pnordd.H | 27 ++++--- src/usr/pnor/pnorrp.C | 16 ++-- 8 files changed, 170 insertions(+), 87 deletions(-) (limited to 'src') diff --git a/src/build/buildpnor/defaultPnorLayout.xml b/src/build/buildpnor/defaultPnorLayout.xml index fe2697aad..87a05ebf3 100644 --- a/src/build/buildpnor/defaultPnorLayout.xml +++ b/src/build/buildpnor/defaultPnorLayout.xml @@ -22,7 +22,7 @@ IBM_PROLOG_END_TAG --> - 0x800000 + 0x4000000 0x1000 0x1 0x0 @@ -37,63 +37,130 @@ no
- Hostboot Extended image (2.5MB) + Hostboot Extended image (5MB) HBI - 0x1000 - 0x280000 + 0x10000 + 0x500000 no File no
- Module VPD (512K) - MVPD - 0x281000 + Centaur SBE (512K) + SBEC + 0xA10000 0x80000 - 0x80000 no Blank - yes + no +
+
+ SBE-IPL (Staging Area) (256K) + SBE + 0xB10000 + 0x40000 + no + Blank + no +
+
+ Sleep Winkle Ref Image (1MB) + WINK + 0xB90000 + 0x100000 + no + Blank + no +
+
+ Payload (20MB) + PAYLOAD + 0xD90000 + 0x1400000 + no + Blank + no +
+
+ Special PNOR Test Space (32K) + TEST + 0x3590000 + 0x8000 + no + Blank + no + yes +
+
+ Hostboot Data (1M) + HBD + 0x3B82000 + 0x100000 + no + File + no +
+
+ Guard Data (16K) + GUARD + 0x3D82000 + 0x4000 + no + Blank + no +
+
+ Hostboot Error Logs (128K) + HBEL + 0x3D8A000 + 0x20000 + no + Blank + no
DIMM JEDEC (256K) DJVPD - 0x301000 + 0x3DCA000 0x40000 - 0x40000 no Blank yes
- Hostboot Data (512K) - HBD - 0x341000 + Module VPD (512K) + MVPD + 0x3E0A000 0x80000 no - File - no + Blank + yes
- Hostboot Base (512K) + Centaur VPD (256K) + CVPD + 0x3E8A000 + 0x40000 + no + Blank + yes +
+
+ Hostboot Base (576K) HBB - 0x3C1000 - 0x80000 - 0x80000 + 0x3ECA000 + 0x90000 no File no
- Special PNOR Test Space (32K) - TEST - 0x441000 - 0x8000 - 0x8000 + Global Data (36K) + GLOBAL + 0x3FEA000 + 0x9000 no Blank no - yes
- diff --git a/src/build/buildpnor/makefile b/src/build/buildpnor/makefile index 1cf0f2093..458785563 100644 --- a/src/build/buildpnor/makefile +++ b/src/build/buildpnor/makefile @@ -42,23 +42,10 @@ $${IMGDIR}/$(1).pnor: $${IMGDIR}/hbicore_extended.bin $${IMGDIR}/$(1)_targeting. --binFile_HBI $${IMGDIR}/hbicore_extended.bin \ --binFile_HBD $${IMGDIR}/$(1)_targeting.bin endef -define PNOR_vbu_test_template -$${IMGDIR}/$(1)_test.pnor: $${IMGDIR}/hbicore_extended.bin $${IMGDIR}/$(1)_targeting.bin - ./buildpnorOld.pl --pnorLayout ./pnorLayoutVpo.xml --test \ - --genToc \ - --pnorOutBin $${IMGDIR}/$(1)_test.pnor \ - --binFile_part $${IMGDIR}/$(1)_test_pnor.toc \ - --binFile_HBI $${IMGDIR}/hbicore_test_extended.bin \ - --binFile_HBD $${IMGDIR}/$(1)_targeting.bin -endef - -PNOR_IMAGES = $(addsuffix .pnor, $(addprefix $(IMGDIR)/, ${PNOR_TARGETS})) \ - $(addsuffix _test.pnor, $(addprefix $(IMGDIR)/, ${PNOR_TARGETS})) PNOR_VBU_IMAGES = $(addsuffix .pnor, $(addprefix $(IMGDIR)/, ${PNOR_VBU_TARGETS})) \ - $(addsuffix _test.pnor, $(addprefix $(IMGDIR)/, ${PNOR_VBU_TARGETS})) \ -EXTRA_CLEAN = ${PNOR_IMAGES} ${PNOR_IMAGES:.pnor=_pnor.toc} ${PNOR_VBU_IMAGES} ${PNOR_VBU_IMAGES:.pnor=_pnor.toc} +EXTRA_CLEAN = ${PNOR_VBU_IMAGES} ${PNOR_VBU_IMAGES:.pnor=_pnor.toc} include ${ROOTPATH}/config.mk @@ -68,4 +55,3 @@ buildpnor: ${PNOR_VBU_IMAGES} #VBU Specific images $(foreach pnor,$(PNOR_VBU_TARGETS),$(eval $(call PNOR_vbu_template,$(pnor)))) -$(foreach pnor,$(PNOR_VBU_TARGETS),$(eval $(call PNOR_vbu_test_template,$(pnor)))) diff --git a/src/build/simics/combined.simics b/src/build/simics/combined.simics index b21247e4c..9e66a731a 100755 --- a/src/build/simics/combined.simics +++ b/src/build/simics/combined.simics @@ -19,3 +19,10 @@ try { } } } except { echo "ERROR: Failed to load tools in combined.simics." } + +# 4-byte PNOR addressing workaround for Defect SW170513. +# Only needed in combined configs to enable FSP communication. Hostboot +# PNOR DD covers hostboot access. Remove with RTC: 51500 +try { + fpga0.sfc_master->state_three_bytes=0 +} except { echo "ERROR: Failed to run 4-byte PNOR address workaround in combined.simics." } diff --git a/src/build/simics/startup.simics b/src/build/simics/startup.simics index 050dc85cf..45cece49d 100755 --- a/src/build/simics/startup.simics +++ b/src/build/simics/startup.simics @@ -10,8 +10,8 @@ python "os.environ['HB_MACHINE'] = \""+$hb_machine+"\"" # Preload VPD in PNOR try { run-python-file (lookup-file hbfw/hb-pnor-mvpd-preload.py) - fpga0.sfc_master_mem.load-file ./sysmvpd.dat 0x281000 - fpga0.sfc_master_mem.load-file ./sysspd.dat 0x301000 + fpga0.sfc_master_mem.load-file ./sysmvpd.dat 0x3E0A000 + fpga0.sfc_master_mem.load-file ./sysspd.dat 0x3DCA000 } except { echo "ERROR: Failed to preload VPD into PNOR." } # Load HB debug tools. diff --git a/src/include/usr/pnor/pnorif.H b/src/include/usr/pnor/pnorif.H index 055dadbb9..533c7f932 100644 --- a/src/include/usr/pnor/pnorif.H +++ b/src/include/usr/pnor/pnorif.H @@ -38,20 +38,21 @@ enum SectionId TOC, /**< Table of Contents */ // Value of HB_EXT_CODE must be 1 for debug framework. HB_EXT_CODE, /**< Hostboot Extended Image */ + GLOBAL_DATA, /**< Global Data */ + HB_BASE_CODE, /**< Hostboot Base Image */ + CENTAUR_SBE, /**< Centaur Self-Boot Engine image */ + SBE_IPL, /**< Self-Boot Engine IPL image */ + WINK, /**< Sleep Winkle Reference image */ + PAYLOAD, /**< HAL/OPAL */ HB_DATA, /**< Hostboot Data */ + GUARD_DATA, /**< Guard Data */ + HB_ERRLOGS, /**< Hostboot Error log Repository */ DIMM_JEDEC_VPD, /**< DIMM JEDEC VPD */ MODULE_VPD, /**< Module VPD */ - HB_BASE_CODE, /**< Hostboot Base Image */ + CENTAUR_VPD, /**< Centaur VPD */ TEST, /**< Scratch space for PNOR test cases */ NUM_SECTIONS, /**< Number of defined sections */ - //Not currently used -// GLOBAL_DATA, /**< Global Data */ -// SBE_IPL, /**< Self-Boot Engine IPL image */ -// PAYLOAD, /**< HAL/OPAL */ -// HB_RUNTIME, /**< Hostboot Runtime Image */ -// HB_ERRLOGS, /**< Hostboot Error log Repository */ - FIRST_SECTION = TOC, /**< First section (for looping) */ LAST_SECTION = TEST, /**< Last section (for looping) */ INVALID_SECTION = NUM_SECTIONS, /**< Used for error cases, initialization */ diff --git a/src/usr/pnor/pnordd.C b/src/usr/pnor/pnordd.C index 62982163a..ea36adf02 100644 --- a/src/usr/pnor/pnordd.C +++ b/src/usr/pnor/pnordd.C @@ -351,7 +351,9 @@ PnorDD::PnorDD( PnorMode_t i_mode, : iv_mode(i_mode) { iv_erasesize_bytes = ERASESIZE_BYTES_DEFAULT; - iv_erases = NULL; + + //Zero out erase counter + memset(iv_erases, 0xff, sizeof(iv_erases)); //Use real PNOR for everything except VPO if(0 == iv_vpoMode) @@ -403,10 +405,7 @@ PnorDD::PnorDD( PnorMode_t i_mode, */ PnorDD::~PnorDD() { - if(iv_erases) - { - delete iv_erases; - } + } bool PnorDD::cv_sfcInitDone = false; //Static flag to ensure we only init the SFC one time. @@ -484,16 +483,16 @@ void PnorDD::sfcInit( ) iv_erasesize_bytes); if(l_err) { break; } - //create array to count erases. - iv_erases = new uint8_t[PNORSIZE/iv_erasesize_bytes]; - for( uint64_t x=0; x < (PNORSIZE/iv_erasesize_bytes); x++ ) - { - iv_erases[x] = 0; - } + //Enable 4-byte addressing for Macronix-type device + SfcCmdReg_t sfc_cmd; + sfc_cmd.opcode = SPI_START4BA; + sfc_cmd.length = 0; + l_err = writeRegSfc(SFC_CMD_SPACE, + SFC_REG_CMD, + sfc_cmd.data32); if(l_err) { break; } - } else if(VPO_NOR_ID == cv_nor_chipid) { @@ -1361,11 +1360,29 @@ errlHndl_t PnorDD::eraseFlash(uint32_t i_address) break; } - if(iv_erases) + for(uint32_t idx = 0; idx < ERASE_COUNT_MAX; idx++ ) { - // log the erase of this block - iv_erases[i_address/iv_erasesize_bytes]++; - TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Block 0x%.8X has %d erasures", i_address, iv_erases[i_address/iv_erasesize_bytes] ); + if(iv_erases[idx].addr == i_address) + { + iv_erases[idx].count++; + TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Block 0x%.8X has %d erasures", i_address, iv_erases[idx].count ); + break; + + } + //iv_erases is init to all 0xff, + // so can use ~0 to check for an unused position + else if(iv_erases[idx].addr == ~0u) + { + iv_erases[idx].addr = i_address; + iv_erases[idx].count = 1; + TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Block 0x%.8X has %d erasures", i_address, iv_erases[idx].count ); + break; + } + else if( idx == (ERASE_COUNT_MAX - 1)) + { + TRACFCOMP(g_trac_pnor, "PnorDD::eraseFlash> Erase counter full! Block 0x%.8X Erased", i_address ); + break; + } } if( (MODEL_MEMCPY == iv_mode) || (MODEL_LPC_MEM == iv_mode)) diff --git a/src/usr/pnor/pnordd.H b/src/usr/pnor/pnordd.H index 1f04157ce..407315930 100644 --- a/src/usr/pnor/pnordd.H +++ b/src/usr/pnor/pnordd.H @@ -76,9 +76,9 @@ class PnorDD enum PnorMode_t { MODEL_UNKNOWN, /**< Invalid */ MODEL_MEMCPY, /**< No LPC logic, just do memcpy into cache area */ - MODEL_LPC_MEM, /**< Break into 32-bit LPC ops but use memcpy into cache area */ - MODEL_REAL_CMD, /**< Code for real hardware or complete sim model using Commands based reads */ - MODEL_REAL_MMIO, /**< Code for real hardware or complete sim model using MMIO reads-Not currently implemented */ + MODEL_LPC_MEM, /**< Break into 32-bit LPC ops but use fake-PNOR */ + MODEL_REAL_CMD, /**< Code for real HW using Command based reads */ + MODEL_REAL_MMIO, /**< Code for real hardware using MMIO reads */ }; /** @@ -96,6 +96,11 @@ class PnorDD protected: + struct EraseInfo_t + { + uint32_t addr; /**< Address of the erase block */ + uint32_t count; /**< Num Erases of block */ + }; /** * @brief LPC HC Registers @@ -114,6 +119,7 @@ class PnorDD */ enum SpiConfigInfo { SPI_GET_CHIPID_OP = 0x9F, /**< Default Op code for getting NOR ChipID */ + SPI_START4BA = 0x37, /**< Enable Macronix 4-Byte addressing */ SPI_SIM_SM_ERASE_OP = 0x00000020, /**< Simics Op Code for Small Erase */ SPI_SIM_SM_ERASE_SZ = 0x1000, /**< Simics Small Erase Size */ @@ -350,9 +356,9 @@ class PnorDD LPCHC_REG_SPACE = 0xC0012000, /**< LPC Host Ctlr Register Space */ LPC_DIRECT_READ_OFFSET = 0xFC000000, - LPC_SFC_CMDREG_OFFSET = 0xF0000C00, /** LPC Offest to SFC Command Registers */ - LPC_SFC_CMDBUF_OFFSET = 0xF0000D00, /** LPC Offest to SFC Command Buffer space */ - LPC_SFC_MMIO_OFFSET = 0xF4000000, /** LPC Offset into SFC MMIO Direct Read space */ + LPC_SFC_CMDREG_OFFSET = 0xF0000C00, /** LPC Offest to SFC Cmd Regs */ + LPC_SFC_CMDBUF_OFFSET = 0xF0000D00, /** LPC Off to SFC Cmd Buf space */ + LPC_SFC_MMIO_OFFSET = 0xF4000000, /** LPC Off to SFC Direct Read space*/ LPC_TOP_OF_FLASH_OFFSET = 0xFFFFFFFF, ECCB_CTL_REG = 0x000B0020, /**< ECCB Control Reg (FW) */ @@ -365,8 +371,8 @@ class PnorDD LPC_STAT_REG_ERROR_MASK = 0xFC0000000007F700, /**< Error Bits */ - PNORSIZE = 16 * MEGABYTE, //@fixme - read from TOC instead (RTC: 42252) - ERASESIZE_BYTES_DEFAULT = 4 * KILOBYTE, /**< Minimum Erase Block (bytes) */ + ERASE_COUNT_MAX = 64, /**