Map BAR attributes based on data from Bootloader

If the master processor has no memory behind it the entire
memory map must be modified.  Each processor has its own statically
defined map that covers both memory and MMIOs.  If the master
has no memory, its memory map is swapped with another processor.
Each processor gets a new effective fabric id that is then used
to compute all of the BAR values for those processors.

The SBE boots with a certain memory map programmed into the master
processor.  That value is then passed up through the bootloader
into Hostboot.  This value is compared to the BAR values that
Hostboot assumes it is using.  Based on that comparison, various
attributes are computed to match the effective fabric positions.

Change-Id: I2b0d1959c303df8c9c28c8f0a5b5be1e77aa154f
RTC: 173528
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40359
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

8 files changed, 187 insertions, 83 deletions

diff --git a/src/usr/lpc/lpcdd.C b/src/usr/lpc/lpcdd.C
index c84253563..fd1fa54e1 100644
--- a/src/usr/lpc/lpcdd.C
+++ b/src/usr/lpc/lpcdd.C
@@ -47,7 +47,7 @@
 #include <errl/errludlogregister.H>
 #include <initservice/taskargs.H>
 #include <config.h>
-
+#include <arch/memorymap.H>
 
 trace_desc_t* g_trac_lpc;
 TRAC_INIT( & g_trac_lpc, LPC_COMP_NAME, 2*KILOBYTE, TRACE::BUFFER_SLOW);
@@ -380,6 +380,16 @@ void block_lpc_ops( bool i_block )
     Singleton<LpcDD>::instance().lock(i_block);
 }
 
+/**
+ * @brief Return the value of the LPC BAR that the driver is using
+ */
+uint64_t get_lpc_bar( void )
+{
+    //@todo-RTC:173521-Return live value
+    return MMIO_GROUP0_CHIP0_LPC_BASE_ADDR;
+}
+
+
 }; //namespace LPC
 
 ///////////////////////////////////////////////////////////////////////////////
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 55cb75bc3..dfc247ea3 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -3085,13 +3085,6 @@ sub generate_sys
 ";
     }
 
-    #adding XSCOM_BASE_ADDRESS to the system target for HDAT
-    print "
-    <attribute><id>XSCOM_BASE_ADDRESS</id>
-        <default>0x000603FC00000000</default>
-    </attribute>
-";
-
     if( $haveFSPs == 0 )
     {
         generate_apss_adc_config()
@@ -3929,12 +3922,6 @@ sub generate_proc
        0x0006013100000000 + $nodeSize*$lognode + $chipSize*$logid );
     printf( "    </attribute>\n" );
 
-    #LPC Bus address
-    printf( "    <attribute><id>LPC_BUS_ADDR</id>\n" );
-    printf( "        <default>0x%016X</default>\n",
-       0x0006030000000000 + $nodeSize*$lognode + $chipSize*$logid );
-    printf( "    </attribute>\n" );
-
     #Nvidia Link - NPU Priviledged address
     printf( "    <attribute><id>NVIDIA_NPU_PRIVILEGED_ADDR</id>\n" );
     printf( "        <default>0x%016X</default>\n",
@@ -3983,12 +3970,6 @@ sub generate_proc
        0x00060302031D0000 + $nodeSize*$lognode + $chipSize*$logid );
     printf( "    </attribute>\n" );
 
-    #XSCOM address
-    printf( "    <attribute><id>XSCOM_BASE_ADDRESS</id>\n" );
-    printf( "        <default>0x%016X</default>\n",
-       0x000603FC00000000 + $nodeSize*$lognode + $chipSize*$logid );
-    printf( "    </attribute>\n" );
-
     print "    <!-- End PHYP Memory Map -->\n\n";
     # end PHYP Memory Map
 
diff --git a/src/usr/targeting/common/processMrw.pl b/src/usr/targeting/common/processMrw.pl
index 56cfe4572..7cd36a09e 100644
--- a/src/usr/targeting/common/processMrw.pl
+++ b/src/usr/targeting/common/processMrw.pl
@@ -177,10 +177,13 @@ sub processSystem
         $targetObj->{NUM_PROCS_PER_NODE});
     parseBitwise($targetObj,$target,"CDM_POLICIES");
 
-    my ($num,$base,$group_offset,$proc_offset,$offset) = split(/,/,
-         $targetObj->getAttribute($target,"XSCOM_BASE_ADDRESS"));
-
-    $targetObj->setAttribute($target, "XSCOM_BASE_ADDRESS", $base);
+    #@fixme-RTC:174616-Remove deprecated support
+    if (!$targetObj->isBadAttribute($target,"XSCOM_BASE_ADDRESS") )
+    {
+        my ($num,$base,$group_offset,$proc_offset,$offset) = split(/,/,
+            $targetObj->getAttribute($target,"XSCOM_BASE_ADDRESS"));
+        $targetObj->setAttribute($target, "XSCOM_BASE_ADDRESS", $base);
+    }
 
     # TODO RTC:170860 - Remove this after dimm connector defines VDDR_ID
     my $system_name = $targetObj->getAttribute($target,"SYSTEM_NAME");
@@ -751,14 +754,12 @@ sub setupBars
                 "INTP_BASE_ADDR",
                 "VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR",
                 "VAS_USER_WINDOW_CONTEXT_ADDR",
-                "LPC_BUS_ADDR",
                 "NVIDIA_NPU_PRIVILEGED_ADDR",
                 "NVIDIA_NPU_USER_REG_ADDR",
                 "NVIDIA_PHY0_REG_ADDR",
                 "NVIDIA_PHY1_REG_ADDR",
                 "PSI_HB_ESB_ADDR",
                 "XIVE_CONTROLLER_BAR_ADDR",
-                "XSCOM_BASE_ADDRESS",
                 "NX_RNG_ADDR");
 
     # Attribute only valid in naples-based systems
@@ -766,6 +767,14 @@ sub setupBars
           push(@bars,"NPU_MMIO_BAR_BASE_ADDR");
     }
 
+    #@fixme-RTC:174616-Remove deprecated support
+    if (!$targetObj->isBadAttribute($target,"LPC_BUS_ADDR") ) {
+          push(@bars,"LPC_BUS_ADDR");
+    }
+    if (!$targetObj->isBadAttribute($target,"XSCOM_BASE_ADDRESS") ) {
+          push(@bars,"XSCOM_BASE_ADDRESS");
+    }
+
     foreach my $bar (@bars)
     {
         my ($num,$base,$group_offset,$proc_offset,$offset) = split(/,/,
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 8d8b743d0..2acf9856c 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -3390,13 +3390,14 @@
 
 <attribute>
     <id>XSCOM_BASE_ADDRESS</id>
-    <description>System XSCOM base address</description>
+    <description>XSCOM base address</description>
     <simpleType>
         <uint64_t>
         </uint64_t>
     </simpleType>
-    <persistency>non-volatile</persistency>
+    <persistency>volatile</persistency>
     <readable/>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -18893,12 +18894,13 @@ Measured in GB</description>
 
 <attribute>
     <id>LPC_BUS_ADDR</id>
-    <description>LPC Bus address - MMIO consumed by PHYP</description>
+    <description>LPC Bus address</description>
     <simpleType>
         <uint64_t></uint64_t>
     </simpleType>
-    <persistency>non-volatile</persistency>
+    <persistency>volatile</persistency>
     <readable/>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -21791,21 +21793,6 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
-  <id>ADU_XSCOM_BAR_BASE_ADDR</id>
-  <description>Defines XSCOM base address on each processor level.
-        address provided by the MRW </description>
-  <simpleType>
-      <uint64_t></uint64_t>
-  </simpleType>
-  <hwpfToHbAttrMap>
-    <id>ATTR_ADU_XSCOM_BAR_BASE_ADDR</id>
-    <macro>DIRECT</macro>
-  </hwpfToHbAttrMap>
-  <persistency>volatile-zeroed</persistency>
-  <readable/>
-</attribute>
-
-<attribute>
     <id>PARENT_PERVASIVE</id>
     <description>
         Physical entity path of the target's associated pervasive target
@@ -30238,23 +30225,6 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
-  <id>LPC_BASE_ADDR</id>
-  <description>
-    Defines LPC base address on each processor level.
-  </description>
-  <simpleType>
-    <uint64_t>
-    </uint64_t>
-  </simpleType>
-  <persistency>non-volatile</persistency>
-  <readable/>
-  <hwpfToHbAttrMap>
-      <id>ATTR_LPC_BASE_ADDR</id>
-      <macro>DIRECT</macro>
-  </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
   <id>PROC_FSP_BAR_ENABLE</id>
   <description>
       FSP BAR enable
@@ -30781,6 +30751,7 @@ Measured in GB</description>
       <id>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</id>
       <macro>DIRECT</macro>
   </hwpfToHbAttrMap>
+  <writeable/>
 </attribute>
 
 
diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
index ca63e2b18..485881f1f 100644
--- a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
@@ -44,7 +44,7 @@
      * Each Nimbus has 2 OBUS (OB0 and OB3)
      *     Each OBUS has 3 OBUS_BRICK
      * Each Nimbus has 21 PPE units (including the SBE):
-     *    1 SBE, 1 Powerbus/Fabric PPE, 4 GPEs, 12 CMEs, and 3 IO PPEs.     *
+     *    1 SBE, 1 Powerbus/Fabric PPE, 4 GPEs, 12 CMEs, and 3 IO PPEs.
      * Each chiplet existing in a Nimbus has 1 equivalent PERV unit
      * Each Nimbus has 2 CAPP units
      * Each Nimbus has 1 SBE unit
@@ -119,10 +119,15 @@
         <id>PAYLOAD_KIND</id>
         <default>NONE</default>
     </attribute>
-        <attribute><id>XSCOM_BASE_ADDRESS</id>
+    <attribute>
+        <id>XSCOM_BASE_ADDRESS</id>
         <default>0x000603FC00000000</default>
     </attribute>
     <attribute>
+        <id>LPC_BUS_ADDR</id>
+        <default>0x0006030000000000</default>
+    </attribute>
+    <attribute>
         <id>TPM_REQUIRED</id>
         <default>1</default>
     </attribute>
@@ -450,9 +455,6 @@
         <id>PROC_MASTER_TYPE</id>
         <default>ACTING_MASTER</default>
     </attribute>
-    <attribute><id>XSCOM_BASE_ADDRESS</id>
-        <default>0x000603FC00000000</default>
-    </attribute>
     <attribute>
         <id>I2C_BUS_SPEED_ARRAY</id>
         <default>
@@ -5592,9 +5594,6 @@
     <attribute><id>VAS_USER_WINDOW_CONTEXT_ADDR</id>
         <default>0x0006053100000000</default>
     </attribute>
-    <attribute><id>LPC_BUS_ADDR</id>
-        <default>0x0006070000000000</default>
-    </attribute>
     <attribute><id>NVIDIA_NPU_PRIVILEGED_ADDR</id>
         <default>0x0006070200000000</default>
     </attribute>
@@ -5619,9 +5618,6 @@
     <attribute><id>NX_RNG_ADDR</id>
         <default>0x00060702031D0000</default>
     </attribute>
-    <attribute><id>XSCOM_BASE_ADDRESS</id>
-        <default>0x000607FC00000000</default>
-    </attribute>
     <!-- End PHYP Memory Map -->
 
     <!-- PM_ attributes -->
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 3bdf8f1af..1c02faadb 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -311,7 +311,6 @@
     <attribute><id>TLB_RESERVE_SIZE</id></attribute>
     <attribute><id>TIME_BASE</id></attribute>
     <attribute><id>CPU_ATTR</id></attribute>
-    <attribute><id>ADU_XSCOM_BAR_BASE_ADDR</id></attribute>
     <attribute><id>PROC_OCC_SANDBOX_SIZE</id></attribute>
     <attribute><id>PROC_FABRIC_SYSTEM_MASTER_CHIP</id></attribute>
     <attribute><id>PROC_FABRIC_GROUP_MASTER_CHIP</id></attribute>
@@ -592,7 +591,7 @@
         <id>AFFINITY_PATH</id>
         <default>affinity:sys-0</default>
     </attribute>
-    <attribute><id>XSCOM_BASE_ADDRESS</id></attribute>
+    <attribute><id>XSCOM_BASE_ADDRESS</id><default>0x000603FC00000000</default></attribute>
     <attribute>
         <id>IS_SIMULATION</id>
         <default>0</default>
@@ -799,6 +798,7 @@
     <attribute><id>MSS_MRW_RESET_DELAY_BEFORE_CAL</id></attribute>
     <attribute><id>MSS_MRW_DRAM_2N_MODE</id></attribute>
     <attribute><id>MRW_HW_MIRRORING_ENABLE</id></attribute>
+    <attribute><id>LPC_BUS_ADDR</id><default>0x0006030000000000</default></attribute>
 
     <!-- attributes for sbe_start -->
     <attribute><id>SBE_UPDATE_DISABLE</id></attribute>
@@ -1066,6 +1066,7 @@
     <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute>
     <attribute><id>PROC_DCM_INSTALLED</id></attribute>
     <attribute><id>XSCOM_BASE_ADDRESS</id></attribute>
+    <attribute><id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id></attribute>
     <attribute><id>PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id></attribute>
     <attribute><id>STOPGPE_BOOT_COPIER_IVPR_OFFSET</id></attribute>
     <attribute><id>EQ_GARD</id></attribute>
@@ -1259,7 +1260,6 @@
         <default>8</default>
     </attribute>
     <!-- End processor characteristics for HDAT -->
-    <attribute><id>LPC_BASE_ADDR</id></attribute>
     <attribute><id>BOOT_FREQ_MHZ</id></attribute>
 
 <!-- p9_setup_bars - Begin -->
diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C
index 969a2a7ab..1faae4cee 100755
--- a/src/usr/targeting/targetservicestart.C
+++ b/src/usr/targeting/targetservicestart.C
@@ -58,6 +58,10 @@
 #include <config.h>
 #include <initservice/initserviceif.H>
 #include <util/misc.H>
+#include <kernel/bltohbdatamgr.H>
+#include <map>
+#include <arch/memorymap.H>
+#include <lpc/lpcif.H>
 
 #ifdef CONFIG_DRTM
 #include <secureboot/drtm.H>
@@ -95,6 +99,12 @@ static void initializeAttributes(TargetService& i_targetService,
 static void checkProcessorTargeting(TargetService& i_targetService);
 
 /**
+ *  @brief Compute any values that might change based on a remap of memory
+ *  @param[in]  Pointer to targeting service
+ */
+static void adjustMemoryMap(TargetService& i_targetService);
+
+/**
  *  @brief Entry point for initialization service to initialize the targeting
  *      code
  *
@@ -381,6 +391,9 @@ static void initializeAttributes(TargetService& i_targetService,
         else
         {
             l_pTopLevel->setAttr<ATTR_IS_MPIPL_HB>(0);
+
+            // Compute any values that might change based on a remap of memory
+            adjustMemoryMap(i_targetService);
         }
     }
     else // top level is NULL - never expected
@@ -392,6 +405,135 @@ static void initializeAttributes(TargetService& i_targetService,
     #undef TARG_FN
 }
 
+/**
+ *  @brief Utility macro to swap attributes
+ *  @param[in]  _attr    Attribute ID
+ *  @param[in]  _master  Master proc target
+ *  @param[in]  _victim  Victim proc target
+ *  @param[in]  _cache   Cache of victime attributes
+ */
+#define SWAP_ATTRIBUTE( _attr, _master, _victim, _cache ) \
+{ \
+    _attr##_type l_masterVal = _master->getAttr<_attr>(); \
+    _victim->setAttr<_attr>(l_masterVal); \
+    TARG_INF( "%.8X>" #_attr "=%.16llX", get_huid(_victim), l_masterVal ); \
+    _master->setAttr<_attr>(_cache[_attr]); \
+    TARG_INF( "%.8X>" #_attr "=%.16llX", get_huid(_master), _cache[_attr] ); \
+}
+
+// Compute any values that might change based on a remap of memory
+static void adjustMemoryMap( TargetService& i_targetService )
+{
+    // Grab the value of the BARs that SBE booted with
+    uint64_t l_curXscomBAR = g_BlToHbDataManager.getXscomBAR();
+    uint64_t l_curLpcBAR = g_BlToHbDataManager.getLpcBAR();
+    TARG_INF( "adjustMemoryMap> xscom=%X, lpc=%X", l_curXscomBAR, l_curLpcBAR );
+
+    // Get the master proc
+    Target* l_pMasterProcChip = nullptr;
+    i_targetService.masterProcChipTargetHandle(l_pMasterProcChip);
+    assert(l_pMasterProcChip,"No Master Proc");
+
+    // Save off the base (group0-chip0) value for the BARs
+    Target* l_pTopLevel = nullptr;
+    i_targetService.getTopLevelTarget(l_pTopLevel);
+    ATTR_XSCOM_BASE_ADDRESS_type l_xscomBase =
+      l_pTopLevel->getAttr<ATTR_XSCOM_BASE_ADDRESS>();
+    ATTR_LPC_BUS_ADDR_type l_lpcBase =
+      l_pTopLevel->getAttr<ATTR_LPC_BUS_ADDR>();
+
+    // Loop through all the procs to recompute all the BARs
+    //  also find the victim to swap with
+    Target* l_swapVictim = nullptr;
+    std::map<ATTRIBUTE_ID,uint64_t> l_swapAttrs;
+
+    TARGETING::TargetHandleList l_funcProcs;
+    getAllChips(l_funcProcs, TYPE_PROC, false );
+    for( auto & l_procChip : l_funcProcs )
+    {
+        TARG_INF( "Proc=%.8X", get_huid(l_procChip) );
+        // Set effective fabric ids back to default values
+        ATTR_FABRIC_GROUP_ID_type l_groupId =
+          l_procChip->getAttr<ATTR_FABRIC_GROUP_ID>();
+        l_procChip->setAttr<ATTR_PROC_EFF_FABRIC_GROUP_ID>(l_groupId);
+
+        ATTR_FABRIC_CHIP_ID_type l_chipId =
+          l_procChip->getAttr<ATTR_FABRIC_CHIP_ID>();
+        l_procChip->setAttr<ATTR_PROC_EFF_FABRIC_CHIP_ID>(l_chipId);
+
+        // Compute default xscom BAR
+        ATTR_XSCOM_BASE_ADDRESS_type l_xscomBAR =
+          computeMemoryMapOffset( l_xscomBase, l_groupId, l_chipId );
+        TARG_INF( " XSCOM=%.16llX", l_xscomBAR );
+        l_procChip->setAttr<ATTR_XSCOM_BASE_ADDRESS>(l_xscomBAR);
+
+        // See if this chip's space now belongs to the master
+        if( l_xscomBAR == l_curXscomBAR )
+        {
+            l_swapVictim = l_procChip;
+            TARG_INF( "Master Proc %.8X is using XSCOM BAR from %.8X, BAR=%.16llX", get_huid(l_pMasterProcChip), get_huid(l_swapVictim), l_curXscomBAR );
+            l_swapAttrs[ATTR_PROC_EFF_FABRIC_GROUP_ID] = l_groupId;
+            l_swapAttrs[ATTR_PROC_EFF_FABRIC_CHIP_ID] = l_chipId;
+            l_swapAttrs[ATTR_XSCOM_BASE_ADDRESS] = l_xscomBAR;
+        }
+
+        // Compute default LPC BAR
+        ATTR_LPC_BUS_ADDR_type l_lpcBAR =
+          computeMemoryMapOffset( l_lpcBase, l_groupId, l_chipId );
+        TARG_INF( " LPC=%.16llX", l_lpcBAR );
+        l_procChip->setAttr<ATTR_LPC_BUS_ADDR>(l_lpcBAR);
+        if( l_swapVictim == l_procChip )
+        {
+            l_swapAttrs[ATTR_LPC_BUS_ADDR] = l_lpcBAR;
+        }
+
+        // Paranoid double-check that LPC matches XSCOM...
+        if( ((l_lpcBAR == l_curLpcBAR) && (l_swapVictim != l_procChip))
+            ||
+            ((l_lpcBAR != l_curLpcBAR) && (l_swapVictim == l_procChip)) )
+        {
+            TARG_ERR("BARs do not match : LPC=%.16llX, XSCOM=%.16llX",
+                     l_curLpcBAR, l_curXscomBAR );
+            TARG_ASSERT(false,"Mismatch between LPC and XSCOM BARs");
+        }
+
+        // Set the rest of the BARs...
+    }
+
+    // We must have found a match somewhere
+    TARG_ASSERT( l_swapVictim != nullptr, "No swap match found" );
+
+    // Now swap the BARs between the master and the victim if needed
+    if( l_swapVictim != l_pMasterProcChip )
+    {
+        // Walk through all of the attributes we cached above
+        SWAP_ATTRIBUTE( ATTR_PROC_EFF_FABRIC_GROUP_ID, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_PROC_EFF_FABRIC_CHIP_ID, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_XSCOM_BASE_ADDRESS, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        SWAP_ATTRIBUTE( ATTR_LPC_BUS_ADDR, l_pMasterProcChip,
+                        l_swapVictim, l_swapAttrs );
+        // Handle the rest of the BARs...
+    }
+
+
+    // Cross-check that what we ended up setting in the attributes
+    //  matches the non-TARGETING values that the XSCOM and LPC
+    //  drivers computed
+    if( l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>()
+        != LPC::get_lpc_bar() )
+    {
+        TARG_ERR( "LPC attribute=%.16llX, live=%.16llX",
+           l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>(),
+           LPC::get_lpc_bar() );
+        TARG_ASSERT( true, "LPC BARs are inconsistent" );
+    }
+    //@todo-RTC:173519-Add xscom cross-check
+}
+
+
 #undef TARG_CLASS
 
 #undef TARG_NAMESPACE
diff --git a/src/usr/xscom/xscom.H b/src/usr/xscom/xscom.H
index 9472f39d9..b1ceaab6a 100644
--- a/src/usr/xscom/xscom.H
+++ b/src/usr/xscom/xscom.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -31,6 +31,7 @@
 
 #include <stdint.h>
 #include <limits.h>
+#include <arch/memorymap.H>
 
 /**
  *  @brief  The (fixed) base address value for master proc
@@ -38,12 +39,6 @@
 constexpr uint64_t MASTER_PROC_XSCOM_BASE_ADDR = 0x000603FC00000000;
 
 /**
- *  @brief  Static offsets into other chips
- */
-constexpr uint64_t  MMIO_OFFSET_PER_CHIP  = (4*TERABYTE);
-constexpr uint64_t  MMIO_OFFSET_PER_GROUP = (32*TERABYTE);
-
-/**
  *  @brief  Type definition for XSCom address and Base
  */
 typedef uint32_t XSComAddress_t;