Minor SPD Parser fixes

Brent Wieman spotted some differences between the DDR3 parser output
after DDR4 support was added. Investigation led to these fixes. None
of these errors have any functional effect right now because the
fields in question are not currently used.

Change-Id: I93894eeb19d4bd748ed7ba6131bdd54fb201fa02
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5397
Tested-by: Jenkins Server
Reviewed-by: William H. Schwartz <whs@us.ibm.com>
Reviewed-by: Donald E. Dahle <dedahle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 36 insertions, 32 deletions

diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
index a5a38267d..89b876a30 100644
--- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
+++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
@@ -698,10 +698,10 @@ fapi::ReturnCode fapiPlatGetSlopeInterceptData (
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_MIRRORING, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_LR_F0RC3_F0RC2_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC3_FORC2, &(VAL), sizeof(VAL) )
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC3_F0RC2, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_LR_F0RC5_F0RC4_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC5_FORC4, &(VAL), sizeof(VAL) )
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC5_F0RC4, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_LR_F1RC11_F1RC8_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F1RC11_F1RC8, &(VAL), sizeof(VAL) )
@@ -819,6 +819,9 @@ fapi::ReturnCode fapiPlatGetSlopeInterceptData (
 #define ATTR_SPD_CRC_BASE_CONFIG_DDR4_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::BASE_CONFIG_CRC, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_MODULE_REVISION_CODE_DDR4_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_REVISION_CODE_DDR4, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_DRAM_STEPPING_DDR4_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::DRAM_STEPPING, &(VAL), sizeof(VAL) )
diff --git a/src/include/usr/vpd/spdenums.H b/src/include/usr/vpd/spdenums.H
index 49860ffd4..926b50a51 100644
--- a/src/include/usr/vpd/spdenums.H
+++ b/src/include/usr/vpd/spdenums.H
@@ -87,34 +87,34 @@ enum
     MODULE_MANUFACTURING_DATE        = SPD_FIRST_NORM_KEYWORD | 0x27,
     MODULE_SERIAL_NUMBER             = SPD_FIRST_NORM_KEYWORD | 0x28,
     MODULE_PART_NUMBER               = SPD_FIRST_NORM_KEYWORD | 0x29,
-    MODULE_REVISION_CODE             = SPD_FIRST_NORM_KEYWORD | 0x2a,
-    DRAM_MANUFACTURER_ID             = SPD_FIRST_NORM_KEYWORD | 0x2b,
-    MANUFACTURER_SPECIFIC_DATA       = SPD_FIRST_NORM_KEYWORD | 0x2c,
-    DIMM_BAD_DQ_DATA                 = SPD_FIRST_NORM_KEYWORD | 0x2d,
+    DRAM_MANUFACTURER_ID             = SPD_FIRST_NORM_KEYWORD | 0x2a,
+    MANUFACTURER_SPECIFIC_DATA       = SPD_FIRST_NORM_KEYWORD | 0x2b,
+    DIMM_BAD_DQ_DATA                 = SPD_FIRST_NORM_KEYWORD | 0x2c,
 
     // ==============================================================
     // Normal SPD Keywords (Available for DDR3 DIMMs only)
-    BANK_ADDRESS_BITS                = SPD_FIRST_NORM_KEYWORD | 0x2e,
-    MODULE_NOMINAL_VOLTAGE           = SPD_FIRST_NORM_KEYWORD | 0x2f,
-    FTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x30,
-    FTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x31,
-    MTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x32,
-    MTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x33,
-    CAS_LATENCIES_SUPPORTED          = SPD_FIRST_NORM_KEYWORD | 0x34,
-    TWR_MIN                          = SPD_FIRST_NORM_KEYWORD | 0x35,
-    TRRD_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x36,
-    TRFC_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x37,
-    TWTR_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x38,
-    TRTP_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x39,
-    DLL_OFF                          = SPD_FIRST_NORM_KEYWORD | 0x3a,
-    RZQ_7                            = SPD_FIRST_NORM_KEYWORD | 0x3b,
-    RZQ_6                            = SPD_FIRST_NORM_KEYWORD | 0x3c,
-    PASR                             = SPD_FIRST_NORM_KEYWORD | 0x3d,
-    ODTS                             = SPD_FIRST_NORM_KEYWORD | 0x3e,
-    ASR                              = SPD_FIRST_NORM_KEYWORD | 0x3f,
-    ETR_1X                           = SPD_FIRST_NORM_KEYWORD | 0x40,
-    ETR                              = SPD_FIRST_NORM_KEYWORD | 0x41,
-    MODULE_CRC                       = SPD_FIRST_NORM_KEYWORD | 0x42,
+    BANK_ADDRESS_BITS                = SPD_FIRST_NORM_KEYWORD | 0x2d,
+    MODULE_NOMINAL_VOLTAGE           = SPD_FIRST_NORM_KEYWORD | 0x2e,
+    FTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x2f,
+    FTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x30,
+    MTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x31,
+    MTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x32,
+    CAS_LATENCIES_SUPPORTED          = SPD_FIRST_NORM_KEYWORD | 0x33,
+    TWR_MIN                          = SPD_FIRST_NORM_KEYWORD | 0x34,
+    TRRD_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x35,
+    TRFC_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x36,
+    TWTR_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x37,
+    TRTP_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x38,
+    DLL_OFF                          = SPD_FIRST_NORM_KEYWORD | 0x39,
+    RZQ_7                            = SPD_FIRST_NORM_KEYWORD | 0x3a,
+    RZQ_6                            = SPD_FIRST_NORM_KEYWORD | 0x3b,
+    PASR                             = SPD_FIRST_NORM_KEYWORD | 0x3c,
+    ODTS                             = SPD_FIRST_NORM_KEYWORD | 0x3d,
+    ASR                              = SPD_FIRST_NORM_KEYWORD | 0x3e,
+    ETR_1X                           = SPD_FIRST_NORM_KEYWORD | 0x3f,
+    ETR                              = SPD_FIRST_NORM_KEYWORD | 0x40,
+    MODULE_CRC                       = SPD_FIRST_NORM_KEYWORD | 0x41,
+    MODULE_REVISION_CODE             = SPD_FIRST_NORM_KEYWORD | 0x42,
 
     // ==============================================================
     // Normal SPD Keywords (Available for DDR4 DIMMs only)
@@ -137,9 +137,10 @@ enum
     TRRDS_FINE_OFFSET                = SPD_FIRST_NORM_KEYWORD | 0x53,
     TCKMAX_FINE_OFFSET               = SPD_FIRST_NORM_KEYWORD | 0x54,
     BASE_CONFIG_CRC                  = SPD_FIRST_NORM_KEYWORD | 0x55,
-    DRAM_STEPPING                    = SPD_FIRST_NORM_KEYWORD | 0x56,
-    MANUFACTURING_SECTION_CRC        = SPD_FIRST_NORM_KEYWORD | 0x57,
-    SPD_LAST_NORM_KEYWORD            = SPD_FIRST_NORM_KEYWORD | 0x57,
+    MODULE_REVISION_CODE_DDR4        = SPD_FIRST_NORM_KEYWORD | 0x56,
+    DRAM_STEPPING                    = SPD_FIRST_NORM_KEYWORD | 0x57,
+    MANUFACTURING_SECTION_CRC        = SPD_FIRST_NORM_KEYWORD | 0x58,
+    SPD_LAST_NORM_KEYWORD            = SPD_FIRST_NORM_KEYWORD | 0x58,
 
     // ==============================================================
     // Module Specific Keywords (Available for both DDR3 and DDR4 DIMMs)
@@ -183,10 +184,10 @@ enum
     RMM_RC14                         = SPD_FIRST_MOD_SPEC | 0x22,
     LRMM_RANK_NUMBERING              = SPD_FIRST_MOD_SPEC | 0x23,
     LRMM_MEMBUF_ORIEN                = SPD_FIRST_MOD_SPEC | 0x24,
-    LRMM_F0RC3_FORC2                 = SPD_FIRST_MOD_SPEC | 0x25,
+    LRMM_F0RC3_F0RC2                 = SPD_FIRST_MOD_SPEC | 0x25,
     LRMM_F0RC3                       = SPD_FIRST_MOD_SPEC | 0x26,
     LRMM_F0RC2                       = SPD_FIRST_MOD_SPEC | 0x27,
-    LRMM_F0RC5_FORC4                 = SPD_FIRST_MOD_SPEC | 0x28,
+    LRMM_F0RC5_F0RC4                 = SPD_FIRST_MOD_SPEC | 0x28,
     LRMM_F0RC5                       = SPD_FIRST_MOD_SPEC | 0x29,
     LRMM_F0RC4                       = SPD_FIRST_MOD_SPEC | 0x2a,
     LRMM_F1RC11_F1RC8                = SPD_FIRST_MOD_SPEC | 0x2b,