Minor SPD Parser fixes

Brent Wieman spotted some differences between the DDR3 parser output
after DDR4 support was added. Investigation led to these fixes. None
of these errors have any functional effect right now because the
fields in question are not currently used.

Change-Id: I93894eeb19d4bd748ed7ba6131bdd54fb201fa02
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5397
Tested-by: Jenkins Server
Reviewed-by: William H. Schwartz <whs@us.ibm.com>
Reviewed-by: Donald E. Dahle <dedahle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 66 insertions, 53 deletions

diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
index a5a38267d..89b876a30 100644
--- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
+++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
@@ -698,10 +698,10 @@ fapi::ReturnCode fapiPlatGetSlopeInterceptData (
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_MIRRORING, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_LR_F0RC3_F0RC2_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC3_FORC2, &(VAL), sizeof(VAL) )
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC3_F0RC2, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_LR_F0RC5_F0RC4_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC5_FORC4, &(VAL), sizeof(VAL) )
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F0RC5_F0RC4, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_LR_F1RC11_F1RC8_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::LRMM_F1RC11_F1RC8, &(VAL), sizeof(VAL) )
@@ -819,6 +819,9 @@ fapi::ReturnCode fapiPlatGetSlopeInterceptData (
 #define ATTR_SPD_CRC_BASE_CONFIG_DDR4_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::BASE_CONFIG_CRC, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_MODULE_REVISION_CODE_DDR4_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_REVISION_CODE_DDR4, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_DRAM_STEPPING_DDR4_GETMACRO(ID, PTARGET, VAL) \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::DRAM_STEPPING, &(VAL), sizeof(VAL) )
diff --git a/src/include/usr/vpd/spdenums.H b/src/include/usr/vpd/spdenums.H
index 49860ffd4..926b50a51 100644
--- a/src/include/usr/vpd/spdenums.H
+++ b/src/include/usr/vpd/spdenums.H
@@ -87,34 +87,34 @@ enum
     MODULE_MANUFACTURING_DATE        = SPD_FIRST_NORM_KEYWORD | 0x27,
     MODULE_SERIAL_NUMBER             = SPD_FIRST_NORM_KEYWORD | 0x28,
     MODULE_PART_NUMBER               = SPD_FIRST_NORM_KEYWORD | 0x29,
-    MODULE_REVISION_CODE             = SPD_FIRST_NORM_KEYWORD | 0x2a,
-    DRAM_MANUFACTURER_ID             = SPD_FIRST_NORM_KEYWORD | 0x2b,
-    MANUFACTURER_SPECIFIC_DATA       = SPD_FIRST_NORM_KEYWORD | 0x2c,
-    DIMM_BAD_DQ_DATA                 = SPD_FIRST_NORM_KEYWORD | 0x2d,
+    DRAM_MANUFACTURER_ID             = SPD_FIRST_NORM_KEYWORD | 0x2a,
+    MANUFACTURER_SPECIFIC_DATA       = SPD_FIRST_NORM_KEYWORD | 0x2b,
+    DIMM_BAD_DQ_DATA                 = SPD_FIRST_NORM_KEYWORD | 0x2c,
 
     // ==============================================================
     // Normal SPD Keywords (Available for DDR3 DIMMs only)
-    BANK_ADDRESS_BITS                = SPD_FIRST_NORM_KEYWORD | 0x2e,
-    MODULE_NOMINAL_VOLTAGE           = SPD_FIRST_NORM_KEYWORD | 0x2f,
-    FTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x30,
-    FTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x31,
-    MTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x32,
-    MTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x33,
-    CAS_LATENCIES_SUPPORTED          = SPD_FIRST_NORM_KEYWORD | 0x34,
-    TWR_MIN                          = SPD_FIRST_NORM_KEYWORD | 0x35,
-    TRRD_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x36,
-    TRFC_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x37,
-    TWTR_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x38,
-    TRTP_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x39,
-    DLL_OFF                          = SPD_FIRST_NORM_KEYWORD | 0x3a,
-    RZQ_7                            = SPD_FIRST_NORM_KEYWORD | 0x3b,
-    RZQ_6                            = SPD_FIRST_NORM_KEYWORD | 0x3c,
-    PASR                             = SPD_FIRST_NORM_KEYWORD | 0x3d,
-    ODTS                             = SPD_FIRST_NORM_KEYWORD | 0x3e,
-    ASR                              = SPD_FIRST_NORM_KEYWORD | 0x3f,
-    ETR_1X                           = SPD_FIRST_NORM_KEYWORD | 0x40,
-    ETR                              = SPD_FIRST_NORM_KEYWORD | 0x41,
-    MODULE_CRC                       = SPD_FIRST_NORM_KEYWORD | 0x42,
+    BANK_ADDRESS_BITS                = SPD_FIRST_NORM_KEYWORD | 0x2d,
+    MODULE_NOMINAL_VOLTAGE           = SPD_FIRST_NORM_KEYWORD | 0x2e,
+    FTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x2f,
+    FTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x30,
+    MTB_DIVIDEND                     = SPD_FIRST_NORM_KEYWORD | 0x31,
+    MTB_DIVISOR                      = SPD_FIRST_NORM_KEYWORD | 0x32,
+    CAS_LATENCIES_SUPPORTED          = SPD_FIRST_NORM_KEYWORD | 0x33,
+    TWR_MIN                          = SPD_FIRST_NORM_KEYWORD | 0x34,
+    TRRD_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x35,
+    TRFC_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x36,
+    TWTR_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x37,
+    TRTP_MIN                         = SPD_FIRST_NORM_KEYWORD | 0x38,
+    DLL_OFF                          = SPD_FIRST_NORM_KEYWORD | 0x39,
+    RZQ_7                            = SPD_FIRST_NORM_KEYWORD | 0x3a,
+    RZQ_6                            = SPD_FIRST_NORM_KEYWORD | 0x3b,
+    PASR                             = SPD_FIRST_NORM_KEYWORD | 0x3c,
+    ODTS                             = SPD_FIRST_NORM_KEYWORD | 0x3d,
+    ASR                              = SPD_FIRST_NORM_KEYWORD | 0x3e,
+    ETR_1X                           = SPD_FIRST_NORM_KEYWORD | 0x3f,
+    ETR                              = SPD_FIRST_NORM_KEYWORD | 0x40,
+    MODULE_CRC                       = SPD_FIRST_NORM_KEYWORD | 0x41,
+    MODULE_REVISION_CODE             = SPD_FIRST_NORM_KEYWORD | 0x42,
 
     // ==============================================================
     // Normal SPD Keywords (Available for DDR4 DIMMs only)
@@ -137,9 +137,10 @@ enum
     TRRDS_FINE_OFFSET                = SPD_FIRST_NORM_KEYWORD | 0x53,
     TCKMAX_FINE_OFFSET               = SPD_FIRST_NORM_KEYWORD | 0x54,
     BASE_CONFIG_CRC                  = SPD_FIRST_NORM_KEYWORD | 0x55,
-    DRAM_STEPPING                    = SPD_FIRST_NORM_KEYWORD | 0x56,
-    MANUFACTURING_SECTION_CRC        = SPD_FIRST_NORM_KEYWORD | 0x57,
-    SPD_LAST_NORM_KEYWORD            = SPD_FIRST_NORM_KEYWORD | 0x57,
+    MODULE_REVISION_CODE_DDR4        = SPD_FIRST_NORM_KEYWORD | 0x56,
+    DRAM_STEPPING                    = SPD_FIRST_NORM_KEYWORD | 0x57,
+    MANUFACTURING_SECTION_CRC        = SPD_FIRST_NORM_KEYWORD | 0x58,
+    SPD_LAST_NORM_KEYWORD            = SPD_FIRST_NORM_KEYWORD | 0x58,
 
     // ==============================================================
     // Module Specific Keywords (Available for both DDR3 and DDR4 DIMMs)
@@ -183,10 +184,10 @@ enum
     RMM_RC14                         = SPD_FIRST_MOD_SPEC | 0x22,
     LRMM_RANK_NUMBERING              = SPD_FIRST_MOD_SPEC | 0x23,
     LRMM_MEMBUF_ORIEN                = SPD_FIRST_MOD_SPEC | 0x24,
-    LRMM_F0RC3_FORC2                 = SPD_FIRST_MOD_SPEC | 0x25,
+    LRMM_F0RC3_F0RC2                 = SPD_FIRST_MOD_SPEC | 0x25,
     LRMM_F0RC3                       = SPD_FIRST_MOD_SPEC | 0x26,
     LRMM_F0RC2                       = SPD_FIRST_MOD_SPEC | 0x27,
-    LRMM_F0RC5_FORC4                 = SPD_FIRST_MOD_SPEC | 0x28,
+    LRMM_F0RC5_F0RC4                 = SPD_FIRST_MOD_SPEC | 0x28,
     LRMM_F0RC5                       = SPD_FIRST_MOD_SPEC | 0x29,
     LRMM_F0RC4                       = SPD_FIRST_MOD_SPEC | 0x2a,
     LRMM_F1RC11_F1RC8                = SPD_FIRST_MOD_SPEC | 0x2b,
diff --git a/src/usr/hwpf/hwp/dimm_spd_attributes.xml b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
index 3b7f8aa52..12eea1672 100644
--- a/src/usr/hwpf/hwp/dimm_spd_attributes.xml
+++ b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
@@ -20,7 +20,7 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-  <!-- $Id: dimm_spd_attributes.xml,v 1.21 2013/06/14 18:51:49 mjjones Exp $ -->
+<!-- $Id: dimm_spd_attributes.xml,v 1.23 2013/07/14 01:35:41 mjjones Exp $ -->
 <!-- XML file specifying DIMM SPD attributes used by HW Procedures. -->
 <attributes>
 
@@ -470,18 +470,6 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
 </attribute>
 
 <attribute>
-    <id>ATTR_SPD_MODULE_REVISION_CODE</id>
-    <targetType>TARGET_TYPE_DIMM</targetType>
-    <description>
-        Module Revision Code.
-        Located in DDR3 SPD bytes 146 (LSB) to 147.
-        Located in DDR4 SPD bytes 349 
-    </description>
-    <valueType>uint32</valueType>
-    <platInit/>
-</attribute>
-
-<attribute>
     <id>ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -665,6 +653,17 @@ Querying them from DDR4 DIMMs will result in an error
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR3 SPD bytes 146 (LSB) to 147.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_LR_ADDR_MIRRORING</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -1212,6 +1211,17 @@ Querying them from DDR3 DIMMs will result in an error
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR4 SPD byte 349
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_DRAM_STEPPING_DDR4</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
diff --git a/src/usr/vpd/spd.C b/src/usr/vpd/spd.C
index a102ed7bd..3db5af0f5 100755
--- a/src/usr/vpd/spd.C
+++ b/src/usr/vpd/spd.C
@@ -822,7 +822,7 @@ errlHndl_t ddr3SpecialCases(const KeywordData & i_kwdData,
             break;
     };
     
-    TRACSSCOMP( g_trac_spd, EXIT_MRK"ddr4SpecialCases()" );
+    TRACSSCOMP( g_trac_spd, EXIT_MRK"ddr3SpecialCases()" );
     return err;
 }
 
@@ -847,7 +847,6 @@ errlHndl_t ddr4SpecialCases(const KeywordData & i_kwdData,
         case TRFC4_MIN:
         case BASE_CONFIG_CRC:
         case MODULE_MANUFACTURER_ID:
-        case MODULE_REVISION_CODE:
         case DRAM_MANUFACTURER_ID:
         case MANUFACTURING_SECTION_CRC:
         case UMM_CRC:
diff --git a/src/usr/vpd/spdDDR3.H b/src/usr/vpd/spdDDR3.H
index e7c701ca8..a8919109a 100644
--- a/src/usr/vpd/spdDDR3.H
+++ b/src/usr/vpd/spdDDR3.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2013              */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -108,7 +108,6 @@ const KeywordData ddr3Data[] =
     { MODULE_MANUFACTURING_DATE,        0x78,   0x02,   0x00,   0x00, false, false, NA },
     { MODULE_SERIAL_NUMBER,             0x7a,   0x04,   0x00,   0x00, false, false, NA },
     { MODULE_PART_NUMBER,               0x80,   0x12,   0x00,   0x00, false, false, NA },
-    { MODULE_REVISION_CODE,             0x92,   0x02,   0x00,   0x00, true,  false, NA },
     { DRAM_MANUFACTURER_ID,             0x95,   0x02,   0x00,   0x00, true,  false, NA },
     { MANUFACTURER_SPECIFIC_DATA,       0x96,   0x1a,   0x00,   0x00, false, false, NA },
     { DIMM_BAD_DQ_DATA,                 0xb0,   0x50,   0x00,   0x00, false, true,  NA },
@@ -133,7 +132,8 @@ const KeywordData ddr3Data[] =
     { ASR,                              0x1f,   0x01,   0x04,   0x02, false, false, NA },
     { ETR_1X,                           0x1f,   0x01,   0x02,   0x01, false, false, NA },
     { ETR,                              0x1f,   0x01,   0x01,   0x00, false, false, NA },
-    { MODULE_CRC,                       0x7e,   0x02,   0x00,   0x00, true, false, NA },
+    { MODULE_CRC,                       0x7f,   0x02,   0x00,   0x00, true,  false, NA },
+    { MODULE_REVISION_CODE,             0x93,   0x02,   0x00,   0x00, true,  false, NA },
     // Module Specific fields supported on both DDR3 and DDR4
     { MODSPEC_COM_NOM_HEIGHT_MAX,       0x3c,   0x01,   0x1f,   0x00, false, false, ALL },
     { MODSPEC_COM_MAX_THICK_BACK,       0x3d,   0x01,   0xf0,   0x04, false, false, ALL },
@@ -173,10 +173,10 @@ const KeywordData ddr3Data[] =
     { RMM_RC14,                         0x4c,   0x01,   0x0f,   0x00, false, false, RMM },
     { LRMM_RANK_NUMBERING,              0x3f,   0x01,   0x20,   0x05, false, false, LRMM },
     { LRMM_MEMBUF_ORIEN,                0x3f,   0x01,   0x10,   0x04, false, false, LRMM },
-    { LRMM_F0RC3_FORC2,                 0x43,   0x01,   0x00,   0x00, false, false, LRMM },
+    { LRMM_F0RC3_F0RC2,                 0x43,   0x01,   0x00,   0x00, false, false, LRMM },
     { LRMM_F0RC3,                       0x43,   0x01,   0xf0,   0x04, false, false, LRMM },
     { LRMM_F0RC2,                       0x43,   0x01,   0x0f,   0x00, false, false, LRMM },
-    { LRMM_F0RC5_FORC4,                 0x44,   0x01,   0x00,   0x00, false, false, LRMM },
+    { LRMM_F0RC5_F0RC4,                 0x44,   0x01,   0x00,   0x00, false, false, LRMM },
     { LRMM_F0RC5,                       0x44,   0x01,   0xf0,   0x04, false, false, LRMM },
     { LRMM_F0RC4,                       0x44,   0x01,   0x0f,   0x00, false, false, LRMM },
     { LRMM_F1RC11_F1RC8,                0x45,   0x01,   0x00,   0x00, false, false, LRMM },
diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H
index 7f165d85a..b4413efe9 100644
--- a/src/usr/vpd/spdDDR4.H
+++ b/src/usr/vpd/spdDDR4.H
@@ -108,7 +108,6 @@ const KeywordData ddr4Data[] =
     { MODULE_MANUFACTURING_DATE,        0x143,  0x02,   0x00,   0x00, false, false, NA },
     { MODULE_SERIAL_NUMBER,             0x145,  0x04,   0x00,   0x00, false, false, NA },
     { MODULE_PART_NUMBER,               0x149,  0x14,   0x00,   0x00, false, false, NA },
-    { MODULE_REVISION_CODE,             0x15d,  0x01,   0x00,   0x00, true,  false, NA },
     { DRAM_MANUFACTURER_ID,             0x15f,  0x02,   0x00,   0x00, true,  false, NA },
     { MANUFACTURER_SPECIFIC_DATA,       0x161,  0x1d,   0x00,   0x00, false, false, NA },
     { DIMM_BAD_DQ_DATA,                 0x180,  0x50,   0x00,   0x00, false, true,  NA },
@@ -132,6 +131,7 @@ const KeywordData ddr4Data[] =
     { TRRDS_FINE_OFFSET,                0x77,   0x01,   0x00,   0x00, false, false, NA },
     { TCKMAX_FINE_OFFSET,               0x7c,   0x01,   0x00,   0x00, false, false, NA },
     { BASE_CONFIG_CRC,                  0x7f,   0x02,   0x00,   0x00, true,  false, NA },
+    { MODULE_REVISION_CODE_DDR4,        0x15d,  0x01,   0x00,   0x00, false, false, NA },
     { DRAM_STEPPING,                    0x160,  0x01,   0x00,   0x00, false, false, NA },
     { MANUFACTURING_SECTION_CRC,        0x17f,  0x02,   0x00,   0x00, true,  false, NA },
     // Module Specific fields supported on both DDR3 and DDR4