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| author | Mike Baiocchi <mbaiocch@us.ibm.com> | 2016-11-04 11:30:17 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-03-08 11:06:34 -0500 |
| commit | c3d233bbaf7a2f274147d16edbc080bae0ffd714 (patch) | |
| tree | 8058bc8e764135eecc21cdcd1177814dd4e180c8 /src/include/usr/util/util_reasoncodes.H | |
| parent | 1301e43641f7d3f315a0abc8112fa88927c9fa9a (diff) | |
| download | blackbird-hostboot-c3d233bbaf7a2f274147d16edbc080bae0ffd714.tar.gz blackbird-hostboot-c3d233bbaf7a2f274147d16edbc080bae0ffd714.zip | |
Hostboot Base TCE Support
This commit adds the base support for hostboot to enable/disable the
use of TCEs. It allows for the creation and managment of a TCE table
and also initializes the P9 processors to use this table.
Change-Id: Idb40f9df5a90d8b7e87b2f5b745cbe7e66109df2
RTC:145071
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32562
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/include/usr/util/util_reasoncodes.H')
| -rw-r--r-- | src/include/usr/util/util_reasoncodes.H | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/include/usr/util/util_reasoncodes.H b/src/include/usr/util/util_reasoncodes.H index 4df8d3897..4b9c5c308 100644 --- a/src/include/usr/util/util_reasoncodes.H +++ b/src/include/usr/util/util_reasoncodes.H @@ -40,6 +40,14 @@ namespace Util UTIL_LIDMGR_RT = 0x06, UTIL_LIDMGR_CLEANUP = 0x07, // UtilLidMgr::cleanup UTIL_RT_CMDS = 0x08, // rt_cmds.C + UTIL_TCE_INIT_HDW = 0x09, // UtilTceMgr::initTceInHdw + UTIL_TCE_ALLOCATE = 0x0A, // UtilTceMgr::allocateTces + UTIL_TCE_DEALLOCATE = 0x0B, // UtilTceMgr::deallocateTces + UTIL_TCE_CREATE_TABLE = 0x0C, // UtilTceMgr::createTceTable + UTIL_TCE_DISABLE_TCES = 0x0D, // Util::UTIL_TCE_DISABLE_TCES + UTIL_TCE_MAP_PSIHB = 0x0E, // UtilTceMgr::mapPsiHostBridge + UTIL_TCE_UNMAP_PSIHB = 0x0F, // UtilTceMgr::unmapPsiHostBridge + }; enum ReasonCode @@ -55,6 +63,17 @@ namespace Util UTIL_LIDMGR_UNLOAD_RC_FAIL = UTIL_COMP_ID | 0x09, UTIL_LIDMGR_NOT_FOUND = UTIL_COMP_ID | 0x0A, UTIL_LIDMGR_MM_FAIL = UTIL_COMP_ID | 0x0B, + UTIL_TCE_INVALID_SIZE = UTIL_COMP_ID | 0x0C, + UTIL_TCE_ADDR_NOT_ALIGNED = UTIL_COMP_ID | 0x0D, + UTIL_TCE_DEV_MAP_FAIL = UTIL_COMP_ID | 0x0E, + UTIL_TCE_DEV_UNMAP_FAIL = UTIL_COMP_ID | 0x0F, + UTIL_TCE_NOT_ENOUGH_FREE_ENTRIES = UTIL_COMP_ID | 0x10, + UTIL_TCE_ENTRY_NOT_CONTIGUOUS = UTIL_COMP_ID | 0x11, + UTIL_TCE_PREVIOUSLY_ALLOCATED = UTIL_COMP_ID | 0x12, + UTIL_TCE_INVALID_COUNT = UTIL_COMP_ID | 0x13, + UTIL_TCE_ALLOC_BLOCK_FAIL = UTIL_COMP_ID | 0x14, + UTIL_TCE_BLOCK_UNMAP_FAIL = UTIL_COMP_ID | 0x15, + }; }; |
