1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
///
/// This file contains declaration for AMDGPU ISA disassembler
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
namespace llvm {
class MCContext;
class MCInst;
class MCSubtargetInfo;
class AMDGPUDisassembler : public MCDisassembler {
public:
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
MCDisassembler(STI, Ctx) {}
~AMDGPUDisassembler() {}
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &WS, raw_ostream &CS) const override;
/// Decode inline float value in VSrc field
DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
/// Decode inline integer value in VSrc field
DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
/// Decode VGPR register
DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
/// Decode SGPR register
DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
/// Decode register in VSrc field
DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;
DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
uint64_t Addr) const;
DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
uint64_t Addr) const;
};
} // namespace llvm
#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
|
