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* [X86] Add LODS schedule testsSimon Pilgrim2017-12-111-6/+103
| | | | llvm-svn: 320403
* [X86] Add CMP/TEST schedule testsSimon Pilgrim2017-12-111-2/+1184
| | | | llvm-svn: 320402
* [X86] Add AND/OR/XOR schedule testsSimon Pilgrim2017-12-111-3/+1926
| | | | llvm-svn: 320400
* [dwarfdump] Fix off-by-one bug in accelerator table extractor.Jonas Devlieghere2017-12-116-10/+16
| | | | | | | | | | | | | | | This fixes a bug where the verifier was complaining about empty accelerator tables. When the table is empty, its size is not a valid offset as it points after the end of the section. This patch also makes the extractor return llvm:Error instead of bool for better error reporting in the verifier. Differential revision: https://reviews.llvm.org/D41063 rdar://35932007 llvm-svn: 320399
* [X86] Add ADD/SUB schedule testsSimon Pilgrim2017-12-111-2/+1285
| | | | llvm-svn: 320397
* [X86] Add ADC/SBB schedule testsSimon Pilgrim2017-12-111-2/+1284
| | | | llvm-svn: 320395
* [X86] Add MOVSLQ schedule testsSimon Pilgrim2017-12-111-1/+97
| | | | llvm-svn: 320392
* Normalize line endings. NFCI.Simon Pilgrim2017-12-111-30/+30
| | | | llvm-svn: 320389
* [GlobalISel] Disable GISel for big endian.Amara Emerson2017-12-114-2/+16
| | | | | | | | | | | | | This is due to PR26161 needing to be resolved before we can fix big endian bugs like PR35359. The work to split aggregates into smaller LLTs instead of using one large scalar will take some time, so in the mean time we'll fall back to SDAG. Some ARM BE tests xfailed for now as a result. Differential Revision: https://reviews.llvm.org/D40789 llvm-svn: 320388
* [X86] Add LWP schedule testsSimon Pilgrim2017-12-112-2/+181
| | | | | | Tag LWP instructions as WriteSystem llvm-svn: 320387
* [X86] Add INT/INTO schedule testsSimon Pilgrim2017-12-112-2/+147
| | | | llvm-svn: 320386
* [X86] Add IN/OUT schedule testsSimon Pilgrim2017-12-111-2/+246
| | | | llvm-svn: 320385
* [X86] Add IDIV schedule testsSimon Pilgrim2017-12-111-1/+164
| | | | llvm-svn: 320384
* [X86] Add CMPXCHG schedule testsSimon Pilgrim2017-12-111-3/+415
| | | | llvm-svn: 320383
* [X86] Add CLZERO schedule testSimon Pilgrim2017-12-111-0/+20
| | | | llvm-svn: 320382
* [MSan] Hotfix compilationAlexander Potapenko2017-12-111-2/+2
| | | | | | | For some reason the override directives got removed in r320373. I suspect this to be an unwanted effect of clang-format. llvm-svn: 320381
* [X86] Add ADCX/ADOX/XADD/XLAT schedule testsSimon Pilgrim2017-12-111-3/+617
| | | | llvm-svn: 320380
* [X86] Modify Nontemporal tests to avoid deadstore optimization.Nirav Dave2017-12-114-47/+167
| | | | llvm-svn: 320379
* [AMDGPU] Rename Bonaire target to be gfx704; update target feature handlingTony Tye2017-12-111-139/+144
| | | | | | | | | | | | - Rename Bonaire target to be gfx704. - Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code. - List target features supported by each processor in the processor table together with the default value. - Add xnack flag to e_flags. - Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property. Differential Revision: https://reviews.llvm.org/D40051 llvm-svn: 320378
* [X86] Add SETCC/STC/STD/UD2 schedule testsSimon Pilgrim2017-12-111-3/+541
| | | | llvm-svn: 320376
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-1114-77/+396
| | | | | | | | | | | | See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 llvm-svn: 320375
* [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)Sanjay Patel2017-12-112-1/+36
| | | | | | | | | | | | | | | | | | | | | | | At first, I tried to thread the x86 needle and use a target hook (isVectorShiftByScalarCheap()) to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only some element types, but...it's difficult. Here we just avoid the loop with the x86 vector transform that conflicts with the general DAG combine and preserve all of the existing behavior AFAICT otherwise. Some tests that will probably fail if someone does try to restrict this in a more targeted way for x86-only may be found in: test/CodeGen/X86/combine-mul.ll test/CodeGen/X86/vector-mul.ll test/CodeGen/X86/widen_arith-5.ll This should prevent the infinite looping seen with: https://bugs.llvm.org/show_bug.cgi?id=35579 Differential Revision: https://reviews.llvm.org/D41040 llvm-svn: 320374
* [MSan] introduce getShadowOriginPtr(). NFC.Alexander Potapenko2017-12-111-129/+191
| | | | | | | | | | | | | | This patch introduces getShadowOriginPtr(), a method that obtains both the shadow and origin pointers for an address as a Value pair. The existing callers of getShadowPtr() and getOriginPtr() are updated to use getShadowOriginPtr(). The rationale for this change is to simplify KMSAN instrumentation implementation. In KMSAN origins tracking is always enabled, and there's no direct mapping between the app memory and the shadow/origin pages. Both the shadow and the origin pointer for a given address are obtained by calling a single runtime hook from the instrumentation, therefore it's easier to work with those pointers together. Reviewed at https://reviews.llvm.org/D40835. llvm-svn: 320373
* [X86] Add SAR/SHL/SHR schedule testsSimon Pilgrim2017-12-111-3/+972
| | | | llvm-svn: 320371
* [X86] Add RCL/RCR schedule testsSimon Pilgrim2017-12-111-2/+732
| | | | llvm-svn: 320370
* [Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek2017-12-112-1/+24
| | | | | | | | A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369
* [PowerPC] Sign-extend negative constant storesNemanja Ivanovic2017-12-113-10/+10
| | | | | | | | | | | | | Second part of https://reviews.llvm.org/D40348. Revision r318436 has extended all constants feeding a store to 64 bits to allow for CSE on the SDAG. However, negative constants were zero extended which made the constant being loaded appear to be a positive value larger than 16 bits. This resulted in long sequences to materialize such constants rather than simply a "load immediate". This patch just sign-extends those updated constants so that they remain 16-bit signed immediates if they started out that way. llvm-svn: 320368
* [DAGCombiner] Add combined indexed load to the work listNemanja Ivanovic2017-12-111-0/+1
| | | | | | | | | | This commit is the first part of https://reviews.llvm.org/D40348. In order to allow target combines to be performed on newly combined indexed loads, add them back to the worklist. The remainder of the above patch will be committed in subsequent revisions and will use this. Test cases will be included with those follow-up commits. llvm-svn: 320365
* [ARM GlobalISel] Add test for a MOVTi16 pattern. NFCDiana Picus2017-12-111-0/+31
| | | | | | Add test for matching an OR with 0xFFFF0000 to a MOVTi16. llvm-svn: 320362
* [X86] Add fsgsbase schedule tests.Simon Pilgrim2017-12-112-6/+411
| | | | llvm-svn: 320361
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-1110-49/+1871
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-112-0/+70
| | | | llvm-svn: 320358
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-1123-49/+1040
| | | | | | | | | | As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
* [X86] Regenerate fsgsbase intrinsic tests. NFCI.Simon Pilgrim2017-12-111-9/+34
| | | | llvm-svn: 320356
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-117-36/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 - fixes PR35103 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 320355
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-1118-129/+242
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* [ARM GlobalISel] Add tests for PKHBT and PKHTBDiana Picus2017-12-111-0/+254
| | | | | | | | Test (some of) the patterns for selecting PKHBT and PKHTB. The others are just very similar to the ones we're testing and there would be little value in covering them as well. llvm-svn: 320352
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-1148-2607/+134
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [AVR] Implement some missing code pathsDylan McKay2017-12-114-15/+54
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.Craig Topper2017-12-112-8/+19
| | | | | | We should probably also fold (mulhs/u X, 1) for vectors, but that's harder. llvm-svn: 320344
* [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFCCraig Topper2017-12-111-4/+3
| | | | llvm-svn: 320343
* [X86] Regenerate test with update_llc_test_checks.pyCraig Topper2017-12-111-76/+340
| | | | llvm-svn: 320342
* [X86] Add a test case for masked scatter where the index needs to be ↵Craig Topper2017-12-111-0/+52
| | | | | | legalized from v2i32 while other types are legal. llvm-svn: 320340
* [X86] Add ROL/ROR schedule testsSimon Pilgrim2017-12-101-2/+732
| | | | llvm-svn: 320334
* [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule testsSimon Pilgrim2017-12-101-6/+862
| | | | llvm-svn: 320333
* [X86] Add DEC/INC schedule testsSimon Pilgrim2017-12-102-2/+1079
| | | | | | Include i686 (non-REX) variant tests as well llvm-svn: 320332
* [X86] Add INS/OUTS schedule testsSimon Pilgrim2017-12-101-8/+186
| | | | llvm-svn: 320331
* [X86] Add CMPS/MOVS/SCAS/STOS schedule testsSimon Pilgrim2017-12-101-20/+412
| | | | llvm-svn: 320330
* [X86] Add CMOV schedule testsSimon Pilgrim2017-12-102-1/+2004
| | | | llvm-svn: 320329
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