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| author | Diana Picus <diana.picus@linaro.org> | 2017-12-11 13:28:45 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-12-11 13:28:45 +0000 |
| commit | 291e8d924ff47fdb9a0920a15a183ca699ecd6c0 (patch) | |
| tree | 6ee4bea54cff4d2faae97767a2c11d63eaf44645 /llvm | |
| parent | 969850f514574584042a84c3e0c0552e407081aa (diff) | |
| download | bcm5719-llvm-291e8d924ff47fdb9a0920a15a183ca699ecd6c0.tar.gz bcm5719-llvm-291e8d924ff47fdb9a0920a15a183ca699ecd6c0.zip | |
[ARM GlobalISel] Add test for a MOVTi16 pattern. NFC
Add test for matching an OR with 0xFFFF0000 to a MOVTi16.
llvm-svn: 320362
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir index 406fa0250ac..a683d3ab4e7 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -28,6 +28,8 @@ define void @test_pkhtb_imm16() #0 { ret void } define void @test_pkhtb_imm1_15() #0 { ret void } + define void @test_movti16_0xffff() #2 { ret void } + attributes #0 = { "target-features"="+v6" } attributes #1 = { "target-features"="-v6" } attributes #2 = { "target-features"="+v6t2" } @@ -832,3 +834,32 @@ body: | BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... +--- +name: test_movti16_0xffff +# CHECK-LABEL: name: test_movti16_0xffff +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 + + %1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 + + %2(s32) = G_OR %0, %1 + ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, %noreg + + %r0 = COPY %2(s32) + ; CHECK: %r0 = COPY [[VREGR]] + + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 +... |
