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* [X86][SSE] Vectorized i64 uniform constant SRA shiftsSimon Pilgrim2015-07-067-81/+106
| | | | | | | | This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
* WebAssembly: add some TODOJF Bastien2015-07-061-0/+11
| | | | | | | | | | Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D10971 llvm-svn: 241513
* llvm-nm: treat weak undefined as undefined.Rafael Espindola2015-07-063-14/+29
| | | | | | This matches the behavior of gnu ld. llvm-svn: 241512
* [WinEH] Add some test cases I forgot to add to previous commitsReid Kleckner2015-07-062-0/+258
| | | | llvm-svn: 241510
* [WinEH] Insert the EH code load before the block terminatorReid Kleckner2015-07-062-1/+67
| | | | | | | The previous code put the load after the terminator, leading to invalid IR and downstream crashes. This caused http://crbug.com/506446. llvm-svn: 241509
* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-069-6/+521
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* [X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 ↵Simon Pilgrim2015-07-066-138/+177
| | | | | | | | | | | | implementation With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations. This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code. Differential Revision: http://reviews.llvm.org/D10947 llvm-svn: 241506
* [TwoAddressInstructionPass] Rename a variable to match the coding style.Quentin Colombet2015-07-061-4/+4
| | | | | | Spot by Bruno. llvm-svn: 241505
* Swap operands instead of using !.Rafael Espindola2015-07-061-1/+1
| | | | | | | | This avoids returning true for A == B. Thanks to Benjamin Kramer for noticing it. llvm-svn: 241490
* When sorting by address, undefined symbols go first.Rafael Espindola2015-07-062-16/+21
| | | | | | This matches gnu nm. llvm-svn: 241488
* Reduce code duplication. NFC.Rafael Espindola2015-07-061-41/+17
| | | | llvm-svn: 241484
* [llvm-extract] Drop comdats from declarationsReid Kleckner2015-07-062-4/+13
| | | | | | The verifier rejects comdats on declarations. llvm-svn: 241483
* Fix printing of common symbols.Rafael Espindola2015-07-062-4/+12
| | | | | | Printing the symbol size matches the behavior or both gnu nm and freebsd nm. llvm-svn: 241480
* llc: Add a 'run-pass' option.Alex Lorenz2015-07-069-42/+81
| | | | | | | | | | | | | | | This commit adds a 'run-pass' option to llc, which instructs the compiler to run one specific code generation pass only. Llc already has the 'start-after' and the 'stop-after' options, and this new option complements the other two by making it easier to write tests that want to invoke a single pass only. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10776 llvm-svn: 241476
* AMDGPU: Run SIInsertWaits as pre-emit passMatt Arsenault2015-07-061-1/+1
| | | | | | | | | | | Running this after the scheduler enables scheduling waits later so other ALU instructions can run while this would be waiting. When combined with enabling the post-RA scheduler, this gives about a ~20% improvement on sgemm. llvm-svn: 241473
* Change the last few internal StringRef triples into Triple objects.Daniel Sanders2015-07-0616-79/+86
| | | | | | | | | | | | | | | | | | | | Summary: This concludes the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. At this point, the StringRef-form of GNU Triples should only be used in the public API (including IR serialization) and a couple objects that directly interact with the API (most notably the Module class). The next step is to replace these Triple objects with the TargetTuple object that will represent our authoratative/unambiguous internal equivalent to GNU Triples. Reviewers: rengolin Subscribers: llvm-commits, jholewinski, ted, rengolin Differential Revision: http://reviews.llvm.org/D10962 llvm-svn: 241472
* DIBuilder: Don't rauw null pointers with empty arrays in finalize().Adrian Prantl2015-07-061-6/+12
| | | | | | This makes the IR a little easier to read. llvm-svn: 241470
* Where Triple has a suitable predicate, use it rather than the enum values. NFC.Daniel Sanders2015-07-065-9/+7
| | | | | | | | | | Reviewers: mcrosier Subscribers: llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10960 llvm-svn: 241469
* use range-based for loops; NFCISanjay Patel2015-07-061-10/+8
| | | | llvm-svn: 241468
* Resubmit "Add new EliminateAvailableExternally module pass" (r239480)Teresa Johnson2015-07-066-0/+120
| | | | | | | | | | | | | | | | | | | | | | This change includes a fix for https://code.google.com/p/chromium/issues/detail?id=499508#c3, which required updating the visibility for symbols with eliminated definitions. --Original Commit Message-- Add new EliminateAvailableExternally module pass, which is performed in O2 compiles just before GlobalDCE, unless we are preparing for LTO. This pass eliminates available externally globals (turning them into declarations), regardless of whether they are dead/unreferenced, since we are guaranteed to have a copy available elsewhere at link time. This enables additional opportunities for GlobalDCE. If we are preparing for LTO (e.g. a -flto -c compile), the pass is not included as we want to preserve available externally functions for possible link time inlining. The FE indicates whether we are doing an -flto compile via the new PrepareForLTO flag on the PassManagerBuilder. llvm-svn: 241466
* Use an early exit in DIBuilder::finalize() to improve readability.Adrian Prantl2015-07-061-28/+32
| | | | llvm-svn: 241465
* Use the correct DIArray types in DICompileUnit::replace*().Adrian Prantl2015-07-061-3/+3
| | | | | | Thanks to Yaron Keren for noticing! llvm-svn: 241464
* use range-based for loops; NFCISanjay Patel2015-07-061-8/+6
| | | | llvm-svn: 241463
* AMDGPU/SI: Add debugging subtarget feature for DS offsetsMatt Arsenault2015-07-065-3/+21
| | | | | | | | We don't have a good way to detect most situations where DS offsets are usable on SI, so add an option to force using them even if unsafe for debugging performance problems. llvm-svn: 241462
* [Sparc] Add more instruction aliases.James Y Knight2015-07-064-15/+256
| | | | | | | | | These are mostly from the chart in the SparcV8 spec, section "A.3 Synthetic Instructions". Differential Revision: http://reviews.llvm.org/D9834 llvm-svn: 241461
* [Sparc] Add support for flush instruction.James Y Knight2015-07-063-0/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D9833 llvm-svn: 241460
* Simplify. NFC.Rafael Espindola2015-07-061-3/+1
| | | | llvm-svn: 241458
* Simplify. NFC.Rafael Espindola2015-07-061-3/+1
| | | | llvm-svn: 241456
* Inline function into single use. NFC.Rafael Espindola2015-07-061-6/+0
| | | | llvm-svn: 241453
* Remove getRelocationAddress.Rafael Espindola2015-07-0615-74/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally added in r139314. Back then it didn't actually get the address, it got whatever value the relocation used: address or offset. The values in different object formats are: * MachO: Always an offset. * COFF: Always an address, but when talking about the virtual address of sections it says: "for simplicity, compilers should set this to zero". * ELF: An offset for .o files and and address for .so files. In the case of the .so, the relocation in not linked to any section (sh_info is 0). We can't really compute an offset. Some API mappings would be: * Use getAddress for everything. It would be quite cumbersome. To compute the address elf has to follow sh_info, which can be corrupted and therefore the method has to return an ErrorOr. The address of the section is also the same for every relocation in a section, so we shouldn't have to check the error and fetch the value for every relocation. * Use a getValue and make it up to the user to know what it is getting. * Use a getOffset and: * Assert for dynamic ELF objects. That is a very peculiar case and it is probably fair to ask any tool that wants to support it to use ELF.h. The only tool we have that reads those (llvm-readobj) already does that. The only other use case I can think of is a dynamic linker. * Check that COFF .obj files have sections with zero virtual address spaces. If it turns out that some assembler/compiler produces these, we can change COFFObjectFile::getRelocationOffset to subtract it. Given COFF format, this can be done without the need for ErrorOr. The getRelocationAddress method was never implemented for COFF. It also had exactly one use in a very peculiar case: a shortcut for adding the section value to a pcrel reloc on MachO. Given that, I don't expect that there is any use out there of the C API. If that is not the case, let me know and I will add it back with the implementation inlined and do a proper deprecation. llvm-svn: 241450
* Fix a bug in the A57FPLoadBalancing register tracking/scavenger.Chad Rosier2015-07-061-3/+11
| | | | | | | | | | | | The code in AArch64A57FPLoadBalancing::scavengeRegister() to handle dead defs was not correctly handling aliased registers. E.g. if the dead def was of D2, then S2 was not being marked as unavailable, so it could potentially be used across a live-range in which it would be clobbered. Patch by Geoff Berry <gberry@codeaurora.org>! Phabricator: http://reviews.llvm.org/D10900 llvm-svn: 241449
* Check that COFF .obj files have sections with zero virtual address spaces.Rafael Espindola2015-07-064-1/+21
| | | | | | | | | | | | | When talking about the virtual address of sections the coff spec says: ... for simplicity, compilers should set this to zero. Otherwise, it is an arbitrary value that is subtracted from offsets during relocation. We don't currently subtract it, so check that it is zero. If some producer does create such files, we can change getRelocationOffset instead. llvm-svn: 241447
* [X86][SSE] Added missing stack folding test for SQRTSD and SQRTSS instructions.Simon Pilgrim2015-07-061-2/+14
| | | | llvm-svn: 241445
* [X86][AVX512] Multiply Packed Unsigned Integers with Round and ScaleAsaf Badouh2015-07-0610-0/+167
| | | | | | | | | pmulhrsw review: http://reviews.llvm.org/D10948 llvm-svn: 241443
* [Mips] Add support for MCJIT for MIPS32r6Petar Jovanovic2015-07-063-3/+112
| | | | | | | | | | Add support for resolving MIPS32r6 relocations in MCJIT. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10687 llvm-svn: 241442
* Fix handling of ELF::R_MIPS_32 on Mips64.Rafael Espindola2015-07-063-4/+17
| | | | | | Thanks to Aboud, Amjad for reporting the regression and providing the testcase. llvm-svn: 241440
* [TableGen] Change a couple methods to return an ArrayRef instead of a const ↵Craig Topper2015-07-064-6/+6
| | | | | | std::vector reference. NFC llvm-svn: 241430
* Make this test a bit more interesting.Rafael Espindola2015-07-061-1/+4
| | | | | | Before every test was using a section with an address of zero. llvm-svn: 241427
* Untabify.NAKAMURA Takumi2015-07-063-9/+9
| | | | llvm-svn: 241423
* change CHECK to CHECK-LABEL for more precisionSanjay Patel2015-07-051-1/+1
| | | | llvm-svn: 241422
* remove unnecessary test specificationsSanjay Patel2015-07-051-5/+4
| | | | llvm-svn: 241419
* minimize test case and remove unnecessary opt passesSanjay Patel2015-07-051-65/+24
| | | | llvm-svn: 241418
* remove unnecessary temp variable; NFCISanjay Patel2015-07-051-5/+4
| | | | llvm-svn: 241415
* Verifier: Forbid comdats on linker declarations.Peter Collingbourne2015-07-053-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D10945 llvm-svn: 241414
* IR: Do not consider available_externally linkage to be linker-weak.Peter Collingbourne2015-07-0514-71/+55
| | | | | | | | | | | | | | | From the linker's perspective, an available_externally global is equivalent to an external declaration (per isDeclarationForLinker()), so it is incorrect to consider it to be a weak definition. Also clean up some logic in the dead argument elimination pass and clarify its comments to better explain how its behavior depends on linkage, introduce GlobalValue::isStrongDefinitionForLinker() and start using it throughout the optimizers and backend. Differential Revision: http://reviews.llvm.org/D10941 llvm-svn: 241413
* use range-based for loops; NFCISanjay Patel2015-07-051-8/+7
| | | | llvm-svn: 241412
* [TargetLowering] StringRefize asm constraint getters.Benjamin Kramer2015-07-0526-111/+81
| | | | | | | | There is some functional change here because it changes target code from atoi(3) to StringRef::getAsInteger which has error checking. For valid constraints there should be no difference. llvm-svn: 241411
* [X86][SSE3] Just use an explicit SSE3 target attribute - not a cpu type.Simon Pilgrim2015-07-051-1/+1
| | | | | | Merged arch/target into a specific triple - we had i686 and x86_64 targets overriding each other.... llvm-svn: 241410
* [X86][SSE2] Just use an explicit SSE2 target attribute - not a cpu type.Simon Pilgrim2015-07-051-1/+1
| | | | | | corei7 is capable of a lot more than just SSE2.... llvm-svn: 241409
* [RuntimeDyld] Add comment documenting the behavior change in r241383.Lang Hames2015-07-051-0/+4
| | | | llvm-svn: 241408
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