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* [PowerPC] Sign-extend negative constant storesNemanja Ivanovic2017-12-113-10/+10
| | | | | | | | | | | | | Second part of https://reviews.llvm.org/D40348. Revision r318436 has extended all constants feeding a store to 64 bits to allow for CSE on the SDAG. However, negative constants were zero extended which made the constant being loaded appear to be a positive value larger than 16 bits. This resulted in long sequences to materialize such constants rather than simply a "load immediate". This patch just sign-extends those updated constants so that they remain 16-bit signed immediates if they started out that way. llvm-svn: 320368
* [DAGCombiner] Add combined indexed load to the work listNemanja Ivanovic2017-12-111-0/+1
| | | | | | | | | | This commit is the first part of https://reviews.llvm.org/D40348. In order to allow target combines to be performed on newly combined indexed loads, add them back to the worklist. The remainder of the above patch will be committed in subsequent revisions and will use this. Test cases will be included with those follow-up commits. llvm-svn: 320365
* [ARM GlobalISel] Add test for a MOVTi16 pattern. NFCDiana Picus2017-12-111-0/+31
| | | | | | Add test for matching an OR with 0xFFFF0000 to a MOVTi16. llvm-svn: 320362
* [X86] Add fsgsbase schedule tests.Simon Pilgrim2017-12-112-6/+411
| | | | llvm-svn: 320361
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-1110-49/+1871
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-112-0/+70
| | | | llvm-svn: 320358
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-1123-49/+1040
| | | | | | | | | | As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
* [X86] Regenerate fsgsbase intrinsic tests. NFCI.Simon Pilgrim2017-12-111-9/+34
| | | | llvm-svn: 320356
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-117-36/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 - fixes PR35103 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 320355
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-1118-129/+242
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* [ARM GlobalISel] Add tests for PKHBT and PKHTBDiana Picus2017-12-111-0/+254
| | | | | | | | Test (some of) the patterns for selecting PKHBT and PKHTB. The others are just very similar to the ones we're testing and there would be little value in covering them as well. llvm-svn: 320352
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-1148-2607/+134
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [AVR] Implement some missing code pathsDylan McKay2017-12-114-15/+54
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.Craig Topper2017-12-112-8/+19
| | | | | | We should probably also fold (mulhs/u X, 1) for vectors, but that's harder. llvm-svn: 320344
* [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFCCraig Topper2017-12-111-4/+3
| | | | llvm-svn: 320343
* [X86] Regenerate test with update_llc_test_checks.pyCraig Topper2017-12-111-76/+340
| | | | llvm-svn: 320342
* [X86] Add a test case for masked scatter where the index needs to be ↵Craig Topper2017-12-111-0/+52
| | | | | | legalized from v2i32 while other types are legal. llvm-svn: 320340
* [X86] Add ROL/ROR schedule testsSimon Pilgrim2017-12-101-2/+732
| | | | llvm-svn: 320334
* [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule testsSimon Pilgrim2017-12-101-6/+862
| | | | llvm-svn: 320333
* [X86] Add DEC/INC schedule testsSimon Pilgrim2017-12-102-2/+1079
| | | | | | Include i686 (non-REX) variant tests as well llvm-svn: 320332
* [X86] Add INS/OUTS schedule testsSimon Pilgrim2017-12-101-8/+186
| | | | llvm-svn: 320331
* [X86] Add CMPS/MOVS/SCAS/STOS schedule testsSimon Pilgrim2017-12-101-20/+412
| | | | llvm-svn: 320330
* [X86] Add CMOV schedule testsSimon Pilgrim2017-12-102-1/+2004
| | | | llvm-svn: 320329
* [X86] Add BT/BTC/BTR/BTS schedule testsSimon Pilgrim2017-12-101-4/+669
| | | | llvm-svn: 320328
* [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the ↵Craig Topper2017-12-101-4/+4
| | | | | | skylake server sheduler model llvm-svn: 320326
* [X86] Rename some instructions that start with Int_ to have the _Int at the end.Craig Topper2017-12-1013-267/+267
| | | | | | | | This matches AVX512 version and is more consistent overall. And improves our scheduler models. In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses. llvm-svn: 320325
* [X86][X87] Fix typo in znver1 FIST/FISTT schedule patternsSimon Pilgrim2017-12-102-5/+5
| | | | llvm-svn: 320322
* [X86][X87] Add missing x87 scheduler testsSimon Pilgrim2017-12-101-62/+1322
| | | | | | Split off some 'n' instruction versions to make it clearer when WAIT is being inserted llvm-svn: 320321
* [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper ↵Craig Topper2017-12-103-18/+18
| | | | | | | | suffix. Fix the scheduling information for some of them. Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)' llvm-svn: 320320
* [X86] Add VCVTQQ2PS to the skylake server scheduler models.Craig Topper2017-12-102-1/+7
| | | | llvm-svn: 320319
* [X86] Add VPMULLWZ256 to the skylake server scheduler modelCraig Topper2017-12-101-0/+2
| | | | llvm-svn: 320318
* [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler ↵Craig Topper2017-12-101-2/+4
| | | | | | model. llvm-svn: 320317
* [X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper2017-12-104-15/+15
| | | | | | This makes things consistent with our normal instruction naming. llvm-svn: 320316
* [X86] Add VPSRLWZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320315
* [X86] Add VPUNPCKLWDZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320314
* [X86] Adjust tablegen includes so we can use Instructions in scheduler ↵Craig Topper2017-12-102-26/+25
| | | | | | | | models instead of just instregexs. This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models. llvm-svn: 320313
* [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) callSanjay Patel2017-12-102-15/+12
| | | | | | | Follow-up for a bug that's similar to: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320312
* [InstCombine] add test for pow(x, -1.0) with FMF; NFCSanjay Patel2017-12-101-20/+23
| | | | llvm-svn: 320311
* [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)Sanjay Patel2017-12-102-3/+8
| | | | | | | This should fix the larger problem with sqrt shown in: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320310
* [InstCombine] add test for pow(x, 2.0) with FMF; NFCSanjay Patel2017-12-101-6/+18
| | | | llvm-svn: 320309
* [X86] Flag BroadWell scheduler model as completeSimon Pilgrim2017-12-108-44/+43
| | | | | | Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder. llvm-svn: 320308
* Regenerate some AVX2+ scheduling tests that got missedSimon Pilgrim2017-12-102-39/+39
| | | | llvm-svn: 320307
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320306
* Regenerate some scheduling tests that got missedSimon Pilgrim2017-12-102-20/+20
| | | | llvm-svn: 320305
* [X86] Flag ZNVER1 scheduler model as completeSimon Pilgrim2017-12-101-6/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320304
* [X86] Flag SLM scheduler model as completeSimon Pilgrim2017-12-101-5/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320303
* [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classesSimon Pilgrim2017-12-102-3/+9
| | | | llvm-svn: 320302
* [X86] Tag SSE4A instructions as SSE INTALU scheduler classesSimon Pilgrim2017-12-101-4/+8
| | | | llvm-svn: 320301
* [X86] Flag BTVER2 scheduler model as completeSimon Pilgrim2017-12-101-4/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320300
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