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* Add support for addmod to mri scripts.Rafael Espindola2014-10-212-1/+23
| | | | llvm-svn: 220294
* [PowerPC] Avoid VSX FMA mutate when killed product reg = addend regBill Schmidt2014-10-213-2/+29
| | | | | | | | | | | | | | | | | | | | | With VSX enabled, test/CodeGen/PowerPC/recipest.ll exposes a bug in the FMA mutation pass. If we have a situation where a killed product register is the same register as the FMA target, such as: %vreg5<def,tied1> = XSNMSUBADP %vreg5<tied0>, %vreg11, %vreg5, %RM<imp-use>; VSFRC:%vreg5 F8RC:%vreg11 then the substitution makes no sense. We end up getting a crash when we try to extend the interval associated with the killed product register, as there is already a live range for %vreg5 there. This patch just disables the mutation under those circumstances. Since recipest.ll generates different code with VMX enabled, I've modified that test to use -mattr=-vsx. I've borrowed the code from that test that exposed the bug and placed it in fma-mutate.ll, where it tests several mutation opportunities including the "bad" one. llvm-svn: 220290
* [ARM] NEON 32-bit scalar moves are also available in VFPv2Oliver Stannard2014-10-212-2/+35
| | | | | | | | | | | The 32-bit variants of the NEON scalar<->GPR move instructions are also available in VFPv2. The 8- and 16-bit variants do require NEON. Note that the checks in the test file are all -DAG because they are checking a mixture of stdout and stderr, and the ordering is not guaranteed. llvm-svn: 220288
* [asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an ↵Yuri Gorshenin2014-10-212-83/+135
| | | | | | | | | | | | | | index register. Summary: Fixed memory accesses with rbp as a base or an index register. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5819 llvm-svn: 220283
* [Thumb2] LDRS?[BH] cannot load to the PCOliver Stannard2014-10-212-4/+55
| | | | | | | The Thumb2 LDRS?[BH] instructions are not valid when the destination register is the PC (these encodings are used for preload hints). llvm-svn: 220278
* Teach the load analysis to allow finding available values which requireChandler Carruth2014-10-217-18/+136
| | | | | | | | | | | | | | | | | | | | inttoptr or ptrtoint cast provided there is datalayout available. Eventually, the datalayout can just be required but in practice it will always be there today. To go with the ability to expose available values requiring a ptrtoint or inttoptr cast, helpers are added to perform one of these three casts. These smarts are necessary to finish canonicalizing loads and stores to the operational type requirements without regressing fundamental combines. I've added some test cases. These should actually improve as the load combining and store combining improves, but they may fundamentally be highlighting some missing combines for select in addition to exercising the specific added logic to load analysis. llvm-svn: 220277
* [mips][microMIPS] Implement ADDU16 and SUBU16 instructionsZoran Jovanovic2014-10-214-0/+35
| | | | | | Differential Revision: http://reviews.llvm.org/D5118 llvm-svn: 220276
* [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructionsZoran Jovanovic2014-10-214-0/+50
| | | | | | Differential Revision: http://reviews.llvm.org/D5117 llvm-svn: 220275
* [mips][microMIPS] Implement microMIPS 16-bit instructions registersZoran Jovanovic2014-10-213-0/+46
| | | | | | Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
* Fix a bit of confusion about .set and produce more readable assembly.Rafael Espindola2014-10-2115-91/+63
| | | | | | | | | | | | | | | Every target we support has support for assembly that looks like a = b - c .long a What is special about MachO is that the above combination suppresses the production of a relocation. With this change we avoid producing the intermediary labels when they don't add any value. llvm-svn: 220256
* Do not attribute static allocas to the call site's DebugLoc.Paul Robinson2014-10-212-0/+149
| | | | | | | | | | | | | When functions are inlined, instructions without debug information are attributed to the call site's DebugLoc. After inlining, inlined static allocas are moved to the caller's entry block, adjacent to the caller's original static alloca instructions. By retaining the call site's DebugLoc, these instructions could cause instructions that were subsequently inserted at the entry block to pick up the same DebugLoc. Patch by Wolfgang Pieb! llvm-svn: 220255
* Make this test a bit more strict.Rafael Espindola2014-10-211-6/+11
| | | | llvm-svn: 220253
* Teach lit to filter the host LDFLAGS down from the build system and intoChandler Carruth2014-10-215-1/+5
| | | | | | | | | | the CGO build environment. This lets things like -rpath propagate down to the C++ code that is built along side the Go bindings when testing them. Patch by Peter Collingbourne, and verified that it works by me. llvm-svn: 220252
* PR21202: Memory leak in Windows RWMutexImpl when using SRWLOCKDavid Blaikie2014-10-211-5/+3
| | | | llvm-svn: 220251
* Make AsmPrinter::EmitLabelOffsetDifference a static helper and simplify.Rafael Espindola2014-10-213-39/+27
| | | | | | It had exactly one caller in a position where we know hasSetDirective is true. llvm-svn: 220250
* [MCJIT] Temporarily revert r220245 - it broke several bots.Lang Hames2014-10-2110-62/+7
| | | | | | (See e.g. http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/17653) llvm-svn: 220249
* Introduce enum values for previously defined metadata types. (NFC)Philip Reames2014-10-218-15/+33
| | | | | | | | | | | Our metadata scheme lazily assigns IDs to string metadata, but we have a mechanism to preassign them as well. Using a preassigned ID is helpful since we get compile time type checking, and avoid some (minimal) string construction and comparison. This change adds enum value for three existing metadata types: + MD_nontemporal = 9, // "nontemporal" + MD_mem_parallel_loop_access = 10, // "llvm.mem.parallel_loop_access" + MD_nonnull = 11 // "nonnull" I went through an updated various uses as well. I made no attempt to get all uses; I focused on the ones which were easily grepable and easily to translate. For example, there were several items in LoopInfo.cpp I chose not to update. llvm-svn: 220248
* Extend the verifier to validate range metadata on calls and invokes.Philip Reames2014-10-202-52/+68
| | | | | | Range metadata applies to loads, call, and invokes. We were validating that metadata applied to loads was correct according to the LangRef, but we were not validating metadata applied to calls or invokes. This change extracts the checking functionality to a common location, reuses it for all valid locations, and adds a simple test to ensure a misused range on a call gets reported. llvm-svn: 220246
* [MCJIT] Make MCJIT honor symbol visibility settings when populating the globalLang Hames2014-10-2010-7/+62
| | | | | | | | symbol table. Patch by Anthony Pesch. Thanks Anthony! llvm-svn: 220245
* [X86] Fix a bug in the lowering of the mask of VSELECT.Quentin Colombet2014-10-202-1/+33
| | | | | | | | | | | | | | | | X86 code to lower VSELECT messed a bit with the bits set in the mask of VSELECT when it knows it can be lowered into BLEND. Indeed, only the high bits need to be set for those and it optimizes those accordingly. However, when the mask is a compile time constant, the lowering will be handled by the generic optimizer and those modifications will generate bad code in the generic optimizer. This patch fixes that by preventing the optimization if the VSELECT will be handled by the generic optimizer. <rdar://problem/18675020> llvm-svn: 220242
* Introduce a 'nonnull' metadata on Load instructions.Philip Reames2014-10-203-1/+36
| | | | | | | | | The newly introduced 'nonnull' metadata is analogous to existing 'nonnull' attributes, but applies to load instructions rather than call arguments or returns. Long term, it would be nice to combine these into a single construct. The value of the load is allowed to vary between successive loads, but null is not a valid value to be loaded by any load marked nonnull. Reviewed by: Hal Finkel Differential Revision: http://reviews.llvm.org/D5220 llvm-svn: 220240
* [X86] Memory folding for commutative instructions (updated)Simon Pilgrim2014-10-205-59/+202
| | | | | | | | | | | | This patch improves support for commutative instructions in the x86 memory folding implementation by attempting to fold a commuted version of the instruction if the original folding fails - if that folding fails as well the instruction is 're-commuted' back to its original order before returning. Updated version of r219584 (reverted in r219595) - the commutation attempt now explicitly ensures that neither of the commuted source operands are tied to the destination operand / register, which was the source of all the regressions that occurred with the original patch attempt. Added additional regression test case provided by Joerg Sonnenberger. Differential Revision: http://reviews.llvm.org/D5818 llvm-svn: 220239
* Explain why we don't always use --gc-sections.Rafael Espindola2014-10-201-0/+4
| | | | llvm-svn: 220237
* ARM: rework Thumb1 frame index rewritingTim Northover2014-10-206-114/+102
| | | | | | | | | | | | | | | | | | | | | | | The previous code had a few problems, motivating the choices here. 1. It could create instructions clobbering CPSR, but the incoming MachineInstr didn't reflect this. A potential source of corruption. This is why the patch has a new PseudoInst for before lowering. 2. Similarly, there was some code to handle the incoming instruction not being ARMCC::AL, but this would have caused massive problems if it was actually invoked when a complex offset needing more than one instruction was requested. 3. It wasn't designed to handle unaligned pointers (or offsets). These should probably be minimised anyway, but the code needs to deal with them properly regardless. 4. It had some rather dubious ad-hoc code to avoid calling emitThumbRegPlusImmediate, a function which should be designed to do precisely this job. We seem to cover the common cases correctly now, and hopefully can enhance emitThumbRegPlusImmediate to handle any extra optimisations we need to add in future. llvm-svn: 220236
* Try to fix GCC error about invalid use of const_cast in const version of ↵Alexey Samsonov2014-10-201-1/+1
| | | | | | ErrorOr::get() llvm-svn: 220233
* Constify getELFDynamicSymbolIterators standalone function. NFC.Alexey Samsonov2014-10-201-1/+1
| | | | llvm-svn: 220232
* Add const version of OwningBinary::getBinaryAlexey Samsonov2014-10-201-0/+6
| | | | llvm-svn: 220231
* Be more specific about return type of MachOUniversalBinary::getObjectForArchAlexey Samsonov2014-10-202-6/+4
| | | | llvm-svn: 220230
* Constify input argument of RelocVisitor and DWARFContext constructors. NFC.Alexey Samsonov2014-10-205-6/+6
| | | | llvm-svn: 220228
* Teach Lit to catch OSError exceptions when creating a process during theDan Liew2014-10-201-7/+10
| | | | | | | | | execution of a shell command. This can happen for example if the ``RUN:`` line calls a python script which can work correctly under Linux/OSX but will not work under Windows. A more useful error message is now shown rather than an unhelpful backtrace. llvm-svn: 220227
* Moved out IIT_V64 from common values section.Robert Khasanov2014-10-202-10/+10
| | | | | | Thanks Juergen Ributzka for notice. llvm-svn: 220224
* [AArch64] test case for compfail fixed by r219748Gerolf Hoflehner2014-10-201-2/+36
| | | | llvm-svn: 220206
* Fix Intrinsic::getType not working with varargSteven Wu2014-10-201-0/+6
| | | | | | | | VarArg Intrinsic functions are encoded with "void" type as the last argument. Now Intrinsic::getType can correctly return all the intrinsic function type. llvm-svn: 220205
* [Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7MOliver Stannard2014-10-202-3/+20
| | | | | | | These instructions are related to the v7[AR] exception model, and are not defined on v7M. llvm-svn: 220204
* Remove unnecessary else.Sid Manning2014-10-201-4/+4
| | | | llvm-svn: 220200
* Revert r220174, "Always use -Wl,-gc-sections on our build."NAKAMURA Takumi2014-10-201-9/+6
| | | | | | | | | | | | | | | | | | It dropped required functions for plugins with gnu ld 2.20 and 2.21. Failing Tests (1): LLVM :: Feature/load_module.ll Hello: bin/opt: symbol lookup error: lib/LLVMHello.so: undefined symbol: _ZN4llvm11raw_ostream13write_escapedENS_9StringRefEb Failing Tests (1): Clang :: Frontend/plugins.c error: unable to load plugin 'lib/PrintFunctionNames.so': 'lib/PrintFunctionNames.so: undefined symbol: _ZN5clang15PluginASTAction6anchorEv' I think we should inspect linker's version or behavior to introduce --gc-sections for --export-dynamic. llvm-svn: 220198
* [ARM] Do not select SMULW[BT] or SMLAW[BT]Oliver Stannard2014-10-203-30/+34
| | | | | | | | | | | | | | | | | | | The current instruction selection patterns for SMULW[BT] and SMLAW[BT] are incorrect. These instructions multiply a 32-bit and a 16-bit value (both signed) and return the top 32 bits of the 48-bit result. This preserves the 16 bits of overflow, whereas the patterns they currently match truncate the result to 16 bits then sign extend. To select these instructions, we would need to match an ISD::SMUL_LOHI, a sign extend, two shifts and an or. There is no way to match SMUL_LOHI in an instruction pattern as it defines multiple values, so this would have to be done in C++. I have raised http://llvm.org/bugs/show_bug.cgi?id=21297 to cover allowing correct selection of these instructions. This fixes http://llvm.org/bugs/show_bug.cgi?id=19396 llvm-svn: 220196
* [Thumb] Fix crash in Thumb1RegisterInfo::rewriteFrameIndexOliver Stannard2014-10-202-0/+20
| | | | | | | | | This function can, for some offsets from the SP, split one instruction into two. Since it re-uses the original instruction as the first instruction of the result, we need ensure its result register is not marked as dead before we use it in the second instruction. llvm-svn: 220194
* Switch the default DataLayout to be little endian, and make the variableChandler Carruth2014-10-202-9/+9
| | | | | | | | | be BigEndian so the default can continue to be zero-initialized. This is one of the prerequisites to making DataLayout a constant and always available part of every module. llvm-svn: 220193
* Remove some completely superfluous trailing comments and clang-formatChandler Carruth2014-10-201-53/+36
| | | | | | | this header to remove numerous formatting inconsistencies that impede making simple changes here without large diffs. llvm-svn: 220192
* Clean up the comments and doxygen for DataLayout.Chandler Carruth2014-10-201-96/+99
| | | | llvm-svn: 220191
* Fix a miscompile introduced in r220178.Chandler Carruth2014-10-202-4/+36
| | | | | | | | | | | | | | | | | | The original code had an implicit assumption that if the test for allocas or globals was reached, the two pointers were not equal. With my changes to make the pointer analysis more powerful here, I also had to guard against circumstances where the results weren't useful. That in turn violated the assumption and gave rise to a circumstance in which we could have a store with both the queried pointer and stored pointer rooted at *the same* alloca. Clearly, we cannot ignore such a store. There are other things we might do in this code to better handle the case of both pointers ending up at the same alloca or global, but it seems best to at least make the test explicit in what it intends to check. I've added tests for both the alloca and global case here. llvm-svn: 220190
* IR: Replace DataLayout::RoundUpAlignment with RoundUpToAlignmentDavid Majnemer2014-10-205-20/+11
| | | | | | No functional change intended, just cleaning up some code. llvm-svn: 220187
* Fix a somewhat subtle pair of issues with JumpThreading I introduced inChandler Carruth2014-10-202-3/+37
| | | | | | | | | | | | | | | r220178. First, the creation routine doesn't insert prior to the terminator of the basic block provided, but really at the end of the basic block. Instead, get the terminator and insert before that. The next issue was that we need to ensure multiple PHI node entries for a single predecessor re-use the same cast instruction rather than creating new ones. All of the logic here was without tests previously. I've reduced and added a test case from the test suite that crashed without both of these fixes. llvm-svn: 220186
* [PBQP] Use DenseSet rather than std::set for PBQP's PoolCostAllocatorLang Hames2014-10-203-67/+76
| | | | | | | | | implementation. This is good for a ~6% reduction in total compile time on the nightly test suite when running with -regalloc=pbqp. llvm-svn: 220183
* Teach the load analysis driving core instcombine logic and other bits ofChandler Carruth2014-10-204-23/+164
| | | | | | | | | | | | | | | | | | | logic to look through pointer casts, making them trivially stronger in the face of loads and stores with intervening pointer casts. I've included a few test cases that demonstrate the kind of folding instcombine can do without pointer casts and then variations which obfuscate the logic through bitcasts. Without this patch, the variations all fail to optimize fully. This is more important now than it has been in the past as I've started moving the load canonicialization to more closely follow the value type requirements rather than the pointer type requirements and thus this needs to be prepared for more pointer casts. When I made the same change to stores several test cases regressed without logic along these lines so I wanted to systematically improve matters first. llvm-svn: 220178
* Add a datalayout string to this test so that it exercises the full gamutChandler Carruth2014-10-201-13/+15
| | | | | | | | | | | | | of InstCombine rather than just the bits enabled when datalayout is optional. The primary fixes here are because now things are little endian. In good news, silliness like this seems like it will be going away as we've got pretty stong consensus on dropping optional datalayout entirely. llvm-svn: 220176
* Always use -Wl,-gc-sections on our build.Rafael Espindola2014-10-191-6/+9
| | | | | | | Both bfd ld and gold correctly handle --export-dynamic, so gc-sections is safe even for binaries that support plugins. llvm-svn: 220174
* [PowerPC] Clean up -mattr=+vsx tests to always specify -mcpuBill Schmidt2014-10-1911-31/+8
| | | | | | | | | | | | | | We recently discovered an issue that reinforces what a good idea it is to always specify -mcpu in our code generation tests, particularly for -mattr=+vsx. This patch ensures that all tests that specify -mattr=+vsx also specify -mcpu=pwr7 or -mcpu=pwr8, as appropriate. Some of the uses of -mattr=+vsx added recently don't make much sense (when specified for -mtriple=powerpc-apple-darwin8 or -march=ppc32, for example). For cases like this I've just removed the extra VSX test commands; there's enough coverage without them. llvm-svn: 220173
* [PowerPC] Temporarily disable VSX for PowerPC fast-isel testsBill Schmidt2014-10-195-8/+27
| | | | | | | | | | | | | | | Patch by Bill Seurer; some comment formatting changes by me. There are a few PowerPC test cases for FastISel support that currently fail with VSX support enabled. The temporary workaround under discussion in http://reviews.llvm.org/D5362 helps, but the tests still fail because they specify -fast-isel-abort, and the VSX workaround punts back to SelectionDAG. We have plans to fix FastISel permanently for VSX, but until that's in place these tests are preventing us from enabling VSX by default. Therefore we are adding -mattr=-vsx to these tests until the full support is ready. llvm-svn: 220172
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