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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-20 15:37:35 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-20 15:37:35 +0000 |
| commit | 6672f37ed2b3b1ab1bfc4f85619e454578481f39 (patch) | |
| tree | 859d47379f1166e64f73b071cdf50682cb0ae97b /llvm | |
| parent | c5d4bc7581486a204f34f326d259de3b049f7185 (diff) | |
| download | bcm5719-llvm-6672f37ed2b3b1ab1bfc4f85619e454578481f39.tar.gz bcm5719-llvm-6672f37ed2b3b1ab1bfc4f85619e454578481f39.zip | |
[Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M
These instructions are related to the v7[AR] exception model, and are
not defined on v7M.
llvm-svn: 220204
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 8 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/thumb2-exception-return-mclass.s | 15 |
2 files changed, 20 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index df034fc3ebe..7e5c9bcbe75 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -3757,7 +3757,8 @@ def t2DCPS3 : T2DCPS<0b11, "dcps3">; class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> - : T2I<oops, iops, itin, opc, asm, pattern> { + : T2I<oops, iops, itin, opc, asm, pattern>, + Requires<[IsThumb2,IsNotMClass]> { bits<5> mode; let Inst{31-25} = 0b1110100; let Inst{24-23} = Op; @@ -3788,7 +3789,8 @@ def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>; // Return From Exception is a system instruction. class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> - : T2I<oops, iops, itin, opc, asm, pattern> { + : T2I<oops, iops, itin, opc, asm, pattern>, + Requires<[IsThumb2,IsNotMClass]> { let Inst{31-20} = op31_20{11-0}; bits<4> Rn; @@ -3815,7 +3817,7 @@ let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary, "subs", "\tpc, lr, $imm", [(ARMintretflag imm0_255:$imm)]>, - Requires<[IsThumb2]> { + Requires<[IsThumb2,IsNotMClass]> { let Inst{31-8} = 0b111100111101111010001111; bits<8> imm; diff --git a/llvm/test/MC/ARM/thumb2-exception-return-mclass.s b/llvm/test/MC/ARM/thumb2-exception-return-mclass.s new file mode 100644 index 00000000000..21669b0dc65 --- /dev/null +++ b/llvm/test/MC/ARM/thumb2-exception-return-mclass.s @@ -0,0 +1,15 @@ +# RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s + + .text + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: srsdb sp, #7 + srsdb sp, #7 + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: rfeia r6 + rfeia r6 + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: subs pc, lr, #42 + subs pc, lr, #42 |
