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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-21 11:49:14 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-21 11:49:14 +0000 |
| commit | cdb8db8d3cd35111e149231cc6fb2bb7bae46cc8 (patch) | |
| tree | 51d3e176a8fc2b789c634544f7d5cc0aad6b2577 /llvm | |
| parent | c0126864a0fbcd78e9dcf02faec43891691b77d4 (diff) | |
| download | bcm5719-llvm-cdb8db8d3cd35111e149231cc6fb2bb7bae46cc8.tar.gz bcm5719-llvm-cdb8db8d3cd35111e149231cc6fb2bb7bae46cc8.zip | |
[ARM] NEON 32-bit scalar moves are also available in VFPv2
The 32-bit variants of the NEON scalar<->GPR move instructions are
also available in VFPv2. The 8- and 16-bit variants do require NEON.
Note that the checks in the test file are all -DAG because they are
checking a mixture of stdout and stderr, and the ordering is not
guaranteed.
llvm-svn: 220288
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 5 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/neon-mov-vfp.s | 32 |
2 files changed, 35 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 9f11c5bfffb..a0c627c3541 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -5437,7 +5437,7 @@ def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00, IIC_VMOVSI, "vmov", "32", "$R, $V$lane", [(set GPR:$R, (extractelt (v2i32 DPR:$V), imm:$lane))]>, - Requires<[HasNEON, HasFastVGETLNi32]> { + Requires<[HasVFP2, HasFastVGETLNi32]> { let Inst{21} = lane{0}; } // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td @@ -5505,7 +5505,8 @@ def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V), (ins DPR:$src1, GPR:$R, VectorIndex32:$lane), IIC_VMOVISL, "vmov", "32", "$V$lane, $R", [(set DPR:$V, (insertelt (v2i32 DPR:$src1), - GPR:$R, imm:$lane))]> { + GPR:$R, imm:$lane))]>, + Requires<[HasVFP2]> { let Inst{21} = lane{0}; // This instruction is equivalent as // $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm) diff --git a/llvm/test/MC/ARM/neon-mov-vfp.s b/llvm/test/MC/ARM/neon-mov-vfp.s new file mode 100644 index 00000000000..6ee6bfda436 --- /dev/null +++ b/llvm/test/MC/ARM/neon-mov-vfp.s @@ -0,0 +1,32 @@ +@ RUN: not llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK +@ RUN: not llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK + +@ The 32-bit variants of the NEON scalar move instructions are also available +@ to any core with VFPv2 + +@ CHECK-DAG: vmov.32 d13[0], r6 @ encoding: +@ CHECK-DAG: vmov.32 d17[1], r9 @ encoding: +vmov.32 d13[0], r6 +vmov.32 d17[1], r9 + +@ VFP-DAG: error: instruction requires: NEON +@ VFP-DAG: error: instruction requires: NEON +@ NEON-DAG: vmov.8 d22[5], r2 @ encoding: +@ NEON-DAG: vmov.16 d3[2], r4 @ encoding: +vmov.8 d22[5], r2 +vmov.16 d3[2], r4 + +@ CHECK-DAG: vmov.32 r6, d13[0] @ encoding: +@ CHECK-DAG: vmov.32 r9, d17[1] @ encoding: +vmov.32 r6, d13[0] +vmov.32 r9, d17[1] + +@ VFP-DAG: error: instruction requires: NEON +@ VFP-DAG: error: instruction requires: NEON +@ NEON-DAG: vmov.s8 r2, d22[5] @ encoding: +@ NEON-DAG: vmov.u16 r4, d3[2] @ encoding: +vmov.s8 r2, d22[5] +vmov.u16 r4, d3[2] + |
