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* ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach2011-10-032-4/+15
| | | | llvm-svn: 141038
* Fix typo in comments.Nick Lewycky2011-10-031-2/+2
| | | | llvm-svn: 141032
* Check-pointing the new SjLj EH lowering.Bill Wendling2011-10-032-0/+77
| | | | | | | | | | | This code will replace the version in ARMAsmPrinter.cpp. It creates a new machine basic block, which is the dispatch for the return from a longjmp call. It then shoves the address of that machine basic block into the correct place in the function context so that the EH runtime will jump to it directly instead of having to go through a compare-and-jump-to-the-dispatch bit. This should be more efficient in the common case. llvm-svn: 141031
* Move CHECK after entry label.Akira Hatanaka2011-10-031-2/+2
| | | | llvm-svn: 141030
* Add support for 64-bit logical NOR.Akira Hatanaka2011-10-032-0/+15
| | | | llvm-svn: 141029
* Add support for 64-bit count leading ones and zeros instructions.Akira Hatanaka2011-10-032-0/+32
| | | | llvm-svn: 141028
* Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling2011-10-031-31/+33
| | | | | | the need for returning a std::pair. llvm-svn: 141026
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-034-2/+22
| | | | llvm-svn: 141025
* Add support for 64-bit divide instructions.Akira Hatanaka2011-10-034-3/+50
| | | | llvm-svn: 141024
* Add C api for Instruction->eraseFromParent().Devang Patel2011-10-032-0/+5
| | | | llvm-svn: 141023
* Update test for 141010.Jim Grosbach2011-10-031-1/+1
| | | | llvm-svn: 141022
* Thumb2 ADD/SUB can take SP as a destination register.Jim Grosbach2011-10-031-18/+18
| | | | | | | It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. llvm-svn: 141020
* Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integerAkira Hatanaka2011-10-031-51/+44
| | | | | | registers. llvm-svn: 141019
* Add support for 64-bit integer multiply instructions.Akira Hatanaka2011-10-033-4/+39
| | | | llvm-svn: 141017
* Add definitions of instructions which move values between 64-bit integerAkira Hatanaka2011-10-032-0/+27
| | | | | | | registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions of the instructions. llvm-svn: 141015
* Find the strip tool that works with the specified SDKROOT. rdar://10165908Bob Wilson2011-10-031-4/+10
| | | | llvm-svn: 141013
* Tidy up a bit. Formatting.Jim Grosbach2011-10-031-62/+76
| | | | llvm-svn: 141010
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-037-1/+93
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
* Whitespace.Eric Christopher2011-10-031-1/+1
| | | | llvm-svn: 141005
* Typo.Eric Christopher2011-10-031-1/+1
| | | | llvm-svn: 141004
* Add the returns_twice attribute to LLVM.Rafael Espindola2011-10-039-9/+15
| | | | llvm-svn: 141001
* Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to ↵Craig Topper2011-10-033-0/+9
| | | | | | registers xmm8-xmm15 outside 64-bit mode. llvm-svn: 140997
* Test updates that were supposed to go with r140993.Craig Topper2011-10-031-4/+4
| | | | llvm-svn: 140994
* Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.Craig Topper2011-10-031-9/+13
| | | | llvm-svn: 140993
* Reapply r140979 with fix! We never did get a testcase, but careful review of theNick Lewycky2011-10-032-4/+43
| | | | | | logic by David Meyer revealed this bug. llvm-svn: 140992
* attempt to fix ocaml bindings: landing padsTorok Edwin2011-10-034-4/+40
| | | | llvm-svn: 140991
* Revert r140979 due to reports of bootstrap failure.Nick Lewycky2011-10-032-36/+4
| | | | llvm-svn: 140980
* Add one more case we compute a max trip count.Nick Lewycky2011-10-032-4/+36
| | | | llvm-svn: 140979
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-025-32/+215
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. llvm-svn: 140974
* Special case disassembler handling of REX.B prefix on NOP instruction to ↵Craig Topper2011-10-022-2/+42
| | | | | | decode as XCHG R8D, EAX instead. Fixes PR10344. llvm-svn: 140971
* Add a new icmp+select optz'n. Also shows off the load(cst) folding added inNick Lewycky2011-10-022-0/+16
| | | | | | r140966. llvm-svn: 140969
* Enhance a couple places where we were doing constant folding of instructions,Nick Lewycky2011-10-022-7/+8
| | | | | | but not load instructions. Noticed by inspection. llvm-svn: 140966
* Fix typo in r140954.Craig Topper2011-10-021-1/+0
| | | | llvm-svn: 140962
* Make canonicalization of ImmutableSetRef::asImmutableSet() semi-explicit.Ted Kremenek2011-10-021-2/+3
| | | | llvm-svn: 140959
* Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper2011-10-014-2/+21
| | | | llvm-svn: 140955
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-015-6/+36
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."Chad Rosier2011-10-013-27/+7
| | | | | | to appease nightly testers. Not quite there yet. llvm-svn: 140953
* Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem2011-10-011-10/+10
| | | | | | of the type. Formatted lines to the 80 char limit. llvm-svn: 140952
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-0177-241/+369
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* No one should be using the method directly. Assert if they do.Bill Wendling2011-10-011-12/+1
| | | | llvm-svn: 140947
* Add a convenience method to tell if two things are equal.Bill Wendling2011-10-012-16/+10
| | | | llvm-svn: 140946
* Use the ARMConstantPoolMBB class to handle the MBB values.Bill Wendling2011-10-014-36/+13
| | | | llvm-svn: 140943
* Add ARMConstantPoolMBB to hold an MBB value in the constant pool.Bill Wendling2011-10-012-1/+90
| | | | llvm-svn: 140942
* Remove dead code.Bill Wendling2011-10-012-14/+0
| | | | llvm-svn: 140941
* Remove now dead methods and ivar.Bill Wendling2011-10-012-34/+12
| | | | llvm-svn: 140940
* Use the new ARMConstantPoolSymbol class to handle external symbols.Bill Wendling2011-10-016-14/+27
| | | | llvm-svn: 140939
* Add an ARMConstantPool class for external symbols. This will split out the ↵Bill Wendling2011-10-012-5/+118
| | | | | | support for external symbols from the base class. llvm-svn: 140938
* Remove now dead methods and ivar from ARMConstantPoolValue.Bill Wendling2011-10-012-38/+3
| | | | llvm-svn: 140937
* Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling2011-10-016-34/+39
| | | | | | and block addresses. llvm-svn: 140936
* Some more refactoring.Bill Wendling2011-10-012-6/+78
| | | | | | | | * Add a couple of Create methods to the ARMConstantPoolConstant class, * Add its own version of getExistingMachineCPValue, and * Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant. llvm-svn: 140935
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