Add support for 64-bit count leading ones and zeros instructions.

llvm-svn: 141028

2 files changed, 32 insertions, 0 deletions

diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index 60fc40ca617..3f52e9ebfd3 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -116,6 +116,15 @@ class MoveToLOHI64<bits<6> func, string instr_asm>:
      !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
 }
 
+// Count Leading Ones/Zeros in Word
+class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
+  FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
+     !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
+     Requires<[HasBitCount]> {
+  let shamt = 0;
+  let rt = rd;
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction definition
 //===----------------------------------------------------------------------===//
@@ -168,6 +177,12 @@ let Uses = [HI64] in
 let Uses = [LO64] in
   def MFLO64  : MoveFromLOHI64<0x12, "mflo">;
 
+/// Count Leading
+def DCLZ : CountLeading64<0x24, "dclz",
+                          [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
+def DCLO : CountLeading64<0x25, "dclo",
+                          [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/Mips/mips64instrs.ll b/llvm/test/CodeGen/Mips/mips64instrs.ll
index b2aa3ecc02d..16bca0fbbf7 100644
--- a/llvm/test/CodeGen/Mips/mips64instrs.ll
+++ b/llvm/test/CodeGen/Mips/mips64instrs.ll
@@ -116,3 +116,20 @@ entry:
   ret i64 %rem
 }
 
+declare i64 @llvm.ctlz.i64(i64) nounwind readnone
+
+; CHECK: dclz $2, $4
+define i64 @f18(i64 %X) nounwind readnone {
+entry:
+  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X)
+  ret i64 %tmp1
+}
+
+; CHECK: dclo $2, $4
+define i64 @f19(i64 %X) nounwind readnone {
+entry:
+  %neg = xor i64 %X, -1
+  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg)
+  ret i64 %tmp1
+}
+