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* [DWARF] Support for DW_FORM_strx3 and complete support for DW_FORM_strx{1,2,4}Wolfgang Pieb2017-06-216-13/+148
| | | | | | | | | | (consumer). Reviewer: aprantl Differential Revision: https://reviews.llvm.org/D34418 llvm-svn: 305944
* [Hexagon] Handle more types of immediate operands in expand-condsetsKrzysztof Parzyszek2017-06-212-2/+35
| | | | llvm-svn: 305943
* [InstCombine] Cleanup using commutable matchers. Make a couple helper ↵Craig Topper2017-06-212-25/+19
| | | | | | methods standalone static functions. Put 'if' around variable declaration instead of after. NFC llvm-svn: 305941
* Add a "probe-stack" attributewhitequark2017-06-214-0/+41
| | | | | | | | | | | | | This attribute is used to ensure the guard page is triggered on stack overflow. Stack frames larger than the guard page size will generate a call to __probestack to touch each page so the guard page won't be skipped. Reviewed By: majnemer Differential Revision: https://reviews.llvm.org/D34386 llvm-svn: 305939
* [BasicAA] Use MayAlias instead of PartialAlias for fallback.Michael Kruse2017-06-2113-87/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using various methods, BasicAA tries to determine whether two GetElementPtr memory locations alias when its base pointers are known to be equal. When none of its heuristics are applicable, it falls back to PartialAlias to, according to a comment, protect TBAA making a wrong decision in case of unions and malloc. PartialAlias is not correct, because a PartialAlias result implies that some, but not all, bytes overlap which is not necessarily the case here. AAResults returns the first analysis result that is not MayAlias. BasicAA is always the first alias analysis. When it returns PartialAlias, no other analysis is queried to give a more exact result (which was the intention of returning PartialAlias instead of MayAlias). For instance, ScopedAA could return a more accurate result. The PartialAlias hack was introduced in r131781 (and re-applied in r132632 after some reverts) to fix llvm.org/PR9971 where TBAA returns a wrong NoAlias result due to a union. A test case for the malloc case mentioned in the comment was not provided and I don't think it is affected since it returns an omnipotent char anyway. Since r303851 (https://reviews.llvm.org/D33328) clang does emit specific TBAA for unions anymore (but "omnipotent char" instead). Hence, the PartialAlias workaround is not required anymore. This patch passes the test-suite and check-llvm/check-clang of a self-hoisted build on x64. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D34318 llvm-svn: 305938
* Object: Have the irsymtab builder take a string table builder. NFCI.Peter Collingbourne2017-06-212-19/+23
| | | | | | | | | This will be needed in order to share the irsymtab string table with the bitcode string table. Differential Revision: https://reviews.llvm.org/D33971 llvm-svn: 305937
* [CGP, memcmp] replace CreateZextOrTrunc with CreateZext because it can never ↵Sanjay Patel2017-06-211-5/+7
| | | | | | trunc llvm-svn: 305936
* [CGP] fix variables to be unsigned in memcmp expansionSanjay Patel2017-06-211-12/+14
| | | | llvm-svn: 305935
* Do not inline recursive direct calls in sample loader pass.Dehao Chen2017-06-213-0/+22
| | | | | | | | | | | | | | Summary: r305009 disables recursive inlining for indirect calls in sample loader pass. The same logic applies to direct recursive calls. Reviewers: iteratee, davidxl Reviewed By: iteratee Subscribers: sanjoy, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D34456 llvm-svn: 305934
* [PDB] Add symbols to the PDBReid Kleckner2017-06-213-8/+167
| | | | | | | | | | | | | | | | | | | Summary: The main complexity in adding symbol records is that we need to "relocate" all the type indices. Type indices do not have anything like relocations, an opaque data structure describing where to find existing type indices for fixups. The linker just has to "know" where the type references are in the symbol records. I added an overload of `discoverTypeIndices` that works on symbol records, and it seems to be able to link the standard library. Reviewers: zturner, ruiu Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D34432 llvm-svn: 305933
* [PowerPC] define target hook isReallyTriviallyReMaterializable()Lei Huang2017-06-214-2/+208
| | | | | | | | | | | Define target hook isReallyTriviallyReMaterializable() to explicitly specify PowerPC instructions that are trivially rematerializable. This will allow the MachineLICM pass to accurately identify PPC instructions that should always be hoisted. Differential Revision: https://reviews.llvm.org/D34255 llvm-svn: 305932
* [x86] set the datalayout to match the RUN line triple; NFCSanjay Patel2017-06-211-4/+2
| | | | | | | I don't think there's any visible difference from having the wrong layout for the 32-bit case at this point, but that could change in the future. llvm-svn: 305931
* [InstCombine] Add range metadata to cttz/ctlz/ctpop intrinsic calls based on ↵Craig Topper2017-06-213-18/+108
| | | | | | | | | | | | | | | | | | | | | known bits Summary: I noticed that passing known bits across these intrinsics isn't great at capturing the information we really know. Turning known bits of the input into known bits of a count output isn't able to convey a lot of what we really know. This patch adds range metadata to these intrinsics based on the known bits. Currently the patch punts if we already have range metadata present. Reviewers: spatel, RKSimon, davide, majnemer Reviewed By: RKSimon Subscribers: sanjoy, hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D32582 llvm-svn: 305927
* [InstCombine] Don't let folding (select (icmp eq (and X, C1), 0), Y, (or Y, ↵Craig Topper2017-06-212-40/+39
| | | | | | | | | | | | | | | | | | | C2)) create more instructions than it removes Summary: Previously this folding had no checks to see if it was going to result in less instructions. This was pointed out during the review of D34184 This patch adds code to count how many instructions its going to create vs how many its going to remove so we can make a proper decision. Reviewers: spatel, majnemer Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34437 llvm-svn: 305926
* [Reassociate] Support xor reassociating for splat vectorsCraig Topper2017-06-212-24/+123
| | | | | | | | | | | | | | Summary: This patch adds support for xors of splat vectors. Reviewers: mcrosier Reviewed By: mcrosier Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34354 llvm-svn: 305925
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-215-11/+1758
| | | | | | | | | | See Bug 33509: https://bugs.llvm.org//show_bug.cgi?id=33509 Reviewers: Sam Kolton, Artem Tamazov, Valery Pykhtin Differential Revision: https://reviews.llvm.org/D34360 llvm-svn: 305923
* [DAG] Move BaseIndexOffset into separate Libarary. NFC.Nirav Dave2017-06-214-114/+161
| | | | | | | Move BaseIndexOffset analysis out of DAGCombiner for use in other files. llvm-svn: 305921
* ClangFormat some changes from r305226David Blaikie2017-06-211-2/+4
| | | | | | Post commit review feedback from Justin Bogner llvm-svn: 305919
* [AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.Christof Douma2017-06-211-0/+683
| | | | | | | | | | | | Added test file for ARMv8.1 LSE Atomics that I forgot to include in commit r305893. Patch by Ananth Jasty. Differential Revision: https://reviews.llvm.org/D33586 Change-Id: Ic1ad8ed87c1b584c4c791b459a686c866a3c3087 llvm-svn: 305918
* [DAG] Remove Node csonstruction from BaseIndexOffset match. NFCI.Nirav Dave2017-06-211-52/+69
| | | | | | | | Move GlobalAddress Offset decomposition from initial match into comparision check and removing the possibility of constructing a new offseted global address when examining addresses. llvm-svn: 305917
* [X86][SSE] Dropped -mcpu from 256-bit vector shuffle testsSimon Pilgrim2017-06-214-20/+12
| | | | | | Use triple and attribute only for consistency llvm-svn: 305916
* [AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is ↵Dmitry Preobrazhensky2017-06-216-14/+117
| | | | | | | | | | | | different than any of the src See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D34003 llvm-svn: 305915
* [x86] fix formatting; NFCSanjay Patel2017-06-211-15/+13
| | | | llvm-svn: 305914
* [X86][SSE] Dropped -mcpu from 128-bit vector shuffle testsSimon Pilgrim2017-06-214-38/+26
| | | | | | Use triple and attribute only for consistency llvm-svn: 305913
* [X86][SSE] Regenerate merge store testsSimon Pilgrim2017-06-211-15/+17
| | | | llvm-svn: 305910
* [X86][SSE] Dropped -mcpu from vector blend shuffle tests and regenerateSimon Pilgrim2017-06-211-54/+20
| | | | | | Use triple and attribute only for consistency llvm-svn: 305909
* [X86][SSE] Dropped -mcpu from vector shuffle testsSimon Pilgrim2017-06-214-14/+24
| | | | | | Use triple and attribute only for consistency llvm-svn: 305908
* [X86][SSE] Dropped -mcpu from vector zero extend testsSimon Pilgrim2017-06-211-7/+5
| | | | | | Use triple and attribute only for consistency llvm-svn: 305907
* [X86][SSE] Dropped -mcpu from variable shuffle testsSimon Pilgrim2017-06-212-8/+7
| | | | | | Use triple and attribute only for consistency llvm-svn: 305906
* [X86][AVX] Add AVX1 shuffle truncation testsSimon Pilgrim2017-06-211-107/+234
| | | | llvm-svn: 305905
* [X86][SSE] Add SSE2/SSE42 shuffle truncation testsSimon Pilgrim2017-06-211-0/+156
| | | | llvm-svn: 305904
* [X86] Rerun the update_llc_test_checks tool on test. NFC.Zvi Rackover2017-06-211-0/+8
| | | | llvm-svn: 305897
* Fix build after r305892Pavel Labath2017-06-211-0/+1
| | | | | | Make sure to #include <cerrno> in Support/Errno.h llvm-svn: 305895
* [AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.Christof Douma2017-06-214-5/+114
| | | | | | | | | | | | | | | | | | | | | | Implemented support to AArch64 codegen for ARMv8.1 Large System Extensions atomic instructions. Where supported, these instructions can provide atomic operations with higher performance. Currently supported operations include: fetch_add, fetch_or, fetch_xor, fetch_smin, fetch_min/max (signed and unsigned), swap, and compare_exchange. This implementation implies sequential-consistency ordering, more relaxed ordering is under development. Subtarget->hasLSE is currently supported for Cavium ThunderX2T99. Patch by Ananth Jasty. Differential Revision: https://reviews.llvm.org/D33586 Change-Id: I82f6d3d64255622791ceb0715b7ab9f4dc4d4b2c llvm-svn: 305893
* [Support] Add RetryAfterSignal helper functionPavel Labath2017-06-216-25/+59
| | | | | | | | | | | | | | | | | | | | | Summary: This function retries an operation if it was interrupted by a signal (failed with EINTR). It's inspired by the TEMP_FAILURE_RETRY macro in glibc, but I've turned that into a template function. I've also added a fail-value argument, to enable the function to be used with e.g. fopen(3), which is documented to fail for any reason that open(2) can fail (which includes EINTR). The main user of this function will be lldb, but there were also a couple of uses within llvm that I could simplify using this function. Reviewers: zturner, silvas, joerg Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D33895 llvm-svn: 305892
* [AArch64] Add early exit to promoteLoadFromStore.Florian Hahn2017-06-211-1/+4
| | | | | | | | There should be at most a single kill flag for the promoted operand between the store/load pair. Discussed in https://reviews.llvm.org/D34402. llvm-svn: 305889
* [MIPS] Fix for selecting of DINS/INS instructionStrahinja Petrovic2017-06-212-6/+38
| | | | | | | | | | This patch adds one more condition in selection DINS/INS instruction, which fixes MultiSource/Applications/JM/ldecod/ for mips32r2 (and mips64r2 n32 abi). Differential Revision: https://reviews.llvm.org/D33725 llvm-svn: 305888
* Use range-loop in machine-scheduler. NFCI.Javed Absar2017-06-211-94/+72
| | | | | | | | | | | | Converts to range-loop usage in machine scheduler. This makes the code neater and easier to read, and also keeps pace of the machine scheduler implementation with C++11 features. Reviewed by: Matthias Braun Differential Revision: https://reviews.llvm.org/D34320 llvm-svn: 305887
* [AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton2017-06-2115-281/+323
| | | | | | | | | | | | Summary: Previously there were two separate pseudo instruction for SDWA on VI and on GFX9. Created one pseudo instruction that is union of both of them. Added verifier to check that operands conform either VI or GFX9. Reviewers: dp, arsenm, vpykhtin Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, artem.tamazov Differential Revision: https://reviews.llvm.org/D34026 llvm-svn: 305886
* [AArch64] Preserve register flags when promoting a load from store.Florian Hahn2017-06-212-4/+23
| | | | | | | | | | | | | | | | | | | | | Summary: This patch updates promoteLoadFromStore to use the store MachineOperand as the source operand of the of the new instruction instead of creating a new register MachineOperand. This way, the existing register flags are preserved. This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468). Reviewers: MatzeB, t.p.northover, junbuml Reviewed By: MatzeB Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34402 llvm-svn: 305885
* [DAGCombiner] Add another combine from build vector to shuffleGuy Blank2017-06-213-37/+18
| | | | | | | Add support for combining a build vector to a shuffle. When the build vector is of extracted elements from 2 vectors (vec1, vec2) where vec2 is 2 times smaller than vec1. llvm-svn: 305883
* [SCEV] Make MulOpsInlineThreshold lower to avoid excessive compilation timeMax Kazantsev2017-06-212-1/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MulOpsInlineThreshold option of SCEV is defaulted to 1000, which is inadequately high. When constructing SCEVs of expressions like: x1 = a * a x2 = x1 * x1 x3 = x2 * x2 ... We actually have huge SCEVs with max allowed amount of operands inlined. Such expressions are easy to get from unrolling of loops looking like x = a for (i = 0; i < n; i++) x = x * x Or more tricky cases where big powers are involved. If some non-linear analysis tries to work with a SCEV that has 1000 operands, it may lead to excessively long compilation. The attached test does not pass within 1 minute with default threshold. This patch decreases its default value to 32, which looks much more reasonable if we use analyzes with complexity O(N^2) or O(N^3) working with SCEV. Differential Revision: https://reviews.llvm.org/D34397 llvm-svn: 305882
* Simplify test.Rafael Espindola2017-06-211-40/+8
| | | | llvm-svn: 305881
* [XRay] Reduce synthetic references emitted by XRayDean Michael Berris2017-06-219-55/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When we're building with XRay instrumentation, we use a trick that preserves references from the function to a function sled index. This index table lives in a separate section, and without this trick the linker is free to garbage-collect this section and all the segments it refers to. Until we're able to tell the linkers to preserve these sections, we use this reference trick to keep around both the index and the entries in the instrumentation map. Before this change we emitted both a synthetic reference to the label in the instrumentation map, and to the entry in the function map index. This change removes the first synthetic reference and only emits one synthetic reference to the index -- the index entry has the references to the labels in the instrumentation map, so the linker will still preserve those if the function itself is preserved. This reduces the amount of synthetic references we emit from 16 bytes to just 8 bytes in x86_64, and similarly to other platforms. Reviewers: dblaikie Subscribers: javed.absar, kpw, pelikan, llvm-commits Differential Revision: https://reviews.llvm.org/D34340 llvm-svn: 305880
* [ImplicitNullChecks] Uphold an invariant in areMemoryOpsAliasedSerguei Katkov2017-06-212-24/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now areMemoryOpsAliased has an assertion justified as: MMO1 should have a value due it comes from operation we'd like to use as implicit null check. assert(MMO1->getValue() && "MMO1 should have a Value!"); However, it is possible for that invariant to not be upheld in the following situation (conceptually): Null check %RAX NotNullSucc: %RAX = LEA %RSP, 16 // I0 %RDX = MOV64rm %RAX // I1 With the current code, we will have an early exit from ImplicitNullChecks::isSuitableMemoryOp on I0 with SR_Unsuitable. However, I1 will look plausible (since it loads from %RAX) and will go ahead and call areMemoryOpsAliased(I1, I0). This will cause us to fail the assert mentioned above since I1 does not load from an IR level value and thus is allowed to have a non-Value base address. The fix is to bail out earlier whenever we see an unsuitable instruction overwrite PointerReg. This would guarantee that when we call areMemoryOpsAliased, we're guaranteed to be looking at an instruction that loads from or stores to an IR level value. Original Patch Author: sanjoy Reviewers: sanjoy, mkazantsev, reames Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34385 llvm-svn: 305879
* [NewGVN] Fix a bug that made the store verifier less effective.Davide Italiano2017-06-201-6/+4
| | | | | | | | | We weren't actually checking for duplicated stores, as the condition was always actually false. This was found by Coverity, and I have no clue how to trigger this in real-world code (although I tried for a bit). llvm-svn: 305867
* Updated llvm-objdump with Mach-O files and the -objc-meta-data option soKevin Enderby2017-06-202-2/+8
| | | | | | | | that it symbolically prints the superclass when it has dyld bind info for it. rdar://7638823 llvm-svn: 305866
* clang-format a region.Rafael Espindola2017-06-201-20/+19
| | | | | | It will make a followup patch easier to read. llvm-svn: 305865
* Add a cantFail overload for Expected-reference (Expected<T&>) types.Lang Hames2017-06-202-0/+25
| | | | llvm-svn: 305863
* [codeview] YAMLize all section offsets and indices in symbol recordsReid Kleckner2017-06-203-25/+62
| | | | | | | | | | | | We forgot to serialize these because llvm-readobj didn't dump them. They are typically all zeros in an object file. The linker fills them in with relocations before adding them to the PDB. Now we can properly round trip these symbols through pdb2yaml -> yaml2pdb. I made these fields optional with a zero default so that we can elide them from our test cases. llvm-svn: 305857
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