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| author | Florian Hahn <florian.hahn@arm.com> | 2017-06-21 08:47:23 +0000 |
|---|---|---|
| committer | Florian Hahn <florian.hahn@arm.com> | 2017-06-21 08:47:23 +0000 |
| commit | 80e485179e767c95de7de18fc44a82bcfab1c579 (patch) | |
| tree | c196aa5ecd84bbda543c96ea2a0a8a34ed7dbc84 /llvm | |
| parent | 52d73fce8568f69832f3eb06d2ddff7a771f2224 (diff) | |
| download | bcm5719-llvm-80e485179e767c95de7de18fc44a82bcfab1c579.tar.gz bcm5719-llvm-80e485179e767c95de7de18fc44a82bcfab1c579.zip | |
[AArch64] Preserve register flags when promoting a load from store.
Summary:
This patch updates promoteLoadFromStore to use the store MachineOperand as the
source operand of the of the new instruction instead of creating a new
register MachineOperand. This way, the existing register flags are
preserved.
This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468).
Reviewers: MatzeB, t.p.northover, junbuml
Reviewed By: MatzeB
Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34402
llvm-svn: 305885
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/ldst-opt.mir | 20 |
2 files changed, 23 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index 9243eb91cc1..c35de77727e 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -795,6 +795,7 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI, int LoadSize = getMemScale(*LoadI); int StoreSize = getMemScale(*StoreI); unsigned LdRt = getLdStRegOp(*LoadI).getReg(); + const MachineOperand &StMO = getLdStRegOp(*StoreI); unsigned StRt = getLdStRegOp(*StoreI).getReg(); bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt); @@ -819,7 +820,7 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI, BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(), TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt) .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR) - .addReg(StRt) + .add(StMO) .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); } else { // FIXME: Currently we disable this transformation in big-endian targets as @@ -860,14 +861,14 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI, BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(), TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri), DestReg) - .addReg(StRt) + .add(StMO) .addImm(AndMaskEncoded); } else { BitExtMI = BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(), TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri), DestReg) - .addReg(StRt) + .add(StMO) .addImm(Immr) .addImm(Imms); } diff --git a/llvm/test/CodeGen/AArch64/ldst-opt.mir b/llvm/test/CodeGen/AArch64/ldst-opt.mir index f7641d3ffd0..5b3576d898e 100644 --- a/llvm/test/CodeGen/AArch64/ldst-opt.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt.mir @@ -34,7 +34,7 @@ body: | # Don't count transient instructions towards search limits. # CHECK-LABEL: name: promote-load-from-store # CHECK: STRWui %w1 -# CHECK: UBFMWri %w1 +# CHECK: UBFMWri killed %w1 --- name: store-pair tracksRegLiveness: true @@ -144,3 +144,21 @@ body: | # CHECK: %wzr = COPY %w1 # CHECK: %w11 = ORRWrs %wzr, %w1, 0 # CHECK: HINT 0, implicit %w11 +--- +name: promote-load-from-store-undef +tracksRegLiveness: true +body: | + bb.0: + liveins: %x0, %x2, %lr + + STRWui undef %w1, %x0, 0 :: (store 4) + %w0 = LDRBBui %x0, 1 :: (load 2) + STRHHui undef %w3, %x2, 0 :: (store 4) + %w1 = LDRBBui %x2, 0 :: (load 4) + RET %lr, implicit %w0 +... +# CHECK-LABEL: name: promote-load-from-store-undef +# CHECK: STRWui undef %w1 +# CHECK: UBFMWri undef %w1 +# CHECK: STRHHui undef %w3 +# CHECK: ANDWri undef %w3 |
