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* [IR] Split Intrinsics.inc into enums and implementationsReid Kleckner2018-06-233-30/+53
| | | | | | | | | | | | | | | | | | | Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
* TableGen/SearchableTables: Support more generic enums and tablesNicolai Haehnle2018-06-211-201/+634
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is essentially a rewrite of the backend which introduces TableGen base classes GenericEnum, GenericTable, and SearchIndex. They allow generating custom enums and tables with lookup functions using separately defined records as the underlying database. Also added as part of this change: - Lookup functions may use indices composed of multiple fields. - Instruction fields are supported similar to Intrinsic fields. - When the lookup key has contiguous numeric values, the lookup function will directly index into the table instead of using a binary search. The existing SearchableTable functionality is internally mapped to the new primitives. Change-Id: I444f3490fa1dbfb262d7286a1660a2c4308e9932 Reviewers: arsenm, tra, t.p.northover Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D48013 llvm-svn: 335225
* [X86] Add the ability to force an EVEX2VEX mapping table entry from the .td ↵Craig Topper2018-06-191-71/+30
| | | | | | | | | | | | | | files. Remove remaining manual table entries from the tablegen emitter. This adds an EVEX2VEXOverride string to the X86 instruction class in X86InstrFormats.td. If this field is set it will add manual entry in the EVEX->VEX tables that doesn't check the encoding information. Then use this mechanism to map VMOVDU/A8/16, 128-bit VALIGN, and VPSHUFF/I instructions to VEX instructions. Finally, remove the manual table from the emitter. This has the bonus of fully sorting the autogenerated EVEX->VEX tables by their EVEX instruction enum value. We may be able to use this to do a binary search for the conversion and get rid of the need to create a DenseMap. llvm-svn: 335018
* [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have ↵Craig Topper2018-06-193-80/+42
| | | | | | | | | | | | | | VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. EVEX makes heavy use of the VEX.W bit to indicate 64-bit element vs 32-bit elements. Many of the VEX instructions were split into 2 versions with different masking granularity. The EVEX->VEX table generate can collapse the two versions if the VEX version uses is tagged as VEX_WIG. But if the VEX version is instead marked VEX.W==0 we can't combine them because we don't know if there is also a VEX version with VEX.W==1. This patch adds a new VEX_W1X tag that indicates the EVEX instruction encodes with VEX.W==1, but is safe to convert to a VEX instruction with VEX.W==0. This allows us to remove a bunch of manual EVEX->VEX table entries. We may want to look into splitting up the VEX_WPrefix field which would simplify the disassembler. llvm-svn: 335017
* [X86] Encode the EVEX2VEX exception list information in .td files instead of ↵Craig Topper2018-06-181-26/+2
| | | | | | | | the emitter source. Rather than having an exclusion list in tablegen sources, add a flag to the X86 instruction records that can be used to suppress checking for convertibility. llvm-svn: 334971
* [TableGen] Make TiedAsmOperandTable in the AsmMatcher 'static' since its at ↵Craig Topper2018-06-181-2/+2
| | | | | | file scope. llvm-svn: 334957
* [TableGen] Remove unused member variable.Craig Topper2018-06-181-14/+0
| | | | | | I think this became unused after r324196. llvm-svn: 334956
* [TableGen][AsmMatcherEmitter] Allow tied operands of different classes in ↵Sander de Smalen2018-06-182-27/+61
| | | | | | | | | | | | | | | | | | | | | | aliases. Allow a tied operand of a different operand class in InstAliases, so that the operand can be printed (and added to the MC instruction) as the appropriate register. For example, 'GPR64as32', which would be printed/parsed as a 32bit register and should match a tied 64bit register operand, where the former is a sub-register of the latter. This patch also generalizes the constraint checking to an overrideable method in MCTargetAsmParser, so that target asmparsers can specify whether a given operand satisfies the tied register constraint. Reviewers: olista01, rengolin, fhahn, SjoerdMeijer, samparker, dsanders, craig.topper Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47714 llvm-svn: 334942
* [TableGen] Prevent double flattening of InstAlias asm strings in the asm ↵Craig Topper2018-06-184-14/+13
| | | | | | | | | | | | matcher emitter. Unlike CodeGenInstruction, CodeGenInstAlias was flatting asm strings in its constructor. For instructions it was the users responsibility to flatten the string. AsmMatcherEmitter didn't know this and treated them the same. This caused double flattening of InstAliases. This is mostly harmless unless the desired assembly string contains curly braces. The second flattening wouldn't know to ignore these and would remove the curly braces. And for variant 1 it would remove the contents of them as well. To mitigate this, this patch makes removes the flattening from the CodeGenIntAlias constructor and modifies AsmWriterEmitter to account for the flattening not having been done. llvm-svn: 334919
* [X86] More additions to the load folding tables based on the autogenerated ↵Craig Topper2018-06-161-4/+6
| | | | | | | | tables. Including more additions for NotMemoryFoldable to remove some entries from the autogenerated table. llvm-svn: 334898
* [globalisel][tablegen] Add support for C++ predicates on PatFrags and use it ↵Daniel Sanders2018-06-153-20/+115
| | | | | | | | | | | | | | | | | | | | | to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
* [X86] Add 'Z' to the internal names of various EVEX instructions for overall ↵Craig Topper2018-06-151-8/+8
| | | | | | consistency. llvm-svn: 334785
* Revert r334764, as it breaks some botsFlorian Hahn2018-06-146-502/+503
| | | | llvm-svn: 334767
* [TableGen] Make TreePatternNode::getChild return a reference (NFC)Florian Hahn2018-06-146-503/+502
| | | | | | | | The return value of TreePatternNode::getChild is never null. This patch also updates various places that use return values of getChild to also use references. Those changes were suggested post-commit for D47463. llvm-svn: 334764
* [TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).Florian Hahn2018-06-141-21/+21
| | | | | | Those changes were suggested post-commit for D47463. llvm-svn: 334706
* [TableGen] Make getOnlyTree return a const ref (NFC)Florian Hahn2018-06-132-9/+11
| | | | | | | This avoids some unnecessary copies of shared_ptrs. Those changes were suggested post-commit for D47463. llvm-svn: 334656
* [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.Clement Courbet2018-06-131-2/+16
| | | | | | | | | | | | | | | | | | | | | Summary: For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files. For more obvious cases, I've ventured a fix. Some notes: - Exynos is especially fishy. - AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice. - The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit. Also see PR37310. Reviewers: RKSimon, craig.topper, javed.absar Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46356 llvm-svn: 334586
* [X86] Mark all instructions that have masked store semantics with ↵Craig Topper2018-06-131-16/+2
| | | | | | | | NotMemoryFoldable. Remove dependency on SchedRW from memory table autogenerator. Previously we were whitelisting in instructions based on their SchedRW value. With the masked store instructions explicitly removed via NotMemoryFoldable, we don't seem to need this check anymore. llvm-svn: 334563
* [X86] Remove unnecessary include from one of the tblgen emitters.Craig Topper2018-06-121-1/+0
| | | | llvm-svn: 334530
* [X86] Don't add stores to the autogenerated load folding tables if the ↵Craig Topper2018-06-121-1/+2
| | | | | | | | register and memory operands have different widths. This can cause the amount of the memory written to be changed which would be bad. llvm-svn: 334480
* [X86] Update folding table generator to properly detect RMW arithmetic ↵Craig Topper2018-06-121-2/+4
| | | | | | | | | | instructions. The RMW instructions are detected by reading the SchedRW data, but the RMW instructions have had their SchedRW changed in recent months. This broke the expectation. We probably should fix this to use the mayLoad/mayStore flags if possible. llvm-svn: 334478
* [X86] Enforce agreement of AdSize field when autogenerating load folding ↵Craig Topper2018-06-121-0/+1
| | | | | | table entries. llvm-svn: 334473
* TableGen: Change some pointer parameters to references since they're never ↵David Blaikie2018-06-112-21/+22
| | | | | | null anyway llvm-svn: 334446
* [TableGen] Make better use of std::map::emplace and emplace construct the ↵Craig Topper2018-06-101-9/+10
| | | | | | object in the map rather than moving it into it. Remove a use std::map::find by remembering the return from emplace. llvm-svn: 334380
* [TableGen] Combine two constructors by taking vectors by value instead of ↵Craig Topper2018-06-101-11/+3
| | | | | | trying to support combininations for rvalue and lvalue references. llvm-svn: 334379
* Revert r334374 [TableGen] Move some shared_ptrs to avoid unnecessary copies ↵Florian Hahn2018-06-102-26/+21
| | | | | | | | (NFC). This breaks some builders. llvm-svn: 334376
* [TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).Florian Hahn2018-06-102-21/+26
| | | | | | Those changes were suggested post-commit for D47463. llvm-svn: 334374
* [tablegen] Improve performance on *GenRegisterInfo.inc by replacing ↵Daniel Sanders2018-06-081-3/+3
| | | | | | | | | | | | | | | | SparseVector with BitVector. NFC Summary: Generating X86GenRegisterInfo.inc and AArch64GenRegisterInfo.inc is 8-9% faster on my build. Reviewers: bogner, javed.absar Reviewed By: bogner Subscribers: llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D47907 llvm-svn: 334337
* [TableGen] Make DAGInstruction own Pattern to avoid leaking it.Florian Hahn2018-06-082-11/+13
| | | | | | | | | | Reviewers: dsanders, craig.topper, stoklund, nhaehnle Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47525 llvm-svn: 334275
* [X86] Rename vy512mem->vy512xmem and vz256xmem->vz256mem.Craig Topper2018-06-061-4/+4
| | | | | | | | | | | The index size is represented by the letter after the 'v'. The number represents the memory size. If an 'x' appears after the number its means the index register can be from VR128X/VR256X instead of VR128/VR256. As vy512mem uses a VR256X index it should have an x. And vz256mem uses a VR512 index so it shouldn't have an x. I admit these names kind of suck and are confusing. llvm-svn: 334120
* TableGen/DAGPatterns: Allow bit constants in addition to int constantsNicolai Haehnle2018-06-041-3/+5
| | | | | | | | | | | | | | | Summary: Implicit casting is a simple quality of life improvement. Change-Id: I3d2b31b8b8f12cbb1e84f691e359fa713a9c4b42 Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D47432 llvm-svn: 333904
* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-311-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* [TableGen] Avoid leaking TreePatternNodes by using shared_ptr.Florian Hahn2018-05-303-234/+229
| | | | | | | | | | | | By using std::shared_ptr for TreePatternNode, we can avoid leaking them. Reviewers: craig.topper, dsanders, stoklund, tstellar, zturner Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47463 llvm-svn: 333591
* [TableGen] Use explicit constructor for InstMemoFlorian Hahn2018-05-291-2/+8
| | | | | | | This should fix a few buildbot failures with old GCC versions. llvm-svn: 333448
* [TableGen] Fix leaking of PhysRegInputs.Florian Hahn2018-05-291-13/+17
| | | | | | | | | | | | | Instead of dynamically allocating the vector for PhysRegs, we can allocate it on the stack and move it into InstructionMemo. Reviewers: mcrosier, craig.topper, RKSimon, dsanders Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47461 llvm-svn: 333438
* [TableGen] Fix leaking synthesized registers.Florian Hahn2018-05-292-2/+15
| | | | | | | | | | | | | By keeping track of unique_ptrs to the synthesized definitions in CodeGenRegBank we avoid leaking them. Reviewers: dsanders, kparzysz, stoklund Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47462 llvm-svn: 333434
* [Tablegen] Avoid generating empty switch statements. NFCAndrea Di Biagio2018-05-271-4/+10
| | | | | | | This fixes an MSVC warning (warning C4065: switch statement contains 'default' but no 'case' labels) introduced with revision 333293. llvm-svn: 333363
* [Tablegen][SubtargetEmitter] Add a default case to the auto-generated switch ↵Andrea Di Biagio2018-05-251-1/+3
| | | | | | in MCSubtargetInfo::resolveVariantSchedClass(). NFC llvm-svn: 333293
* [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling ↵Andrea Di Biagio2018-05-252-1/+79
| | | | | | | | | | | | | | | | | | | | classes. This patch is the second of a sequence of three patches related to LLVM-dev RFC "MC support for varinat scheduling classes". https://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to enable the resolution of variant classes in MC with the help of a new method named `MCSubtargetInfo::resolveVariantSchedClass()`. This patch also teaches the SubtargetEmitter how to automatically generate the definition of method resolveVariantSchedClass(). That definition is emitted within a sub-class of MCSubtargetInfo named XXXGenMCSubtargetInfo (where XXX is the name of the Target). Differential Revision: https://reviews.llvm.org/D47077 llvm-svn: 333286
* [RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.Andrea Di Biagio2018-05-255-33/+447
| | | | | | | | | | | | | | | | | | | | | | This patch is the first of a sequence of three patches described by the LLVM-dev RFC "MC support for variant scheduling classes". http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html The goal of this patch is to introduce a new class of scheduling predicates for SchedReadVariant and SchedWriteVariant. An MCSchedPredicate can be used instead of a normal SchedPredicate to model checks on the instruction (either a MachineInstr or a MCInst). Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition. MCInstPredicate allows the definition of expressions with a well-known semantic, that can be used to generate code for both MachineInstr and MCInst. This is the first step toward teaching to tools like lllvm-mca how to resolve variant scheduling classes. Differential Revision: https://reviews.llvm.org/D46695 llvm-svn: 333282
* [GlobalISel][InstructionSelect] Switching over root LLTs, perf patch 10Roman Tereshin2018-05-241-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | This patch continues a series of patches started by r332907 (reapplied as r332917). In this commit we introduce new matching opcode for the MatchTable: GIM_SwitchType, similar to GIM_SwitchOpcode, and use it to switch over LLTs of def operands of root instructions on the 2nd level of the MatchTable within GIM_SwitchOpcode's cases. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by about 6.5% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64 (cross-compile on x86). Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333146
* [GlobalISel][InstructionSelect] Moving Reg Bank Checks forward, perf patch 9Roman Tereshin2018-05-231-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch continues a series of patches started by r332907 (reapplied as r332917). In this commit we move register bank checks back from epilogue of every rule matcher to a position locally close to the rest of the checks for a particular (nested) instruction. This increases the number of common conditions within 2nd level groups. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by about 2% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64 (cross-compile on x86). Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333144
* [GlobalISel][InstructionSelect] Maximizing # of Group's common conditions, ↵Roman Tereshin2018-05-231-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | perf patch 8 This patch continues a series of patches started by r332907 (reapplied as r332917). In this commit we greedily stuff 2nd level GroupMatcher's common conditions with as many predicates as possible. This is purely post-processing and it doesn't change which rules are put into the groups in the first place: that decision is made by looking at the first common predicate only. The compile time improvements are minor and well within error margin, however, it's highly improbable that this transformation could pessimize performance, thus I'm still committing it for potential gains for targets not implementing GlobalISel yet and out of tree targets. Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333139
* [GlobalISel][Tablegen] Assign small opcodes to pseudosRoman Tereshin2018-05-233-15/+38
| | | | | | | | | | | | | | Sort pseudo instructions first while emitting enum's for target instructions info. That puts them close to each other and to generic G_* opcodes for GlobalISel. This makes it easier to build small jump tables over opcodes that could be directly embedded into MatchTable's Tablegen'erated for GlobalISel's InstructionSelect. Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D47240 llvm-svn: 333135
* [GlobalISel][InstructionSelect] Sorting MatchTable's 2nd level by root LLT, ↵Roman Tereshin2018-05-231-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | perf patch 7 This patch continues a series of patches started by r332907 (reapplied as r332917). In this commit we sort rules within their 2nd level by the type check on def operand of the root instruction, which allows for better nesting grouping on the level. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by roughly 22% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64 (cross-compile on x86). Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333131
* [Tablegen] Tidying up InstRegexOp a little, NFCRoman Tereshin2018-05-232-15/+16
| | | | | | Differential Review: https://reviews.llvm.org/D47240 llvm-svn: 333121
* [GlobalISel][InstructionSelect] Moving type checks forward, perf patch 6Roman Tereshin2018-05-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch continues a series of patches started by r332907 (reapplied as r332917) In this commit we sort type checks towards the beginning of every rule within the MatchTable as they fail often and it's best to fail early. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by roughly 7% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64. The amalgamation is a large single-file C-source that makes compiler backend performance improvements to stand out from frontend. It's also a part of CTMark. Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333114
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-233-0/+3
| | | | | | | | | | | | | This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 llvm-svn: 333093
* Remove DEBUG macro.Nicola Zaghen2018-05-231-1/+1
| | | | | | | | | | Now that the LLVM_DEBUG() macro landed on the various sub-projects the DEBUG macro can be removed. Also change the new uses of DEBUG to LLVM_DEBUG. Differential Revision: https://reviews.llvm.org/D46952 llvm-svn: 333091
* [GlobalISel][InstructionSelect] MatchTable second level grouping, perf patch 5Roman Tereshin2018-05-231-1/+14
| | | | | | | | | | | | | | | | | | | | | | | This patch continues a series of patches started by r332907 (reapplied as r332917) In this commit we start grouping rules with common first condition on the second level of the table. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by roughly 13% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64. Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333053
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