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| author | Florian Hahn <florian.hahn@arm.com> | 2018-05-29 16:55:06 +0000 |
|---|---|---|
| committer | Florian Hahn <florian.hahn@arm.com> | 2018-05-29 16:55:06 +0000 |
| commit | 6c21b3b5950705021255095ebb6c08402c776184 (patch) | |
| tree | 175a2fa8ba78e07c4dddd72a34f63291173ea0b4 /llvm/utils/TableGen | |
| parent | b1bb60aec99a39cc8e9abb7a1c4a5466639a2651 (diff) | |
| download | bcm5719-llvm-6c21b3b5950705021255095ebb6c08402c776184.tar.gz bcm5719-llvm-6c21b3b5950705021255095ebb6c08402c776184.zip | |
[TableGen] Fix leaking synthesized registers.
By keeping track of unique_ptrs to the synthesized definitions in
CodeGenRegBank we avoid leaking them.
Reviewers: dsanders, kparzysz, stoklund
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D47462
llvm-svn: 333434
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenRegisters.cpp | 14 | ||||
| -rw-r--r-- | llvm/utils/TableGen/CodeGenRegisters.h | 3 |
2 files changed, 15 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp index b7833d017e1..273aefd6128 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/CodeGenRegisters.cpp @@ -605,6 +605,13 @@ unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const { namespace { struct TupleExpander : SetTheory::Expander { + // Reference to SynthDefs in the containing CodeGenRegBank, to keep track of + // the synthesized definitions for their lifetime. + std::vector<std::unique_ptr<Record>> &SynthDefs; + + TupleExpander(std::vector<std::unique_ptr<Record>> &SynthDefs) + : SynthDefs(SynthDefs) {} + void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override { std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); unsigned Dim = Indices.size(); @@ -649,7 +656,9 @@ struct TupleExpander : SetTheory::Expander { // Create a new Record representing the synthesized register. This record // is only for consumption by CodeGenRegister, it is not added to the // RecordKeeper. - Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); + SynthDefs.emplace_back( + llvm::make_unique<Record>(Name, Def->getLoc(), Def->getRecords())); + Record *NewReg = SynthDefs.back().get(); Elts.insert(NewReg); // Copy Proto super-classes. @@ -1075,7 +1084,8 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records, // Configure register Sets to understand register classes and tuples. Sets.addFieldExpander("RegisterClass", "MemberList"); Sets.addFieldExpander("CalleeSavedRegs", "SaveList"); - Sets.addExpander("RegisterTuples", llvm::make_unique<TupleExpander>()); + Sets.addExpander("RegisterTuples", + llvm::make_unique<TupleExpander>(SynthDefs)); // Read in the user-defined (named) sub-register indices. // More indices will be synthesized later. diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h index e6f613cd49f..32aa33c80b3 100644 --- a/llvm/utils/TableGen/CodeGenRegisters.h +++ b/llvm/utils/TableGen/CodeGenRegisters.h @@ -562,6 +562,9 @@ namespace llvm { // Give each register unit set an order based on sorting criteria. std::vector<unsigned> RegUnitSetOrder; + // Keep track of synthesized definitions generated in TupleExpander. + std::vector<std::unique_ptr<Record>> SynthDefs; + // Add RC to *2RC maps. void addToMaps(CodeGenRegisterClass*); |

