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* Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for ↵Simon Pilgrim2019-09-091-92/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | packetized instructions This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936 ........ Reverted as this is causing "compiler out of heap space" errors on MSVC 2017/19 NDEBUG builds llvm-svn: 371393
* GlobalISel: Support physical register inputs in patternsMatt Arsenault2019-09-063-11/+177
| | | | llvm-svn: 371253
* [DFAPacketizer] Track resources for packetized instructionsJames Molloy2019-09-061-48/+92
| | | | | | | | | | | | | | | | | | | | | | This patch allows the DFAPacketizer to be queried after a packet is formed to work out which resources were allocated to the packetized instructions. This is particularly important for targets that do their own bundle packing - it's not sufficient to know simply that instructions can share a packet; which slots are used is also required for encoding. This extends the emitter to emit a side-table containing resource usage diffs for each state transition. The packetizer maintains a set of all possible resource states in its current state. After packetization is complete, all remaining resource states are possible packetization strategies. The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default (most uses of the packetizer like MachinePipeliner don't care and don't need the extra maintained state). Differential Revision: https://reviews.llvm.org/D66936 llvm-svn: 371198
* GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraintsMatt Arsenault2019-09-061-19/+47
| | | | | | | | | | | | | | | | This was only using the correct register constraints if this was the final result instruction. If the extract was a sub instruction of the result, it would attempt to use GIR_ConstrainSelectedInstOperands on a COPY, which won't work. Move the handling to createAndImportSubInstructionRenderer so it works correctly. I don't fully understand why runOnPattern and createAndImportSubInstructionRenderer both need to handle these special cases, and constrain them with slightly different methods. If I remove the runOnPattern handling, it does break the constraint when the final result instruction is EXTRACT_SUBREG. llvm-svn: 371150
* GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patternsMatt Arsenault2019-09-041-25/+31
| | | | | | | | This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
* [DFAPacketizer] Allow namespacing of automata per-itineraryJames Molloy2019-08-301-24/+41
| | | | | | | | | | | | | | | | | | | | | The Hexagon itineraries are cunningly crafted such that functional units between itineraries do not clash. Because all itineraries are bundled into the same DFA, a functional unit index clash would cause an incorrect DFA to be generated. A workaround for this is to ensure all itineraries declare the universe of all possible functional units, but this isn't ideal for three reasons: 1) We only have a limited number of FUs we can encode in the packetizer, and using the universe causes us to hit the limit without care. 2) Silent codegen faults are bad, and careful triage of the FU list shouldn't be required. 3) Smooshing all itineraries into the same automaton allows combinations of instruction classes that cannot exist, which bloats the table. A simple solution is to allow "namespacing" packetizers. Differential Revision: https://reviews.llvm.org/D66940 llvm-svn: 370508
* [ValueTypes] Add v16f16 and v32f16 to EVT::getEVTString and Tablegen's ↵Craig Topper2019-08-301-0/+2
| | | | | | | | getEnumName Missed these when I hadded the enum entries llvm-svn: 370494
* GlobalISel/TableGen: Handle setcc patternsMatt Arsenault2019-08-291-1/+68
| | | | | | | | | | | This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
* Add tie-breaker for register class sorting in getSuperRegForSubRegJessica Paquette2019-08-281-1/+8
| | | | | | | | | | | | llvm::stable_sort is apparently not sufficient. Use the same tie-breaker/sorting style as TopoOrderRC fix bot failures. E.g. http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19401/steps/test-check-all/logs/stdio llvm-svn: 370267
* [GlobalISel] Import patterns containing SUBREG_TO_REGJessica Paquette2019-08-281-19/+85
| | | | | | | | | | | | | | | | | | | | | | | Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
* Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG"Jessica Paquette2019-08-273-1/+235
| | | | | | | | | | I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
* Revert "[GlobalISel] Import patterns containing INSERT_SUBREG"Jessica Paquette2019-08-273-235/+1
| | | | | | | | | | When EXPENSIVE_CHECKS are enabled, GlobalISelEmitterSubreg.td doesn't get stable output. Reverting while I debug it. See: https://reviews.llvm.org/D66498 llvm-svn: 370080
* [IntrinsicEmitter] Support scalable vectors in intrinsicsCullen Rhodes2019-08-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds support for scalable vectors in intrinsics, enabling intrinsics such as the following to be defined: declare <vscale x 4 x i32> @llvm.something.nxv4i32(<vscale x 4 x i32>) Support for this is implemented by defining a new type descriptor for scalable vectors and adding mangling support for scalable vector types in the name mangling scheme used by 'any' types in intrinsic signatures. Tests have been added for IRBuilder to test scalable vectors work as expected when using intrinsics through this interface. This required implementing an intrinsic that is explicitly defined with scalable vectors, e.g. LLVMType<nxv4i32>, an SVE floating-point convert intrinsic was used for this. The behaviour of the overloaded type LLVMScalarOrSameVectorWidth with scalable vectors is tested using the existing masked load intrinsic. Also added an .ll test to test the Verifier catches a bad intrinsic argument when passing a fixed-width predicate (mask) to the masked.load intrinsic where a scalable is expected. Patch by Paul Walker Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D65930 llvm-svn: 370053
* [GlobalISel] Import patterns containing INSERT_SUBREGJessica Paquette2019-08-263-1/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This teaches the importer to handle INSERT_SUBREG instructions. We were missing patterns involving INSERT_SUBREG in AArch64. It appears in AArch64InstrInfo.td 107 times, and 14 times in AArch64InstrFormats.td. To meaningfully import it, the GlobalISelEmitter needs to know how to infer a super register class for a given register class. This patch introduces the following: - `getSuperRegForSubReg`, a function which finds the largest register class which supports a value type and subregister index - `inferSuperRegisterClass`, a function which finds the appropriate super register class for an INSERT_SUBREG' - `inferRegClassFromPattern`, a function which allows for some trivial lookthrough into instructions - `getRegClassFromLeaf`, a helper function which returns the register class for a leaf `TreePatternNode` - Support for subregister index operands in `importExplicitUseRenderer` It also - Updates tests in each backend which are impacted by the change - Adds GlobalISelEmitterSubreg.td to test that we import and skip the expected patterns As a result of this patch, INSERT_SUBREG patterns in X86 may use the LOW32_ADDR_ACCESS_RBP register class instead of GR32. This is correct, since the register class contains the same registers as GR32 (except with the addition of RBP). So, this also teaches X86 to handle that register class. This is in line with X86ISelLowering, which treats this as a GR class. Differential Revision: https://reviews.llvm.org/D66498 llvm-svn: 369973
* [TableGen] Correct comments for end of namespace. NFCBjorn Pettersson2019-08-2510-29/+29
| | | | | | | | | | | | | | | | | | | | | | Summary: Update end-of-namespace comments generated by tablegen emitters to fulfill the rules setup by clang-tidy's llvm-namespace-comment checker. Fixed a few end-of-namespace comments in the tablegen source code as well. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: craig.topper, stoklund, dschuff, sbc100, jgravelle-google, aheejin, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66396 llvm-svn: 369865
* Use a bit of relaxed constexpr to make FeatureBitset costant intializableBenjamin Kramer2019-08-244-6/+6
| | | | | | | | | | | This requires std::intializer_list to be a literal type, which it is starting with C++14. The downside is that std::bitset is still not constexpr-friendly so this change contains a re-implementation of most of it. Shrinks clang by ~60k. llvm-svn: 369847
* Retire llvm::less_ptr. llvm::deref is much more flexible.Benjamin Kramer2019-08-221-1/+1
| | | | llvm-svn: 369675
* Retire llvm::less/equal in favor of C++14 std::less<>/equal_to<>.Benjamin Kramer2019-08-224-18/+21
| | | | llvm-svn: 369674
* Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operandsJessica Paquette2019-08-203-7/+30
| | | | | | | | | | | | | | Overloaded intrinsics can use iPTRAny in used/input operands. The GlobalISelEmitter doesn't know that these are pointers, so it treats them as scalars. As a result, these intrinsics can't be imported. This teaches the GlobalISelEmitter to recognize these as pointers rather than scalars. Differential Revision: https://reviews.llvm.org/D65756 llvm-svn: 369455
* TableGen: Revert changes from r369038Matt Arsenault2019-08-181-3/+1
| | | | | | | These aren't needed for a specific use yet, and I meant to not commit these. llvm-svn: 369201
* MVT: Add v3i16/v3f16 vectorsMatt Arsenault2019-08-152-1/+5
| | | | | | | | | | | | AMDGPU has some buffer intrinsics which theoretically could use this. Some of the generated tables include the 3 and 4 element vector versions of these rounded to 64-bits, which is ambiguous. Add these to help the table disambiguate these. Assertion change is for the path odd sized vectors now take for R600. v3i16 is widened to v4i16, which then needs to be promoted to v4i32. llvm-svn: 369038
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-1511-36/+36
| | | | | | | | Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
* [Intrinsics] Add a 'NoAlias' intrinsic property; annotate llvm.memcpyDavid Bolvansky2019-08-143-0/+10
| | | | | | | | | | Reviewers: jdoerfert Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D66158 llvm-svn: 368810
* [TableGen] Correct the shift to the proper bit width.Michael Liao2019-08-101-1/+1
| | | | | | - Replace the previous 32-bit shift with 64-bit one matching `OpInit`. llvm-svn: 368513
* [TableGen] Add "InitValue": Handle operands with set bit values in decoder ↵Daniel Sanders2019-08-091-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | methods Summary: The problem: When an operand had bits explicitly set to "1" (as in the InitValue.td test case attached), the decoder was ignoring those bits, and the DecoderMethod was receiving an input where the bits were still zero. The solution: We added an "InitValue" variable that stores the initial value of the operand based on what bits were explicitly initialized to 1 in TableGen code. The generated decoder code then uses that initial value to initialize the "tmp" variable, then calls fieldFromInstruction to read the values for the remaining bits that were left unknown in TableGen. This is mainly useful when there are variations of an instruction that differ based on what bits are set in the operands, since this change makes it possible to access those bits in a DecoderMethod. The DecoderMethod can use those bits to know how to handle the input. Patch by Nicolas Guillemot Reviewers: craig.topper, dsanders, fhahn Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D63741 llvm-svn: 368458
* [X86] Limit vpermil2pd/vpermil2ps immediates to 4 bits in the assembly parser.Craig Topper2019-08-071-0/+2
| | | | | | | | | | The upper 4 bits of the immediate byte are used to encode a register. We need to limit the explicit immediate to fit in the remaining 4 bits. Fixes PR42899. llvm-svn: 368123
* [GlobalISel] Check LLT size matches memory size for non-truncating stores.Amara Emerson2019-08-021-5/+13
| | | | | | | | This was causing a bug where non-truncating stores would be selected instead of truncating ones. Differential Revision: https://reviews.llvm.org/D64845 llvm-svn: 367737
* TableGen: Add MinAlignment predicateMatt Arsenault2019-07-313-2/+65
| | | | | | | | | | AMDGPU uses some custom code predicates for testing alignments. I'm still having trouble comprehending the behavior of predicate bits in the PatFrag hierarchy. Any attempt to abstract these properties unexpectdly fails to apply them. llvm-svn: 367373
* AMDGPU: Avoid emitting "true" predicatesMatt Arsenault2019-07-304-4/+15
| | | | | | | | | | Empty condition strings are considerde always true. This removes a lot of clutter from the generated matcher tables. This shrinks the source size of AMDGPUGenDAGISel.inc from 7.3M to 6.1M. llvm-svn: 367326
* TableGen: Support physical register inputs > 255Matt Arsenault2019-07-223-11/+27
| | | | | | | This was truncating register value that didn't fit in unsigned char. Switch AMDGPU sendmsg intrinsics to using a tablegen pattern. llvm-svn: 366695
* [AMDGPU] Allow register tuples to set asm namesStanislav Mekhanoshin2019-07-191-3/+12
| | | | | | | | | | | | This change reverts most of the previous register name generation. The real problem is that RegisterTuple does not generate asm names. Added optional operand to RegisterTuple. This way we can simplify register name access and dramatically reduce the size of static tables for the backend. Differential Revision: https://reviews.llvm.org/D64967 llvm-svn: 366598
* [Attributor] Deduce "willreturn" function attributeHideto Ueno2019-07-173-2/+18
| | | | | | | | | | | | | | | | | Summary: Deduce the "willreturn" attribute for functions. For now, intrinsics are not willreturn. More annotation will be done in another patch. Reviewers: jdoerfert Subscribers: jvesely, nhaehnle, nicholas, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63046 llvm-svn: 366335
* [TableGen] Do not set ReadNone attribute on intrinsics with side effectsMomchil Velikov2019-07-172-2/+4
| | | | | | | | | | | If an intrinsic is defined without outputs, but having side effects, it still can be removed completely from the program. This patch makes TableGen not set Attribute::ReadNone for intrinsics which are declared with IntrHasSideEffects. Differential Revision: https://reviews.llvm.org/D64414 llvm-svn: 366312
* [TableGen] Generate offsets into a flat array for getOperandTypeJustin Bogner2019-07-161-25/+38
| | | | | | | | | | Rather than an array of std::initializer_list, generate a table of offsets and a flat array of the operands for getOperandType. This is a bit more efficient on platforms that don't manage to get the array of inintializer_lists initialized at link time (I'm looking at you macOS). It's also quite quite a bit faster to compile. llvm-svn: 366278
* [TableGen] Add "getOperandType" to get operand types from opcode/opidxJustin Bogner2019-07-161-4/+57
| | | | | | | | | | | | | The InstrInfoEmitter outputs an enum called "OperandType" which gives numerical IDs to each operand type. This patch makes use of this enum to define a function called "getOperandType", which allows looking up the type of an operand given its opcode and operand index. Patch by Nicolas Guillemot. Thanks! Differential Revision: https://reviews.llvm.org/D63320 llvm-svn: 366274
* [WebAssembly] Rename except_ref type to exnrefHeejin Ahn2019-07-151-1/+1
| | | | | | | | | | | | | | | | | | | Summary: We agreed to rename `except_ref` to `exnref` for consistency with other reference types in https://github.com/WebAssembly/exception-handling/issues/79. This also renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order to use the file for other reference types in future. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64703 llvm-svn: 366145
* TableGen/GlobalISel: Fix handling of truncstore patternsMatt Arsenault2019-07-151-1/+8
| | | | | | | | | | | | This was failing to import the AMDGPU truncstore patterns. The truncating stores from 32-bit to 8/16 were then somehow being incorrectly selected to a 4-byte store. A separate check is emitted for the LLT size in comparison to the specific memory VT, which looks strange to me but makes sense based on the hierarchy of PatFrags used for the default truncstore PatFrags. llvm-svn: 366129
* TableGen: Add address space to matchersMatt Arsenault2019-07-153-4/+113
| | | | | | | | | | | | | | | | | Currently AMDGPU uses a CodePatPred to check address spaces from the MachineMemOperand. Introduce a new first class property so that the existing patterns can be easily modified to uses the new generated predicate, which will also be handled for GlobalISel. I would prefer these to match against the pointer type of the instruction, but that would be difficult to get working with SelectionDAG compatbility. This is much easier for now and will avoid a painful tablegen rewrite for all the loads and stores. I'm also not sure if there's a better way to encode multiple address spaces in the table, rather than putting the number to expect. llvm-svn: 366128
* [CodeGen] Add larger vector types for i32 and f32David Majnemer2019-07-071-0/+12
| | | | | | | | | | Some out of tree backend require larger vector type. Since maintaining the changes out of tree is difficult due to the many manual changes needed when adding a new type we are adding it even if no backend currently use it. Differential Revision: https://reviews.llvm.org/D64141 Patch by Thomas Raoux! llvm-svn: 365274
* [TableGen] Allow DAG isel patterns to override default operands.Simon Tatham2019-07-043-10/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a Tablegen instruction description uses `OperandWithDefaultOps`, isel patterns for that instruction don't have to fill in the default value for the operand in question. But the flip side is that they actually //can't// override the defaults even if they want to. This will be very inconvenient for the Arm backend, when we start wanting to write isel patterns that generate the many MVE predicated vector instructions, in the form with predication actually enabled. So this small Tablegen fix makes it possible to write an isel pattern either with or without values for a defaulted operand, and have the default values filled in only if they are not overridden. If all the defaulted operands come at the end of the instruction's operand list, there's a natural way to match them up to the arguments supplied in the pattern: consume pattern arguments until you run out, then fill in any missing instruction operands with their default values. But if defaulted and non-defaulted operands are interleaved, it's less clear what to do. This does happen in existing targets (the first example I came across was KILLGT, in the AMDGPU/R600 backend), and of course they expect the previous behaviour (that the default for those operands is used and a pattern argument is not consumed), so for backwards compatibility I've stuck with that. Reviewers: nhaehnle, hfinkel, dmgreen Subscribers: mehdi_amini, javed.absar, tpr, kristof.beyls, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63814 llvm-svn: 365114
* Teach TableGen Intrin Emitter to handle LLVMPointerType<llvm_any_ty>Erich Keane2019-06-261-0/+3
| | | | | | | | | | r363233 rewrote a bunch of the Intrin Emitter code, however the new function to update the arg codes did not properly consider a pointer to an any. This patch adds that logic. Differential Revision: https://reviews.llvm.org/D63507 llvm-svn: 364364
* Re-commit r363744: [tblgen][disasm] Allow multiple encodings to disassemble ↵Daniel Sanders2019-06-181-45/+95
| | | | | | | | | | | | | | to the same instruction It seems macOS lets you have ArrayRef<const X> even though this is apparently forbidden by the language standard (Thanks MSVC++ for the clear error message). Removed the problematic const's to fix this. (It also seems I'm not receiving buildbot emails anymore and I'm trying to find out why. In the mean time I'll be polling lab.llvm.org to hopefully see if/when failures occur) llvm-svn: 363753
* Revert [tblgen][disasm] Allow multiple encodings to disassemble to the same ↵Jordan Rupprecht2019-06-181-98/+48
| | | | | | | | | | instruction This reverts r363744 (git commit 9b2252123d1e79d2b3594097a9d9cc60072b83d9) This breaks many buildbots, e.g. http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/203/steps/build%20stage%201/logs/stdio llvm-svn: 363747
* [tblgen][disasm] Allow multiple encodings to disassemble to the same instructionDaniel Sanders2019-06-181-48/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add an AdditionalEncoding class which can be used to define additional encodings for a given instruction. This causes the disassembler to add an additional encoding to its matching tables that map to the specified instruction. Usage: def ADD1 : Instruction { bits<8> Reg; bits<32> Inst; let Size = 4; let Inst{0-7} = Reg; let Inst{8-14} = 0; let Inst{15} = 1; // Continuation bit let Inst{16-31} = 0; ... } def : AdditionalEncoding<ADD1> { bits<8> Reg; bits<16> Inst; // You can also have bits<32> and it will still be a 16-bit encoding let Size = 2; let Inst{0-3} = 0; let Inst{4-7} = Reg; let Inst{8-15} = 0; ... } with those definitions, llvm-mc will successfully disassemble both of these: 0x01 0x00 0x10 0x80 0x00 0x00 to: ADD1 r1 Depends on D52366 Reviewers: bogner, charukcs Reviewed By: bogner Subscribers: nlguillemot, nhaehnle, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D52369 llvm-svn: 363744
* [X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ↵Craig Topper2019-06-131-51/+23
| | | | | | | | | | ATTR_VEXL/ATTR_EVEXL bits. NFCI Merging the two bits shrinks the context table from 16384 bytes to 8192 bytes. Remove the ATTRIBUTE_BITS macro and just create an enum directly. Then fix the ATTR_max define to be 8192 to reflect the table size so we stop hardcoding it separately. llvm-svn: 363330
* Improve reduction intrinsics by overloading result value.Sander de Smalen2019-06-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
* [IntrinsicEmitter] Extend argument overloading with forward references.Sander de Smalen2019-06-132-23/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the mechanism to overload intrinsic arguments by using either backward or forward references to the overloadable arguments. In for example: def int_something : Intrinsic<[LLVMPointerToElt<0>], [llvm_anyvector_ty], []>; LLVMPointerToElt<0> is a forward reference to the overloadable operand of type 'llvm_anyvector_ty' and would allow intrinsics such as: declare i32* @llvm.something.v4i32(<4 x i32>); declare i64* @llvm.something.v2i64(<2 x i64>); where the result pointer type is deduced from the element type of the first argument. If the returned pointer is not a pointer to the element type, LLVM will give an error: Intrinsic has incorrect return type! i64* (<4 x i32>)* @llvm.something.v4i32 Reviewers: RKSimon, arsenm, rnk, greened Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62995 llvm-svn: 363233
* [RISCV] Replace map with set in getReqFeaturesSameer AbuAsal2019-06-101-9/+7
| | | | | | | | | | | | | | | | | | | | Summary: Use a set in getReqFeatures() in RISCVCompressInstEmitter instead of a map because the index we save is not needed. This also fixes bug 41666. Reviewers: llvm-commits, apazos, asb, nickdesaulniers Reviewed By: asb Subscribers: Jim, nickdesaulniers, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna Tags: #llvm Differential Revision: https://reviews.llvm.org/D61412 llvm-svn: 362968
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-053-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ISD::STRICT_ nodes used to implement the constrained floating-point intrinsics are currently never passed to the target back-end, which makes it impossible to handle them correctly (e.g. mark instructions are depending on a floating-point status and control register, or mark instructions as possibly trapping). This patch allows the target to use setOperationAction to switch the action on ISD::STRICT_ nodes to Legal. If this is done, the SelectionDAG common code will stop converting the STRICT nodes to regular floating-point nodes, but instead pass the STRICT nodes to the target using normal SelectionDAG matching rules. To avoid having the back-end duplicate all the floating-point instruction patterns to handle both strict and non-strict variants, we make the MI codegen explicitly aware of the floating-point exceptions by introducing two new concepts: - A new MCID flag "mayRaiseFPException" that the target should set on any instruction that possibly can raise FP exception according to the architecture definition. - A new MI flag FPExcept that CodeGen/SelectionDAG will set on any MI instruction resulting from expansion of any constrained FP intrinsic. Any MI instruction that is *both* marked as mayRaiseFPException *and* FPExcept then needs to be considered as raising exceptions by MI-level codegen (e.g. scheduling). Setting those two new flags is straightforward. The mayRaiseFPException flag is simply set via TableGen by marking all relevant instruction patterns in the .td files. The FPExcept flag is set in SDNodeFlags when creating the STRICT_ nodes in the SelectionDAG, and gets inherited in the MachineSDNode nodes created from it during instruction selection. The flag is then transfered to an MIFlag when creating the MI from the MachineSDNode. This is handled just like fast-math flags like no-nans are handled today. This patch includes both common code changes required to implement the new features, and the SystemZ implementation. Reviewed By: andrew.w.kaylor Differential Revision: https://reviews.llvm.org/D55506 llvm-svn: 362663
* [TableGen] Fix std::array initializer to avoid warnings with older tool ↵Mikael Holmen2019-06-031-1/+1
| | | | | | | | | | | | | chains. NFC A std::array is implemented as a template with an array inside a struct. Older versions of clang, like 3.6, require an extra set of curly braces around std::array initializations to avoid warnings. The C++ language was changed regarding this by CWG 1270. So more modern tool chains does not complain even if leaving out one level of braces. llvm-svn: 362360
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