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path: root/llvm/utils/TableGen
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* [X86] Add all of the MRM_C0-MRM_FF forms to the switch in RecognizableInstr::...Craig Topper2018-03-121-27/+20
* [MCSchedule] Always generate processor resource names.Andrea Di Biagio2018-03-081-2/+2
* [WebAssembly] Add except_ref as a first-class typeHeejin Ahn2018-03-081-0/+1
* TableGen: Use DefInit::getDef() instead of the type's getRecord()Nicolai Haehnle2018-03-051-14/+11
* Shrink various scheduling tables by using narrower types.Benjamin Kramer2018-02-231-7/+12
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-233-3/+14
* Fix signed/unsigned comparison warning in AsmGenMatcher generated code. NFCI.Simon Pilgrim2018-02-171-4/+4
* [GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAGAditya Nandakumar2018-02-161-0/+12
* [X86][3DNOW] Teach decoder about AMD 3DNow! instrsRafael Auler2018-02-153-21/+30
* [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the...Craig Topper2018-02-131-1/+19
* [TargetSchedule] Fix r324582.Clement Courbet2018-02-091-1/+1
* Fix missing field initializer warning in TableGen SubtargetEmitterDavid Blaikie2018-02-081-3/+4
* [TargetSchedule] Expose sub-units of a ProcResGroup in MCProcResourceDesc.Clement Courbet2018-02-081-3/+39
* [CodeGenSchedule][NFC] Always emit ProcResourceUnits.Clement Courbet2018-02-051-0/+8
* [TableGen][AsmMatcherEmitter] Fix tied-constraint checking for InstAliasesSander de Smalen2018-02-041-154/+188
* [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from D...Daniel Sanders2018-01-291-6/+9
* [TableGen][NFC]Remove dead variable.Clement Courbet2018-01-261-1/+0
* [GlobalISel][TableGen] Fix the statistics for emitted pattersVolkan Keles2018-01-251-3/+3
* [TableGen] Add a way of getting the number of generic opcodes without includi...Benjamin Kramer2018-01-243-9/+18
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-241-1/+1
* [TableGen] Optimize the regex search.Benjamin Kramer2018-01-231-20/+76
* [globalisel][tablegen] Honour priority order within nested instructions.Daniel Sanders2018-01-171-0/+13
* [GlobalISel][TableGen] Add support for SDNodeXFormVolkan Keles2018-01-161-26/+106
* [X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode ...Craig Topper2018-01-161-2/+0
* [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operandsSander de Smalen2018-01-101-0/+155
* [mips] Improve diagnostics for instruction mappingAleksandar Beserminji2018-01-081-1/+6
* [X86] Don't put any EVEX_B instructions in the tablegen generated load foldin...Craig Topper2018-01-071-2/+3
* [TableGen] Make the ambiguous match debug messages from the AsmMatcherEmitter...Craig Topper2018-01-061-0/+6
* [TableGen] Add support of Intrinsics with multiple returnsHal Finkel2018-01-031-1/+4
* Avoid int to string conversion in Twine or raw_ostream contexts.Benjamin Kramer2017-12-283-37/+37
* [TableGen] Print more helpful information in case of type contradictionKrzysztof Parzyszek2017-12-212-21/+39
* Do not generate an empty switch statement as it causes MSVC to issue diagnost...Aaron Ballman2017-12-201-4/+7
* TableGen: Allow setting SDNodeProperties on intrinsicsMatt Arsenault2017-12-208-52/+120
* [globalisel][tablegen] Allow ImmLeaf predicates to use InstructionSelector me...Daniel Sanders2017-12-201-12/+22
* [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2Sander de Smalen2017-12-201-11/+15
* Silence a bunch of implicit fallthrough warningsAdrian Prantl2017-12-191-0/+1
* [TableGen][GlobalISel] Reset the internal map of RuleMatchers just before the...Quentin Colombet2017-12-191-3/+4
* [TableGen][GlobalISel] Make the arguments of the Instruction and Operand Matc...Quentin Colombet2017-12-181-18/+18
* [TableGen][GlobalISel] Refactor optimizeRules related bit to allow code reuseQuentin Colombet2017-12-181-12/+23
* Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner2017-12-181-15/+11
* [TableGen][GlobalISel] Optimize MatchTable for faster instruction selectionQuentin Colombet2017-12-181-17/+194
* [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specifiedSander de Smalen2017-12-181-6/+7
* [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled ins...Sander de Smalen2017-12-181-5/+8
* [TableGen][GlobalISel] Make the different Matcher comparableQuentin Colombet2017-12-151-0/+52
* [TableGen][GlobalISel] Fix unused variable warning in release modeQuentin Colombet2017-12-151-0/+1
* [TableGen][GlobalISel] Have the predicate directly know which data they are d...Quentin Colombet2017-12-151-101/+169
* [TableGen][GlobalISel] Add a common class for all PredicateMatcherQuentin Colombet2017-12-141-48/+44
* Add MVT::v128i1, NFCKrzysztof Parzyszek2017-12-141-0/+1
* Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-12-141-3/+2
* Remove redundant includes from utils/TableGen.Michael Zolotukhin2017-12-136-7/+0
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