diff options
| author | Benjamin Kramer <benny.kra@googlemail.com> | 2018-02-23 19:32:56 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2018-02-23 19:32:56 +0000 |
| commit | b941ababce76b2f25599a4e14ba150ae82bf700a (patch) | |
| tree | 9553733b69ceb4333eee805aa164552e8622b172 /llvm/utils/TableGen | |
| parent | 922f2aa9b2f13631febe7167e6db3cd3b421e161 (diff) | |
| download | bcm5719-llvm-b941ababce76b2f25599a4e14ba150ae82bf700a.tar.gz bcm5719-llvm-b941ababce76b2f25599a4e14ba150ae82bf700a.zip | |
Shrink various scheduling tables by using narrower types.
16 bits ought to be enough for everyone. This shrinks clang by ~1MB.
llvm-svn: 325941
Diffstat (limited to 'llvm/utils/TableGen')
| -rw-r--r-- | llvm/utils/TableGen/SubtargetEmitter.cpp | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index c7ccc60acaf..97b8d116868 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -444,7 +444,7 @@ EmitStageAndOperandCycleData(raw_ostream &OS, } // Check to see if stage already exists and create if it doesn't - unsigned FindStage = 0; + uint16_t FindStage = 0; if (NStages > 0) { FindStage = ItinStageMap[ItinStageString]; if (FindStage == 0) { @@ -460,7 +460,7 @@ EmitStageAndOperandCycleData(raw_ostream &OS, } // Check to see if operand cycle already exists and create if it doesn't - unsigned FindOperandCycle = 0; + uint16_t FindOperandCycle = 0; if (NOperandCycles > 0) { std::string ItinOperandString = ItinOperandCycleString+ItinBypassString; FindOperandCycle = ItinOperandMap[ItinOperandString]; @@ -482,10 +482,14 @@ EmitStageAndOperandCycleData(raw_ostream &OS, } // Set up itinerary as location and location + stage count - int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0; - InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages, - FindOperandCycle, - FindOperandCycle + NOperandCycles }; + int16_t NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0; + InstrItinerary Intinerary = { + NumUOps, + FindStage, + uint16_t(FindStage + NStages), + FindOperandCycle, + uint16_t(FindOperandCycle + NOperandCycles), + }; // Inject - empty slots will be 0, 0 ItinList[SchedClassIdx] = Intinerary; @@ -561,7 +565,8 @@ EmitItineraries(raw_ostream &OS, ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; } // End processor itinerary table - OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n"; + OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }" + "// end marker\n"; OS << "};\n"; } } |

